---
_id: '53596'
citation:
  ama: Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. <i>Proceedings
    of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.;
    2019.
  apa: Bringmann, O., Ecker, W., Müller, W., &#38; Müller-Gridschneder, D. (Eds.).
    (2019). <i>Proceedings of the 2nd International Workshop on Embedded Software
    for Industrial IoT - ESIIT</i>.
  bibtex: '@book{Bringmann_Ecker_Müller_Müller-Gridschneder_2019, place={Florence,
    Italy}, title={Proceedings of the 2nd International Workshop on Embedded Software
    for Industrial IoT - ESIIT}, year={2019} }'
  chicago: Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder,
    eds. <i>Proceedings of the 2nd International Workshop on Embedded Software for
    Industrial IoT - ESIIT</i>. Florence, Italy, 2019.
  ieee: O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., <i>Proceedings
    of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.
    Florence, Italy, 2019.
  mla: Bringmann, Oliver, et al., editors. <i>Proceedings of the 2nd International
    Workshop on Embedded Software for Industrial IoT - ESIIT</i>. 2019.
  short: O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings
    of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT,
    Florence, Italy, 2019.
date_created: 2024-04-18T22:09:26Z
date_updated: 2024-04-18T22:09:33Z
department:
- _id: '58'
editor:
- first_name: Oliver
  full_name: Bringmann, Oliver
  last_name: Bringmann
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Daniel
  full_name: Müller-Gridschneder, Daniel
  last_name: Müller-Gridschneder
language:
- iso: eng
place: Florence, Italy
status: public
title: Proceedings of the 2nd International Workshop on Embedded Software for Industrial
  IoT - ESIIT
type: book_editor
user_id: '16243'
year: '2019'
...
---
_id: '24194'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual
    Prototyping and Chip Design. <i>International Workshop on RISC-V Research Activities</i>.
    2018;Presentation.
  apa: Adelt, P., Koppelmann, B., &#38; Müller, W. (2018). Current and Future RISC-V
    Activities for Virtual Prototyping and Chip Design. <i>International Workshop
    on RISC-V Research Activities</i>, <i>Presentation</i>.
  bibtex: '@article{Adelt_Koppelmann_Müller_2018, title={Current and Future RISC-V
    Activities for Virtual Prototyping and Chip Design}, volume={Presentation}, journal={International
    Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian
    and Müller, Wolfgang}, year={2018} }'
  chicago: Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future
    RISC-V Activities for Virtual Prototyping and Chip Design.” <i>International Workshop
    on RISC-V Research Activities</i> Presentation (2018).
  ieee: P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities
    for Virtual Prototyping and Chip Design,” <i>International Workshop on RISC-V
    Research Activities</i>, vol. Presentation, 2018.
  mla: Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping
    and Chip Design.” <i>International Workshop on RISC-V Research Activities</i>,
    vol. Presentation, 2018.
  short: P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research
    Activities Presentation (2018).
conference:
  location: Munich, DE
date_created: 2021-09-13T07:38:01Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '58'
language:
- iso: eng
publication: International Workshop on RISC-V Research Activities
related_material:
  link:
  - relation: confirmation
    url: https://www.edacentrum.de/compact/current-and-future-risc-v-activities-virtual-prototyping-and-chip-design
status: public
title: Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
type: journal_article
user_id: '15931'
volume: Presentation
year: '2018'
...
---
_id: '24196'
abstract:
- lang: eng
  text: This paper presents an approach for analog fault effect simulation automation
    based on random fault selection with a high fault coverage of the circuit under
    test by means of fault injection and simulation based on advanced sampling techniques.
    The random fault selection utilizes the likelihood of the fault occurrence of
    different electrical components in the circuit with a confidence level. Defect
    models of different devices are analyzed for the calculation of the fault probability.
    A case study with our implemented tool demonstrates that likelihood calculation
    and fault simulation provides means for efficient fault effect simulation automation.
author:
- first_name: Liang
  full_name: Wu, Liang
  id: '30401'
  last_name: Wu
- first_name: Mohammad Khizer
  full_name: Hussain, Mohammad Khizer
  last_name: Hussain
- first_name: Saed
  full_name: Abughannam, Saed
  id: '37628'
  last_name: Abughannam
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
citation:
  ama: 'Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault
    simulation automation at schematic level with random sampling techniques. In:
    <i>2018 13th International Conference on Design &#38; Technology of Integrated
    Systems In Nanoscale Era (DTIS)) </i>. IEEE; 2018. doi:<a href="https://doi.org/10.1109/DTIS.2018.8368549">10.1109/DTIS.2018.8368549</a>'
  apa: Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker,
    W. (2018). Analog fault simulation automation at schematic level with random sampling
    techniques. <i>2018 13th International Conference on Design &#38; Technology of
    Integrated Systems In Nanoscale Era (DTIS)) </i>. <a href="https://doi.org/10.1109/DTIS.2018.8368549">https://doi.org/10.1109/DTIS.2018.8368549</a>
  bibtex: '@inproceedings{Wu_Hussain_Abughannam_Müller_Scheytt_Ecker_2018, place={Italy/Taormina},
    title={Analog fault simulation automation at schematic level with random sampling
    techniques}, DOI={<a href="https://doi.org/10.1109/DTIS.2018.8368549">10.1109/DTIS.2018.8368549</a>},
    booktitle={2018 13th International Conference on Design &#38; Technology of Integrated
    Systems In Nanoscale Era (DTIS)) }, publisher={IEEE}, author={Wu, Liang and Hussain,
    Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph
    and Ecker, Wolfgang}, year={2018} }'
  chicago: 'Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller,
    Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at
    Schematic Level with Random Sampling Techniques.” In <i>2018 13th International
    Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS))
    </i>. Italy/Taormina: IEEE, 2018. <a href="https://doi.org/10.1109/DTIS.2018.8368549">https://doi.org/10.1109/DTIS.2018.8368549</a>.'
  ieee: 'L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker,
    “Analog fault simulation automation at schematic level with random sampling techniques,”
    2018, doi: <a href="https://doi.org/10.1109/DTIS.2018.8368549">10.1109/DTIS.2018.8368549</a>.'
  mla: Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with
    Random Sampling Techniques.” <i>2018 13th International Conference on Design &#38;
    Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>, IEEE, 2018, doi:<a
    href="https://doi.org/10.1109/DTIS.2018.8368549">10.1109/DTIS.2018.8368549</a>.
  short: 'L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in:
    2018 13th International Conference on Design &#38; Technology of Integrated Systems
    In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.'
conference:
  end_date: 2018.04.12
  start_date: 2018.04.09
date_created: 2021-09-13T07:38:03Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '58'
doi: 10.1109/DTIS.2018.8368549
language:
- iso: eng
place: Italy/Taormina
publication: '2018 13th International Conference on Design & Technology of Integrated
  Systems In Nanoscale Era (DTIS)) '
publisher: IEEE
related_material:
  link:
  - relation: confirmation
    url: https://ieeexplore.ieee.org/document/8368549
status: public
title: Analog fault simulation automation at schematic level with random sampling
  techniques
type: conference
user_id: '15931'
year: '2018'
...
---
_id: '53595'
citation:
  ama: Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. <i>Proceedings
    of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.;
    2018.
  apa: Bringmann, O., Ecker, W., Müller, W., &#38; Müller-Gridschneder, D. (Eds.).
    (2018). <i>Proceedings of the 1st International Workshop on Embedded Software
    for Industrial IoT - ESIIT</i>.
  bibtex: '@book{Bringmann_Ecker_Müller_Müller-Gridschneder_2018, place={Dresden,
    Germany}, title={Proceedings of the 1st International Workshop on Embedded Software
    for Industrial IoT - ESIIT}, year={2018} }'
  chicago: Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder,
    eds. <i>Proceedings of the 1st International Workshop on Embedded Software for
    Industrial IoT - ESIIT</i>. Dresden, Germany, 2018.
  ieee: O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., <i>Proceedings
    of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT</i>.
    Dresden, Germany, 2018.
  mla: Bringmann, Oliver, et al., editors. <i>Proceedings of the 1st International
    Workshop on Embedded Software for Industrial IoT - ESIIT</i>. 2018.
  short: O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings
    of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT,
    Dresden, Germany, 2018.
date_created: 2024-04-18T22:03:47Z
date_updated: 2024-04-18T22:05:33Z
department:
- _id: '58'
editor:
- first_name: Oliver
  full_name: Bringmann, Oliver
  last_name: Bringmann
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Daniel
  full_name: Müller-Gridschneder, Daniel
  last_name: Müller-Gridschneder
language:
- iso: eng
place: Dresden, Germany
status: public
title: Proceedings of the 1st International Workshop on Embedded Software for Industrial
  IoT - ESIIT
type: book_editor
user_id: '16243'
year: '2018'
...
---
_id: '24220'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Daniel
  full_name: Mueller-Gritschneder, Daniel
  last_name: Mueller-Gritschneder
- first_name: Bernd
  full_name: Kleinjohann, Bernd
  last_name: Kleinjohann
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt
    C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen
    auf der Basis virtueller Plattformen. In: <i>Tagungsband des Wissenschaftsforums
    Intelligente Technische Systeme</i>. Verlagsschriftenreihe des Heinz Nixdorf Instituts;
    2017. doi:<a href="https://doi.org/10.17619/UNIPB/1-93">10.17619/UNIPB/1-93</a>'
  apa: Adelt, P., Koppelmann, B., Müller, W., Mueller-Gritschneder, D., Kleinjohann,
    B., &#38; Scheytt, C. (2017). Automatisierte Fehlerinjektion zur Entwicklung sicherer
    Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. <i>Tagungsband
    des Wissenschaftsforums Intelligente Technische Systeme</i>. <a href="https://doi.org/10.17619/UNIPB/1-93">https://doi.org/10.17619/UNIPB/1-93</a>
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Mueller-Gritschneder_Kleinjohann_Scheytt_2017,
    place={Germany, Paderborn}, title={Automatisierte Fehlerinjektion zur Entwicklung
    sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen}, DOI={<a
    href="https://doi.org/10.17619/UNIPB/1-93">10.17619/UNIPB/1-93</a>}, booktitle={Tagungsband
    des Wissenschaftsforums Intelligente Technische Systeme}, publisher={Verlagsschriftenreihe
    des Heinz Nixdorf Instituts}, author={Adelt, Peer and Koppelmann, Bastian and
    Müller, Wolfgang and Mueller-Gritschneder, Daniel and Kleinjohann, Bernd and Scheytt,
    Christoph}, year={2017} }'
  chicago: 'Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder,
    Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur
    Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.”
    In <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>.
    Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017. <a
    href="https://doi.org/10.17619/UNIPB/1-93">https://doi.org/10.17619/UNIPB/1-93</a>.'
  ieee: 'P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann,
    and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen
    auf der Basis virtueller Plattformen,” 2017, doi: <a href="https://doi.org/10.17619/UNIPB/1-93">10.17619/UNIPB/1-93</a>.'
  mla: Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer
    Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” <i>Tagungsband
    des Wissenschaftsforums Intelligente Technische Systeme</i>, Verlagsschriftenreihe
    des Heinz Nixdorf Instituts, 2017, doi:<a href="https://doi.org/10.17619/UNIPB/1-93">10.17619/UNIPB/1-93</a>.
  short: 'P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann,
    C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme,
    Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.'
date_created: 2021-09-13T08:20:35Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
doi: 10.17619/UNIPB/1-93
language:
- iso: ger
place: Germany, Paderborn
publication: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme
publication_identifier:
  isbn:
  - 978-3-942647-88-5
publication_status: published
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts
related_material:
  link:
  - relation: confirmation
    url: https://digital.ub.uni-paderborn.de/hs/content/titleinfo/2436759
status: public
title: Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen
  auf der Basis virtueller Plattformen
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '24223'
abstract:
- lang: eng
  text: "This paper presents the design flow of using \r\nsampling technique for fault
    injection on sche-\r\nmatic level. The parameters used in the docu-\r\nment to
    calculate the likelihood could be modi-\r\nfied by using more realistic data from
    the fab. \r\nWith the help of the fault simulator, the whole \r\ndesign flow of
    the fault effect simulation can be \r\nrealized automatically."
author:
- first_name: Liang
  full_name: Wu, Liang
  id: '30401'
  last_name: Wu
- first_name: Saed
  full_name: Abughannam, Saed
  id: '37628'
  last_name: Abughannam
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
citation:
  ama: 'Wu L, Abughannam S, Müller W, Scheytt C, Ecker W. SPICE-Level Fault Injection
    with Likelihood Weighted Random Sampling - A Case Study. In: <i>2nd Workshop on
    Resiliency in Embedded Electronic Systems (REES)</i>. ; 2017:68.'
  apa: Wu, L., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker, W. (2017). SPICE-Level
    Fault Injection with Likelihood Weighted Random Sampling - A Case Study. <i>2nd
    Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 68.
  bibtex: '@inproceedings{Wu_Abughannam_Müller_Scheytt_Ecker_2017, place={Lausanne,
    Switzerland}, title={SPICE-Level Fault Injection with Likelihood Weighted Random
    Sampling - A Case Study}, booktitle={2nd Workshop on Resiliency in Embedded Electronic
    Systems (REES)}, author={Wu, Liang and Abughannam, Saed and Müller, Wolfgang and
    Scheytt, Christoph and Ecker, Wolfgang}, year={2017}, pages={68} }'
  chicago: Wu, Liang, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang
    Ecker. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling -
    A Case Study.” In <i>2nd Workshop on Resiliency in Embedded Electronic Systems
    (REES)</i>, 68. Lausanne, Switzerland, 2017.
  ieee: L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault
    Injection with Likelihood Weighted Random Sampling - A Case Study,” in <i>2nd
    Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 2017, p. 68.
  mla: Wu, Liang, et al. “SPICE-Level Fault Injection with Likelihood Weighted Random
    Sampling - A Case Study.” <i>2nd Workshop on Resiliency in Embedded Electronic
    Systems (REES)</i>, 2017, p. 68.
  short: 'L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop
    on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017,
    p. 68.'
date_created: 2021-09-13T08:20:39Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
language:
- iso: eng
page: '68'
place: Lausanne, Switzerland
publication: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES)
related_material:
  link:
  - relation: confirmation
    url: https://past.date-conference.com/date17/conference/workshop-w05
status: public
title: SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case
  Study
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '24224'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Bernd
  full_name: Kleinjohann, Bernd
  last_name: Kleinjohann
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. ANALISA - A Tool
    for Static Instruction Set Analysis. In: <i>Design Automation and Testing in Europe
    (DATE), University Booth Interactive Presentation</i>. ; 2017.'
  apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, C. (2017).
    ANALISA - A Tool for Static Instruction Set Analysis. <i>Design Automation and
    Testing in Europe (DATE), University Booth Interactive Presentation</i>.
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, place={Lausanne,
    CH}, title={ANALISA - A Tool for Static Instruction Set Analysis}, booktitle={Design
    Automation and Testing in Europe (DATE), University Booth Interactive Presentation},
    author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann,
    Bernd and Scheytt, Christoph}, year={2017} }'
  chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
    Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In
    <i>Design Automation and Testing in Europe (DATE), University Booth Interactive
    Presentation</i>. Lausanne, CH, 2017.
  ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA
    - A Tool for Static Instruction Set Analysis,” 2017.
  mla: Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.”
    <i>Design Automation and Testing in Europe (DATE), University Booth Interactive
    Presentation</i>, 2017.
  short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design
    Automation and Testing in Europe (DATE), University Booth Interactive Presentation,
    Lausanne, CH, 2017.'
conference:
  end_date: 2017.03.31
  start_date: 2017.03.27
date_created: 2021-09-13T08:20:40Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
language:
- iso: eng
place: Lausanne, CH
publication: Design Automation and Testing in Europe (DATE), University Booth Interactive
  Presentation
related_material:
  link:
  - relation: confirmation
    url: https://www.date-conference.com/content/date-2017-call-papers
status: public
title: ANALISA - A Tool for Static Instruction Set Analysis
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '24225'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Bernd
  full_name: Kleinjohann, Bernd
  last_name: Kleinjohann
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. An Automatic Injection
    Framework for Safety Assessements of Embedded Software Binaries. In: <i>2nd Workshop
    on Resiliency in Embedded Electronic Systems (REES) </i>. ; 2017:44.'
  apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, C. (2017).
    An Automatic Injection Framework for Safety Assessements of Embedded Software
    Binaries. <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)
    </i>, 44.
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, place={Lausanne,
    Switzerland}, title={An Automatic Injection Framework for Safety Assessements
    of Embedded Software Binaries}, booktitle={2nd Workshop on Resiliency in Embedded
    Electronic Systems (REES) }, author={Adelt, Peer and Koppelmann, Bastian and Müller,
    Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}, year={2017}, pages={44}
    }'
  chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
    Christoph Scheytt. “An Automatic Injection Framework for Safety Assessements of
    Embedded Software Binaries.” In <i>2nd Workshop on Resiliency in Embedded Electronic
    Systems (REES) </i>, 44. Lausanne, Switzerland, 2017.
  ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic
    Injection Framework for Safety Assessements of Embedded Software Binaries,” in
    <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES) </i>, 2017,
    p. 44.
  mla: Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements
    of Embedded Software Binaries.” <i>2nd Workshop on Resiliency in Embedded Electronic
    Systems (REES) </i>, 2017, p. 44.
  short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd
    Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland,
    2017, p. 44.'
date_created: 2021-09-13T08:20:41Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
language:
- iso: eng
page: '44'
place: Lausanne, Switzerland
publication: '2nd Workshop on Resiliency in Embedded Electronic Systems (REES) '
related_material:
  link:
  - relation: confirmation
    url: https://www.edacentrum.de/rees/program
status: public
title: An Automatic Injection Framework for Safety Assessements of Embedded Software
  Binaries
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '25068'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Bernd
  full_name: Kleinjohann, Bernd
  last_name: Kleinjohann
- first_name: J. Christoph
  full_name: Scheytt, J. Christoph
  id: '37144'
  last_name: Scheytt
  orcid: '0000-0002-5950-6618 '
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt JC. ANALISA - A Tool
    for Static Instruction Set Analysis. In: University Booth Interactive Presentation,
    ed. <i>Design Automation and Testing in Europe (DATE)</i>. ; 2017.'
  apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, J. C.
    (2017). ANALISA - A Tool for Static Instruction Set Analysis. In University Booth
    Interactive Presentation (Ed.), <i>Design Automation and Testing in Europe (DATE)</i>.
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, title={ANALISA
    - A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and
    Testing in Europe (DATE)}, author={Adelt, Peer and Koppelmann, Bastian and Müller,
    Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}, editor={University
    Booth Interactive Presentation}, year={2017} }'
  chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
    J. Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.”
    In <i>Design Automation and Testing in Europe (DATE)</i>, edited by University
    Booth Interactive Presentation, 2017.
  ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA
    - A Tool for Static Instruction Set Analysis,” in <i>Design Automation and Testing
    in Europe (DATE)</i>, Lausanne, CH, Mrz. 2017, 2017.
  mla: Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.”
    <i>Design Automation and Testing in Europe (DATE)</i>, edited by University Booth
    Interactive Presentation, 2017.
  short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University
    Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe
    (DATE), 2017.'
conference:
  location: Lausanne, CH, Mrz. 2017
corporate_editor:
- University Booth Interactive Presentation
date_created: 2021-09-28T11:08:16Z
date_updated: 2025-02-26T14:45:09Z
department:
- _id: '70'
language:
- iso: eng
publication: Design Automation and Testing in Europe (DATE)
status: public
title: ANALISA - A Tool for Static Instruction Set Analysis
type: conference
user_id: '5603'
year: '2017'
...
---
_id: '25069'
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Bernd
  full_name: Kleinjohann, Bernd
  last_name: Kleinjohann
- first_name: J. Christoph
  full_name: Scheytt, J. Christoph
  id: '37144'
  last_name: Scheytt
  orcid: '0000-0002-5950-6618 '
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt JC. ANALISA - A Tool
    for Static Instruction Set Analysis. In: University Booth Interactive Presentation,
    ed. <i>Design Automation and Testing in Europe (DATE)</i>. ; 2017.'
  apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, J. C.
    (2017). ANALISA - A Tool for Static Instruction Set Analysis. In University Booth
    Interactive Presentation (Ed.), <i>Design Automation and Testing in Europe (DATE)</i>.
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, title={ANALISA
    - A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and
    Testing in Europe (DATE)}, author={Adelt, Peer and Koppelmann, Bastian and Müller,
    Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}, editor={University
    Booth Interactive Presentation}, year={2017} }'
  chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
    J. Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.”
    In <i>Design Automation and Testing in Europe (DATE)</i>, edited by University
    Booth Interactive Presentation, 2017.
  ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA
    - A Tool for Static Instruction Set Analysis,” in <i>Design Automation and Testing
    in Europe (DATE)</i>, Lausanne, CH, Mrz. 2017, 2017.
  mla: Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.”
    <i>Design Automation and Testing in Europe (DATE)</i>, edited by University Booth
    Interactive Presentation, 2017.
  short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University
    Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe
    (DATE), 2017.'
conference:
  location: Lausanne, CH, Mrz. 2017
corporate_editor:
- University Booth Interactive Presentation
date_created: 2021-09-28T11:12:00Z
date_updated: 2025-02-26T14:45:23Z
department:
- _id: '672'
language:
- iso: eng
publication: Design Automation and Testing in Europe (DATE)
status: public
title: ANALISA - A Tool for Static Instruction Set Analysis
type: conference
user_id: '5603'
year: '2017'
...
---
_id: '24264'
abstract:
- lang: eng
  text: Electronic systems, like they are embedded in road vehicles, have to be compliant
    to functional safety standards like ISO 26262 [1], which limit the impacts of
    malfunctions for safety critical systems. ISO 26262, for instance, defines different
    safety levels for road vehicles, which require different means and measures for
    a safety compliant system and its development process like risk analysis and fault
    effect simulation. For fault effect simulation it is important to investigate
    the impact of physical and hardware related effects to the correct function of
    a system. This article first studies code and model mutations for fault injection
    in the context of fault effect simulation through different system abstraction
    levels. It demonstrates how high level mutations correlate to bit flips of software
    binaries by examples from the TriCore™ instruction set and finally presents a
    virtual platform based implementation for automated injection of bit flip based
    mutations into software binaries. Experimental results demonstrate the efficiency
    of the implemented approach.
author:
- first_name: Peer
  full_name: Adelt, Peer
  id: '5603'
  last_name: Adelt
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Bernd
  full_name: Kleinjohann, Bernd
  last_name: Kleinjohann
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: 'Adelt P, Koppelmann B, Müller W, Becker M, Kleinjohann B, Scheytt C. Fast
    Dynamic Fault Injection for Virtual Microcontroller Platforms. In: <i>Proceedings
    of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. ; 2016. doi:<a
    href="https://doi.org/10.1109/VLSI-SoC.2016.7753545">10.1109/VLSI-SoC.2016.7753545</a>'
  apa: Adelt, P., Koppelmann, B., Müller, W., Becker, M., Kleinjohann, B., &#38; Scheytt,
    C. (2016). Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.
    <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>.
    <a href="https://doi.org/10.1109/VLSI-SoC.2016.7753545">https://doi.org/10.1109/VLSI-SoC.2016.7753545</a>
  bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Becker_Kleinjohann_Scheytt_2016,
    place={Tallin, Estonia}, title={Fast Dynamic Fault Injection for Virtual Microcontroller
    Platforms}, DOI={<a href="https://doi.org/10.1109/VLSI-SoC.2016.7753545">10.1109/VLSI-SoC.2016.7753545</a>},
    booktitle={Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)},
    author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Becker, Markus
    and Kleinjohann, Bernd and Scheytt, Christoph}, year={2016} }'
  chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd
    Kleinjohann, and Christoph Scheytt. “Fast Dynamic Fault Injection for Virtual
    Microcontroller Platforms.” In <i>Proceedings of the IEEE/IFIP International Conference
    on VLSI (VLSI-SOC)</i>. Tallin, Estonia, 2016. <a href="https://doi.org/10.1109/VLSI-SoC.2016.7753545">https://doi.org/10.1109/VLSI-SoC.2016.7753545</a>.
  ieee: 'P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt,
    “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi:
    <a href="https://doi.org/10.1109/VLSI-SoC.2016.7753545">10.1109/VLSI-SoC.2016.7753545</a>.'
  mla: Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller
    Platforms.” <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>,
    2016, doi:<a href="https://doi.org/10.1109/VLSI-SoC.2016.7753545">10.1109/VLSI-SoC.2016.7753545</a>.
  short: 'P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt,
    in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC),
    Tallin, Estonia, 2016.'
conference:
  end_date: 2016.09.28
  start_date: 2016.09.26
date_created: 2021-09-13T09:44:30Z
date_updated: 2022-02-17T13:57:45Z
department:
- _id: '58'
doi: 10.1109/VLSI-SoC.2016.7753545
language:
- iso: eng
place: Tallin, Estonia
publication: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)
publication_identifier:
  eissn:
  - 2324-8440
related_material:
  link:
  - relation: confirmation
    url: https://ieeexplore.ieee.org/document/7753545
status: public
title: Fast Dynamic Fault Injection for Virtual Microcontroller Platforms
type: conference
user_id: '15931'
year: '2016'
...
---
_id: '24263'
abstract:
- lang: eng
  text: The design of safety critical systems requires an efficient methodology for
    an effective fault effect simulation for analog and digital circuits where analog
    fault injection and fault effect simulation is currently a field of active research
    and commercial tools are not available yet. This article begins by discussing
    fault injection strategies for analog circuits applied on a case study with two
    topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs
    on the basis of the example of a Wireless Sensor Network (WSN) node, how far different
    mixed level implementations with Verilog-A and SPICE can affect the simulation
    time and points out which component consumes the major part of the simulation
    time.
author:
- first_name: Saed
  full_name: Abughannam, Saed
  id: '37628'
  last_name: Abughannam
- first_name: Liang
  full_name: Wu, Liang
  id: '30401'
  last_name: Wu
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
- first_name: Christiano
  full_name: Novello, Christiano
  last_name: Novello
citation:
  ama: 'Abughannam S, Wu L, Müller W, Scheytt C, Ecker W, Novello C. Fault Injection
    and Mixed-Level Simulation for Analog Circuits - A Case Study. In: <i>Analog 2016
    - VDE</i>. ; 2016.'
  apa: Abughannam, S., Wu, L., Müller, W., Scheytt, C., Ecker, W., &#38; Novello,
    C. (2016). Fault Injection and Mixed-Level Simulation for Analog Circuits - A
    Case Study. <i>Analog 2016 - VDE</i>.
  bibtex: '@inproceedings{Abughannam_Wu_Müller_Scheytt_Ecker_Novello_2016, title={Fault
    Injection and Mixed-Level Simulation for Analog Circuits - A Case Study}, booktitle={Analog
    2016 - VDE}, author={Abughannam, Saed and Wu, Liang and Müller, Wolfgang and Scheytt,
    Christoph and Ecker, Wolfgang and Novello, Christiano}, year={2016} }'
  chicago: Abughannam, Saed, Liang Wu, Wolfgang Müller, Christoph Scheytt, Wolfgang
    Ecker, and Christiano Novello. “Fault Injection and Mixed-Level Simulation for
    Analog Circuits - A Case Study.” In <i>Analog 2016 - VDE</i>, 2016.
  ieee: S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault
    Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
  mla: Abughannam, Saed, et al. “Fault Injection and Mixed-Level Simulation for Analog
    Circuits - A Case Study.” <i>Analog 2016 - VDE</i>, 2016.
  short: 'S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog
    2016 - VDE, 2016.'
conference:
  end_date: 2016.09.14
  start_date: 2016.09.12
date_created: 2021-09-13T09:44:29Z
date_updated: 2022-02-17T13:58:08Z
department:
- _id: '58'
language:
- iso: eng
publication: Analog 2016 - VDE
publication_identifier:
  isbn:
  - 978-3-8007-4265-3
related_material:
  link:
  - relation: confirmation
    url: https://ieeexplore.ieee.org/document/7584296/
status: public
title: Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
type: conference
user_id: '15931'
year: '2016'
...
---
_id: '24289'
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Liang
  full_name: Wu, Liang
  id: '30401'
  last_name: Wu
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Sven
  full_name: Schoenberg, Sven
  last_name: Schoenberg
citation:
  ama: 'Müller W, Wu L, Scheytt C, Becker M, Schoenberg S. On the Correlation of HW
    Faults and SW Errors. In: Mueller-Gritschneder D, Müller W, Mitra S, eds. <i>Proceedings
    of the 1st International Workshop on Resiliency in Embedded Electronic Systems
    (REES 2014)</i>. ; 2015.'
  apa: Müller, W., Wu, L., Scheytt, C., Becker, M., &#38; Schoenberg, S. (2015). On
    the Correlation of HW Faults and SW Errors. In D. Mueller-Gritschneder, W. Müller,
    &#38; S. Mitra (Eds.), <i>Proceedings of the 1st International Workshop on Resiliency
    in Embedded Electronic Systems (REES 2014)</i>.
  bibtex: '@inproceedings{Müller_Wu_Scheytt_Becker_Schoenberg_2015, place={Amsterdam,
    Netherland}, title={On the Correlation of HW Faults and SW Errors}, booktitle={Proceedings
    of the 1st International Workshop on Resiliency in Embedded Electronic Systems
    (REES 2014)}, author={Müller, Wolfgang and Wu, Liang and Scheytt, Christoph and
    Becker, Markus and Schoenberg, Sven}, editor={Mueller-Gritschneder, Daniel and
    Müller, Wolfgang and Mitra, Subhasish}, year={2015} }'
  chicago: Müller, Wolfgang, Liang Wu, Christoph Scheytt, Markus Becker, and Sven
    Schoenberg. “On the Correlation of HW Faults and SW Errors.” In <i>Proceedings
    of the 1st International Workshop on Resiliency in Embedded Electronic Systems
    (REES 2014)</i>, edited by Daniel Mueller-Gritschneder, Wolfgang Müller, and Subhasish
    Mitra. Amsterdam, Netherland, 2015.
  ieee: W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation
    of HW Faults and SW Errors,” in <i>Proceedings of the 1st International Workshop
    on Resiliency in Embedded Electronic Systems (REES 2014)</i>, 2015.
  mla: Müller, Wolfgang, et al. “On the Correlation of HW Faults and SW Errors.” <i>Proceedings
    of the 1st International Workshop on Resiliency in Embedded Electronic Systems
    (REES 2014)</i>, edited by Daniel Mueller-Gritschneder et al., 2015.
  short: 'W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder,
    W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency
    in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.'
date_created: 2021-09-14T07:06:31Z
date_updated: 2022-02-17T10:08:53Z
department:
- _id: '58'
editor:
- first_name: Daniel
  full_name: Mueller-Gritschneder, Daniel
  last_name: Mueller-Gritschneder
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  last_name: Müller
- first_name: Subhasish
  full_name: Mitra, Subhasish
  last_name: Mitra
language:
- iso: eng
place: Amsterdam, Netherland
publication: Proceedings of the 1st International Workshop on Resiliency in Embedded
  Electronic Systems (REES 2014)
status: public
title: On the Correlation of HW Faults and SW Errors
type: conference
user_id: '15931'
year: '2015'
...
---
_id: '53590'
citation:
  ama: Müller-Gridschneder D, Müller W, Mitra S, eds. <i>Proceedings of the 1st International
    Workshop on Resiliency in Embedded Electronic Systems</i>.; 2015.
  apa: Müller-Gridschneder, D., Müller, W., &#38; Mitra, S. (Eds.). (2015). <i>Proceedings
    of the 1st International Workshop on Resiliency in Embedded Electronic Systems</i>.
  bibtex: '@book{Müller-Gridschneder_Müller_Mitra_2015, place={Amsterdam, Netherlands},
    title={Proceedings of the 1st International Workshop on Resiliency in Embedded
    Electronic Systems}, year={2015} }'
  chicago: Müller-Gridschneder, Daniel, Wolfgang Müller, and Subhasish Mitra, eds.
    <i>Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic
    Systems</i>. Amsterdam, Netherlands, 2015.
  ieee: D. Müller-Gridschneder, W. Müller, and S. Mitra, Eds., <i>Proceedings of the
    1st International Workshop on Resiliency in Embedded Electronic Systems</i>. Amsterdam,
    Netherlands, 2015.
  mla: Müller-Gridschneder, Daniel, et al., editors. <i>Proceedings of the 1st International
    Workshop on Resiliency in Embedded Electronic Systems</i>. 2015.
  short: D. Müller-Gridschneder, W. Müller, S. Mitra, eds., Proceedings of the 1st
    International Workshop on Resiliency in Embedded Electronic Systems, Amsterdam,
    Netherlands, 2015.
date_created: 2024-04-18T21:37:18Z
date_updated: 2024-04-18T22:13:15Z
department:
- _id: '58'
editor:
- first_name: Daniel
  full_name: Müller-Gridschneder, Daniel
  last_name: Müller-Gridschneder
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Subhasish
  full_name: Mitra, Subhasish
  last_name: Mitra
language:
- iso: eng
place: Amsterdam, Netherlands
status: public
title: Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic
  Systems
type: book_editor
user_id: '16243'
year: '2015'
...
---
_id: '25145'
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Becker M, Kuznik C, Müller W. Virtual Platforms for Model-Based Design of
    Dependable Cyber-Physical System Software. In: <i>17th Euromicro Conference on
    Digital Systems Design (DSD)</i>. ; 2014.'
  apa: Becker, M., Kuznik, C., &#38; Müller, W. (2014). Virtual Platforms for Model-Based
    Design of Dependable Cyber-Physical System Software. <i>17th Euromicro Conference
    on Digital Systems Design (DSD)</i>.
  bibtex: '@inproceedings{Becker_Kuznik_Müller_2014, title={Virtual Platforms for
    Model-Based Design of Dependable Cyber-Physical System Software}, booktitle={17th
    Euromicro Conference on Digital Systems Design (DSD)}, author={Becker, Markus
    and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }'
  chicago: Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Virtual Platforms
    for Model-Based Design of Dependable Cyber-Physical System Software.” In <i>17th
    Euromicro Conference on Digital Systems Design (DSD)</i>, 2014.
  ieee: M. Becker, C. Kuznik, and W. Müller, “Virtual Platforms for Model-Based Design
    of Dependable Cyber-Physical System Software,” 2014.
  mla: Becker, Markus, et al. “Virtual Platforms for Model-Based Design of Dependable
    Cyber-Physical System Software.” <i>17th Euromicro Conference on Digital Systems
    Design (DSD)</i>, 2014.
  short: 'M. Becker, C. Kuznik, W. Müller, in: 17th Euromicro Conference on Digital
    Systems Design (DSD), 2014.'
date_created: 2021-09-30T07:15:48Z
date_updated: 2022-01-06T06:56:53Z
department:
- _id: '672'
language:
- iso: eng
publication: 17th Euromicro Conference on Digital Systems Design (DSD)
status: public
title: Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System
  Software
type: conference
user_id: '21240'
year: '2014'
...
---
_id: '25155'
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC
    Virtual Platform Framework for Cyber-Physical Systems. In: <i>ACM/IEEE 5th International
    Conference on Cyber-Physical Systems</i>. ; 2014.'
  apa: Becker, M., Kuznik, C., &#38; Müller, W. (2014). Fault Effect Modeling in a
    Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems. <i>ACM/IEEE
    5th International Conference on Cyber-Physical Systems</i>.
  bibtex: '@inproceedings{Becker_Kuznik_Müller_2014, title={Fault Effect Modeling
    in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems},
    booktitle={ACM/IEEE 5th International Conference on Cyber-Physical Systems}, author={Becker,
    Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014} }'
  chicago: Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling
    in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems.”
    In <i>ACM/IEEE 5th International Conference on Cyber-Physical Systems</i>, 2014.
  ieee: M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous
    SystemC Virtual Platform Framework for Cyber-Physical Systems,” 2014.
  mla: Becker, Markus, et al. “Fault Effect Modeling in a Heterogeneous SystemC Virtual
    Platform Framework for Cyber-Physical Systems.” <i>ACM/IEEE 5th International
    Conference on Cyber-Physical Systems</i>, 2014.
  short: 'M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference
    on Cyber-Physical Systems, 2014.'
date_created: 2021-09-30T08:17:50Z
date_updated: 2022-01-06T06:56:53Z
department:
- _id: '672'
language:
- iso: eng
publication: ACM/IEEE 5th International Conference on Cyber-Physical Systems
status: public
title: Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework
  for Cyber-Physical Systems
type: conference
user_id: '21240'
year: '2014'
...
---
_id: '25161'
author:
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Koppelmann B, Becker M, Müller W. Portierung der TriCore-Architektur auf QEMU.
    In: <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
    von Schaltungen Und Systemen (MBMV 2014) </i>. ; 2014.'
  apa: Koppelmann, B., Becker, M., &#38; Müller, W. (2014). Portierung der TriCore-Architektur
    auf QEMU. <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung
    Und Verifikation von Schaltungen Und Systemen (MBMV 2014) </i>.
  bibtex: '@inproceedings{Koppelmann_Becker_Müller_2014, title={Portierung der TriCore-Architektur
    auf QEMU}, booktitle={17. Workshop Methoden und Beschreibungssprachen zur Modellierung
    und Verifikation von Schaltungen und Systemen (MBMV 2014) }, author={Koppelmann,
    Bastian and Becker, Markus and Müller, Wolfgang}, year={2014} }'
  chicago: Koppelmann, Bastian, Markus Becker, and Wolfgang Müller. “Portierung Der
    TriCore-Architektur Auf QEMU.” In <i>17. Workshop Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) </i>,
    2014.
  ieee: B. Koppelmann, M. Becker, and W. Müller, “Portierung der TriCore-Architektur
    auf QEMU,” 2014.
  mla: Koppelmann, Bastian, et al. “Portierung Der TriCore-Architektur Auf QEMU.”
    <i>17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
    von Schaltungen Und Systemen (MBMV 2014) </i>, 2014.
  short: 'B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.'
date_created: 2021-09-30T09:51:08Z
date_updated: 2022-01-06T06:56:53Z
department:
- _id: '672'
language:
- iso: eng
publication: '17. Workshop Methoden und Beschreibungssprachen zur Modellierung und
  Verifikation von Schaltungen und Systemen (MBMV 2014) '
status: public
title: Portierung der TriCore-Architektur auf QEMU
type: conference
user_id: '21240'
year: '2014'
...
---
_id: '24305'
abstract:
- lang: eng
  text: Energy efficiency drives the development of more and more complex low-power
    designs. Based on dynamic power management techniques, multiple voltage islands
    as well as a huge amount of power states are specified that have to be tested
    carefully. In this context, low-power design should start at an early stage using
    state-of-the-art system-level modeling and simulation techniques. However, there
    is neither a programming language nor any modeling standard that reflects variable
    power together with its functional side effects in a well-suited abstract manner.
    To overcome this limitation, we present a modeling approach on top of SystemC
    TLM to capture low-power design characteristics at electronic system-level. We
    demonstrate the usability by means of an existing open-source low-power design.
    The experimental results show that appropriate TLM instrumentation cause only
    minimal simulation overhead, but offer sufficient details to identify common low-power
    design errors.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based
    System Modeling and Simulation. In: <i>Embedded Computer Systems: Architectures,
    Modeling, and Simulation (SAMOS XIV)</i>. IEEE; 2014. doi:<a href="https://doi.org/10.1109/SAMOS.2014.6893219">10.1109/SAMOS.2014.6893219</a>'
  apa: 'Mischkalla, F., &#38; Müller, W. (2014). Architectural Low-Power Design Using
    Transaction-Based System Modeling and Simulation. <i>Embedded Computer Systems:
    Architectures, Modeling, and Simulation (SAMOS XIV)</i>. <a href="https://doi.org/10.1109/SAMOS.2014.6893219">https://doi.org/10.1109/SAMOS.2014.6893219</a>'
  bibtex: '@inproceedings{Mischkalla_Müller_2014, place={Greece}, title={Architectural
    Low-Power Design Using Transaction-Based System Modeling and Simulation}, DOI={<a
    href="https://doi.org/10.1109/SAMOS.2014.6893219">10.1109/SAMOS.2014.6893219</a>},
    booktitle={Embedded Computer Systems: Architectures, Modeling, and Simulation
    (SAMOS XIV)}, publisher={IEEE}, author={Mischkalla, Fabian and Müller, Wolfgang},
    year={2014} }'
  chicago: 'Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design
    Using Transaction-Based System Modeling and Simulation.” In <i>Embedded Computer
    Systems: Architectures, Modeling, and Simulation (SAMOS XIV)</i>. Greece: IEEE,
    2014. <a href="https://doi.org/10.1109/SAMOS.2014.6893219">https://doi.org/10.1109/SAMOS.2014.6893219</a>.'
  ieee: 'F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based
    System Modeling and Simulation,” 2014, doi: <a href="https://doi.org/10.1109/SAMOS.2014.6893219">10.1109/SAMOS.2014.6893219</a>.'
  mla: 'Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using
    Transaction-Based System Modeling and Simulation.” <i>Embedded Computer Systems:
    Architectures, Modeling, and Simulation (SAMOS XIV)</i>, IEEE, 2014, doi:<a href="https://doi.org/10.1109/SAMOS.2014.6893219">10.1109/SAMOS.2014.6893219</a>.'
  short: 'F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures,
    Modeling, and Simulation (SAMOS XIV), IEEE, Greece, 2014.'
conference:
  end_date: 2014.07.17
  start_date: 2014.07.14
date_created: 2021-09-14T07:06:51Z
date_updated: 2022-02-17T12:46:32Z
department:
- _id: '58'
doi: 10.1109/SAMOS.2014.6893219
language:
- iso: eng
place: Greece
publication: 'Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS
  XIV)'
publication_identifier:
  eisbn:
  - 978-1-4799-3770-7
publisher: IEEE
related_material:
  link:
  - relation: confirmation
    url: https://ieeexplore.ieee.org/document/6893219
status: public
title: Architectural Low-Power Design Using Transaction-Based System Modeling and
  Simulation
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '24302'
abstract:
- lang: eng
  text: In this paper, we present an efficient approach to virtual platform modeling
    for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
    Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced
    AURIX processor family as a target platform, which utilizes multiple CPU cores
    operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
    For SoC prototyping, we integrate the fast and open instruction accurate QEMU
    software emulator with the TLMu library for SystemC co-verification. This article
    reports our most recent efforts of the implementation of the TriCore instruction
    set for QEMU. The experimental results demonstrate the functional correctness
    and performance of our TriCore implementation.
author:
- first_name: Bastian
  full_name: Koppelmann, Bastian
  id: '25260'
  last_name: Koppelmann
- first_name: Bernd
  full_name: Messidat, Bernd
  last_name: Messidat
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
citation:
  ama: Koppelmann B, Messidat B, Becker M, Kuznik C, Müller W, Scheytt C. Fast and
    Open Virtual Platforms for TriCore-based SoCs Using QEMU. <i>Design and Verification
    Conference (DVCON EUROPE)</i>. Published online 2014.
  apa: Koppelmann, B., Messidat, B., Becker, M., Kuznik, C., Müller, W., &#38; Scheytt,
    C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU.
    <i>Design and Verification Conference (DVCON EUROPE)</i>.
  bibtex: '@article{Koppelmann_Messidat_Becker_Kuznik_Müller_Scheytt_2014, title={Fast
    and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, journal={Design
    and Verification Conference (DVCON EUROPE)}, author={Koppelmann, Bastian and Messidat,
    Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt,
    Christoph}, year={2014} }'
  chicago: Koppelmann, Bastian, Bernd Messidat, Markus Becker, Christoph Kuznik, Wolfgang
    Müller, and Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based
    SoCs Using QEMU.” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.
  ieee: B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and C. Scheytt,
    “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” <i>Design
    and Verification Conference (DVCON EUROPE)</i>, 2014.
  mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
    SoCs Using QEMU.” <i>Design and Verification Conference (DVCON EUROPE)</i>, 2014.
  short: B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt,
    Design and Verification Conference (DVCON EUROPE) (2014).
conference:
  location: München, Germany
  start_date: 2014.10.14
date_created: 2021-09-14T07:06:47Z
date_updated: 2022-02-17T12:34:27Z
department:
- _id: '58'
language:
- iso: eng
publication: Design and Verification Conference (DVCON EUROPE)
related_material:
  link:
  - relation: confirmation
    url: http://dvcon-europe.org/conference/dvcon-europe-2014/
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: journal_article
user_id: '15931'
year: '2014'
...
---
_id: '24309'
abstract:
- lang: eng
  text: Verific-MM is an approach to systematize and accelerate the coverage plan
    engineering as well as the verification environment’s (functional) metric code
    generation -- usually a time-consuming and error-prone task -- in particular by
    (i) improving automation via assisted model-based approaches, utilizing recent
    industry standards such as UCIS and (ii) a supporting methodology suitable for
    various target (functional coverage) languages (IEEE-1800 SystemVerilog, IEEE-1647
    e, IEEE-1666 SystemC).
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Kuznik C, Müller W. Verific-MM: Systematized Verification Metrics Generation
    with UCIS for Improved Automation on Verification Closure. <i>Design, Automation
    and Test in Europe DATE, University Booth, Dresden</i>. Published online 2014.'
  apa: 'Kuznik, C., &#38; Müller, W. (2014). Verific-MM: Systematized Verification
    Metrics Generation with UCIS for Improved Automation on Verification Closure.
    <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>.'
  bibtex: '@article{Kuznik_Müller_2014, title={Verific-MM: Systematized Verification
    Metrics Generation with UCIS for Improved Automation on Verification Closure},
    journal={Design, Automation and Test in Europe DATE, University Booth, Dresden},
    author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }'
  chicago: 'Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification
    Metrics Generation with UCIS for Improved Automation on Verification Closure.”
    <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>,
    2014.'
  ieee: 'C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation
    with UCIS for Improved Automation on Verification Closure,” <i>Design, Automation
    and Test in Europe DATE, University Booth, Dresden</i>, 2014.'
  mla: 'Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification
    Metrics Generation with UCIS for Improved Automation on Verification Closure.”
    <i>Design, Automation and Test in Europe DATE, University Booth, Dresden</i>,
    2014.'
  short: C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University
    Booth, Dresden (2014).
conference:
  start_date: 2014.03.25
date_created: 2021-09-14T07:06:56Z
date_updated: 2022-02-17T13:14:13Z
department:
- _id: '58'
language:
- iso: eng
publication: Design, Automation and Test in Europe DATE, University Booth, Dresden
related_material:
  link:
  - relation: confirmation
    url: https://www.edacentrum.de/effektiv/content/verific-mm-systematized-verification-metrics-generation-ucis-improved-automation-verificatio
status: public
title: 'Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved
  Automation on Verification Closure'
type: journal_article
user_id: '15931'
year: '2014'
...