---
_id: '24311'
abstract:
- lang: eng
text: Intelligent automotive electronics significantly improved driving safety in
the last decades. With the increasing complexity of automotive systems, dependability
of the electronic components themselves and of their interaction must be assured
to avoid any risk to driving safety due to unexpected failures caused by internal
or external faults. Additionally, Virtual Prototypes (VPs) have been accepted
in many areas of system development processes in the automotive industry as platforms
for SW development, verification, and design space exploration. We believe that
VPs will significantly contribute to the analysis of safety conditions for automotive
electronics. This paper shows the advantages of such a methodology based on today's
industrial needs, presents the current state of the art in this field, and outlines
upcoming research challenges that need to be addressed to make this vision a reality.
author:
- first_name: Jan-Hendrik
full_name: Oetjens, Jan-Hendrik
last_name: Oetjens
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Nico
full_name: Bannow, Nico
last_name: Bannow
- first_name: Oliver
full_name: Brinkmann, Oliver
last_name: Brinkmann
- first_name: Andreas
full_name: Burger, Andreas
last_name: Burger
- first_name: Moomen
full_name: Chaari, Moomen
last_name: Chaari
- first_name: Samarjit
full_name: Chakraborty, Samarjit
last_name: Chakraborty
- first_name: R.
full_name: Drechsler, R.
last_name: Drechsler
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
- first_name: Kim
full_name: Grüttner, Kim
last_name: Grüttner
- first_name: Thomas
full_name: Kruse, Thomas
last_name: Kruse
- first_name: Hoang M
full_name: Le, Hoang M
last_name: Le
- first_name: M.
full_name: Mauderer, M.
last_name: Mauderer
- first_name: Daniel
full_name: Mueller-Gritschneider, Daniel
last_name: Mueller-Gritschneider
- first_name: Frank
full_name: Poppen, Frank
last_name: Poppen
- first_name: Hendrik
full_name: Post, Hendrik
last_name: Post
- first_name: SEbastian
full_name: Reiter, SEbastian
last_name: Reiter
- first_name: Wolfgang
full_name: Rosenstiel, Wolfgang
last_name: Rosenstiel
- first_name: 'S. '
full_name: 'Roth, S. '
last_name: Roth
- first_name: Ulf
full_name: Schlichtmann, Ulf
last_name: Schlichtmann
- first_name: Andreas
full_name: Von Schwerin, Andreas
last_name: Von Schwerin
- first_name: Bogdan Andrei
full_name: Tabacaru, Bogdan Andrei
last_name: Tabacaru
- first_name: Alexander
full_name: Viehl, Alexander
last_name: Viehl
citation:
ama: 'Oetjens J-H, Becker M, Kuznik C, et al. Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges. In: Design
Automation Conference (DAC). ; 2014. doi:10.1145/2593069.2602976'
apa: 'Oetjens, J.-H., Becker, M., Kuznik, C., Müller, W., Bannow, N., Brinkmann,
O., Burger, A., Chaari, M., Chakraborty, S., Drechsler, R., Ecker, W., Grüttner,
K., Kruse, T., Le, H. M., Mauderer, M., Mueller-Gritschneider, D., Poppen, F.,
Post, H., Reiter, Se., … Viehl, A. (2014). Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges. Design
Automation Conference (DAC). https://doi.org/10.1145/2593069.2602976'
bibtex: '@inproceedings{Oetjens_Becker_Kuznik_Müller_Bannow_Brinkmann_Burger_Chaari_Chakraborty_Drechsler_et
al._2014, title={Safety Evaluation of Automotive Electronics Using Virtual Prototypes:
State of the Art and Research Challenges}, DOI={10.1145/2593069.2602976},
booktitle={Design Automation Conference (DAC)}, author={Oetjens, Jan-Hendrik and
Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Bannow, Nico and
Brinkmann, Oliver and Burger, Andreas and Chaari, Moomen and Chakraborty, Samarjit
and Drechsler, R. and et al.}, year={2014} }'
chicago: 'Oetjens, Jan-Hendrik, Markus Becker, Christoph Kuznik, Wolfgang Müller,
Nico Bannow, Oliver Brinkmann, Andreas Burger, et al. “Safety Evaluation of Automotive
Electronics Using Virtual Prototypes: State of the Art and Research Challenges.”
In Design Automation Conference (DAC), 2014. https://doi.org/10.1145/2593069.2602976.'
ieee: 'J.-H. Oetjens et al., “Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges,” 2014, doi:
10.1145/2593069.2602976.'
mla: 'Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges.” Design
Automation Conference (DAC), 2014, doi:10.1145/2593069.2602976.'
short: 'J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, N. Bannow, O. Brinkmann,
A. Burger, M. Chaari, S. Chakraborty, R. Drechsler, W. Ecker, K. Grüttner, T.
Kruse, H.M. Le, M. Mauderer, D. Mueller-Gritschneider, F. Poppen, H. Post, Se.
Reiter, W. Rosenstiel, S. Roth, U. Schlichtmann, A. Von Schwerin, B.A. Tabacaru,
A. Viehl, in: Design Automation Conference (DAC), 2014.'
date_created: 2021-09-14T07:06:59Z
date_updated: 2022-02-17T13:47:16Z
department:
- _id: '58'
doi: 10.1145/2593069.2602976
language:
- iso: eng
publication: Design Automation Conference (DAC)
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6881440
status: public
title: 'Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State
of the Art and Research Challenges'
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '25164'
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Joachim
full_name: Stroop, Joachim
last_name: Stroop
- first_name: Ulrich
full_name: Kiffmeier, Ulrich
last_name: Kiffmeier
citation:
ama: Becker M, Müller W, Stroop J, Kiffmeier U. HeroeS - A Framework for Heterogeneous
Software-Intensive System Design with SystemC. Design, Automation and Test
in Europe DATE, University Booth, Dresden. Published online 2014.
apa: Becker, M., Müller, W., Stroop, J., & Kiffmeier, U. (2014). HeroeS - A
Framework for Heterogeneous Software-Intensive System Design with SystemC. Design,
Automation and Test in Europe DATE, University Booth, Dresden.
bibtex: '@article{Becker_Müller_Stroop_Kiffmeier_2014, title={HeroeS - A Framework
for Heterogeneous Software-Intensive System Design with SystemC}, journal={Design,
Automation and Test in Europe DATE, University Booth, Dresden}, author={Becker,
Markus and Müller, Wolfgang and Stroop, Joachim and Kiffmeier, Ulrich}, year={2014}
}'
chicago: Becker, Markus, Wolfgang Müller, Joachim Stroop, and Ulrich Kiffmeier.
“HeroeS - A Framework for Heterogeneous Software-Intensive System Design with
SystemC.” Design, Automation and Test in Europe DATE, University Booth, Dresden,
2014.
ieee: M. Becker, W. Müller, J. Stroop, and U. Kiffmeier, “HeroeS - A Framework for
Heterogeneous Software-Intensive System Design with SystemC,” Design, Automation
and Test in Europe DATE, University Booth, Dresden, 2014.
mla: Becker, Markus, et al. “HeroeS - A Framework for Heterogeneous Software-Intensive
System Design with SystemC.” Design, Automation and Test in Europe DATE, University
Booth, Dresden, 2014.
short: M. Becker, W. Müller, J. Stroop, U. Kiffmeier, Design, Automation and Test
in Europe DATE, University Booth, Dresden (2014).
date_created: 2021-09-30T10:17:43Z
date_updated: 2024-04-18T21:06:21Z
department:
- _id: '672'
language:
- iso: eng
publication: Design, Automation and Test in Europe DATE, University Booth, Dresden
status: public
title: HeroeS - A Framework for Heterogeneous Software-Intensive System Design with
SystemC
type: journal_article
user_id: '16243'
year: '2014'
...
---
_id: '25120'
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based
System Simulation. In: Embedded Computer Systems: Architectures, Modeling,
and Simulation (SAMOS XIV). IEEE; 2014.'
apa: 'Mischkalla, F., & Müller, W. (2014). Architectural Low-Power Design Using
Transaction-Based System Simulation. Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV).'
bibtex: '@inproceedings{Mischkalla_Müller_2014, title={Architectural Low-Power Design
Using Transaction-Based System Simulation}, booktitle={Embedded Computer Systems:
Architectures, Modeling, and Simulation (SAMOS XIV)}, publisher={IEEE}, author={Mischkalla,
Fabian and Müller, Wolfgang}, year={2014} }'
chicago: 'Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design
Using Transaction-Based System Simulation.” In Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV). IEEE, 2014.'
ieee: F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based
System Simulation,” Greece, Sep. 2014, IEEE, 2014.
mla: 'Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using
Transaction-Based System Simulation.” Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV), IEEE, 2014.'
short: 'F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures,
Modeling, and Simulation (SAMOS XIV), IEEE, 2014.'
conference:
location: Greece, Sep. 2014, IEEE
date_created: 2021-09-29T12:06:12Z
date_updated: 2023-01-16T11:29:24Z
department:
- _id: '58'
language:
- iso: eng
publication: 'Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS
XIV)'
publisher: IEEE
status: public
title: Architectural Low-Power Design Using Transaction-Based System Simulation
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25146'
author:
- first_name: M. tech. Mabel Mary
full_name: Joy, M. tech. Mabel Mary
last_name: Joy
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Franz-Josef
full_name: Rammig, Franz-Josef
last_name: Rammig
citation:
ama: 'Joy M tech. MM, Müller W, Rammig F-J. Source code annotated memory leak detection
for soft real time embedded systems with resource constraints. In: 12th IEEE
International Conference on Embedded Computing. ; 2014.'
apa: Joy, M. tech. M. M., Müller, W., & Rammig, F.-J. (2014). Source code annotated
memory leak detection for soft real time embedded systems with resource constraints.
12th IEEE International Conference on Embedded Computing.
bibtex: '@inproceedings{Joy_Müller_Rammig_2014, title={Source code annotated memory
leak detection for soft real time embedded systems with resource constraints},
booktitle={12th IEEE International conference on Embedded Computing}, author={Joy,
M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}, year={2014}
}'
chicago: Joy, M. tech. Mabel Mary, Wolfgang Müller, and Franz-Josef Rammig. “Source
Code Annotated Memory Leak Detection for Soft Real Time Embedded Systems with
Resource Constraints.” In 12th IEEE International Conference on Embedded Computing,
2014.
ieee: M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Source code annotated memory
leak detection for soft real time embedded systems with resource constraints,”
2014.
mla: Joy, M. tech. Mabel Mary, et al. “Source Code Annotated Memory Leak Detection
for Soft Real Time Embedded Systems with Resource Constraints.” 12th IEEE International
Conference on Embedded Computing, 2014.
short: 'M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International
Conference on Embedded Computing, 2014.'
date_created: 2021-09-30T07:18:43Z
date_updated: 2023-01-16T11:36:02Z
department:
- _id: '58'
language:
- iso: eng
publication: 12th IEEE International conference on Embedded Computing
status: public
title: Source code annotated memory leak detection for soft real time embedded systems
with resource constraints
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25144'
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, Müller W. Advanced SoC Virtual Prototyping for System-Level
Power Planning and Validation. In: PATMOS 2014. ; 2014.'
apa: Mischkalla, F., & Müller, W. (2014). Advanced SoC Virtual Prototyping for
System-Level Power Planning and Validation. PATMOS 2014.
bibtex: '@inproceedings{Mischkalla_Müller_2014, place={Palma de Mallorca, Spain},
title={Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation},
booktitle={PATMOS 2014}, author={Mischkalla, Fabian and Müller, Wolfgang}, year={2014}
}'
chicago: Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping
for System-Level Power Planning and Validation.” In PATMOS 2014. Palma
de Mallorca, Spain, 2014.
ieee: F. Mischkalla and W. Müller, “Advanced SoC Virtual Prototyping for System-Level
Power Planning and Validation,” 2014.
mla: Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping
for System-Level Power Planning and Validation.” PATMOS 2014, 2014.
short: 'F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.'
date_created: 2021-09-30T07:13:17Z
date_updated: 2023-01-16T11:28:39Z
department:
- _id: '58'
language:
- iso: eng
place: Palma de Mallorca, Spain
publication: PATMOS 2014
status: public
title: Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '36918'
abstract:
- lang: eng
text: This paper presents an advanced eight levels spanning SystemC based virtual
platform methodology and framework - referred to as HeroeS 3 - providing smooth
application to platform mapping and continuous co-refinement of a virtual prototype
with its physical environment model. For heterogeneity support, various SystemC
extensions are combined covering continuous/discrete models of computation and
different communication abstractions, such as analog mixed-signal models, abstract
RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability
assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to
avoid risking physical injury or damage. Also, simulation results are deterministic
and can be evaluated interactively or offline. We apply FEM to both the physical
environment model and the different abstractions of the virtual prototype. Currently,
we focus on sensor failures and application control flow errors.
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC
Based Virtual Platform Framework for Cyber Physical Systems. In: IEEE; 2014. doi:10.1109/ICCPS.2014.6843726'
apa: Becker, M., Kuznik, C., & Müller, W. (2014). Fault Effect Modeling in
a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems.
ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin. https://doi.org/10.1109/ICCPS.2014.6843726
bibtex: '@inproceedings{Becker_Kuznik_Müller_2014, place={Berlin}, title={Fault
Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for
Cyber Physical Systems}, DOI={10.1109/ICCPS.2014.6843726},
publisher={IEEE}, author={Becker, Markus and Kuznik, Christoph and Müller, Wolfgang},
year={2014} }'
chicago: 'Becker, Markus, Christoph Kuznik, and Wolfgang Müller. “Fault Effect Modeling
in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical
Systems.” Berlin: IEEE, 2014. https://doi.org/10.1109/ICCPS.2014.6843726.'
ieee: 'M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous
SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented
at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin,
2014, doi: 10.1109/ICCPS.2014.6843726.'
mla: Becker, Markus, et al. Fault Effect Modeling in a Heterogeneous SystemC
Based Virtual Platform Framework for Cyber Physical Systems. IEEE, 2014, doi:10.1109/ICCPS.2014.6843726.
short: 'M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.'
conference:
location: Berlin
name: ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)
date_created: 2023-01-16T11:57:08Z
date_updated: 2023-01-16T11:57:22Z
department:
- _id: '58'
doi: 10.1109/ICCPS.2014.6843726
keyword:
- Computational modeling
- Finite element analysis
- Prototypes
- Abstracts
- Software
- Fault tolerance
- Fault tolerant systems
language:
- iso: eng
place: Berlin
publisher: IEEE
status: public
title: Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework
for Cyber Physical Systems
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '36917'
abstract:
- lang: eng
text: The ever-increasing complexity of heterogeneous electronic systems demand
for intensified abstraction and automation efforts to improve design, verification
and validation productivity, especially in earlier phases of system engineering.
Within the verification activity various metrics can be applied to determine functional
correctness or the overall progress. Here, a supporting verification methodology
defining high-level verification planning down to the actual metric code development
is essential. Moreover, an advanced assistance for the designer, such as a tooling
infrastructure to automatize and accelerate the metric code implementation, is
needed to minimize the influence of errorprone manual coding. In this article
we present a single-source verification metric code-generation methodology for
improved coverage automation. We determine (i) a suitable metric model for model-based
capture of verification metrics as well as (ii) an assisted model-based processing
and generation flow of the verification environment and metric skeletons. We apply
our method to a SystemC case-study, in doing so, targeting metric code implementation
productivity and consistency enhancement.
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Gilles Bertrand
full_name: Defo, Gilles Bertrand
last_name: Defo
citation:
ama: 'Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric
Model Code Generation Methodology. In: ; 2014.'
apa: Kuznik, C., Müller, W., & Defo, G. B. (2014). An Assisted Single Source
Verification Metric Model Code Generation Methodology. Proceedings of the
Electronic System Level Synthesis Conference (ESLSyn).
bibtex: '@inproceedings{Kuznik_Müller_Defo_2014, place={San Francisco, USA}, title={An
Assisted Single Source Verification Metric Model Code Generation Methodology},
author={Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}, year={2014}
}'
chicago: Kuznik, Christoph, Wolfgang Müller, and Gilles Bertrand Defo. “An Assisted
Single Source Verification Metric Model Code Generation Methodology.” San Francisco,
USA, 2014.
ieee: C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification
Metric Model Code Generation Methodology,” presented at the Proceedings of the
Electronic System Level Synthesis Conference (ESLSyn), 2014.
mla: Kuznik, Christoph, et al. An Assisted Single Source Verification Metric
Model Code Generation Methodology. 2014.
short: 'C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.'
conference:
name: Proceedings of the Electronic System Level Synthesis Conference (ESLSyn)
date_created: 2023-01-16T11:43:50Z
date_updated: 2023-01-16T11:44:06Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: San Francisco, USA
status: public
title: An Assisted Single Source Verification Metric Model Code Generation Methodology
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25166'
abstract:
- lang: eng
text: Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen
und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung
die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf
einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante
Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen
geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren.
Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer
zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology
(SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur
zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Kuznik C, Müller W. Modellierung effizienter Stresstest-Umgebungen für virtuelle
Prototypen mit SVM. In: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen. ; 2014.'
apa: Kuznik, C., & Müller, W. (2014). Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM. 26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen.
bibtex: '@inproceedings{Kuznik_Müller_2014, title={Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM}, booktitle={26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen}, author={Kuznik, Christoph and
Müller, Wolfgang}, year={2014} }'
chicago: Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM.” In 26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen, 2014.
ieee: C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für
virtuelle Prototypen mit SVM,” 2014.
mla: Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen
für virtuelle Prototypen mit SVM.” 26. ITG / GI / GMM Workshop Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen, 2014.
short: 'C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen, 2014.'
date_created: 2021-09-30T10:26:58Z
date_updated: 2023-01-16T11:46:54Z
department:
- _id: '58'
language:
- iso: ger
publication: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen
status: public
title: Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit
SVM
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25163'
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Bertrand Gilles
full_name: Defo, Bertrand Gilles
last_name: Defo
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Kuznik C, Defo BG, Müller W. Semi-automatische Generierung von Überdeckungsmetriken
mittels methodischer Verikationsplan Verarbeitung. In: 17. Workshop Methoden
und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
Systemen (MBMV 2014) . ; 2014.'
apa: Kuznik, C., Defo, B. G., & Müller, W. (2014). Semi-automatische Generierung
von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. 17.
Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2014) .
bibtex: '@inproceedings{Kuznik_Defo_Müller_2014, title={Semi-automatische Generierung
von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}, booktitle={17.
Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2014) }, author={Kuznik, Christoph and Defo,
Bertrand Gilles and Müller, Wolfgang}, year={2014} }'
chicago: Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “Semi-automatische
Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.”
In 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2014) , 2014.
ieee: C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken
mittels methodischer Verikationsplan Verarbeitung,” 2014.
mla: Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken
mittels methodischer Verikationsplan Verarbeitung.” 17. Workshop Methoden und
Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
(MBMV 2014) , 2014.
short: 'C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.'
date_created: 2021-09-30T10:11:13Z
date_updated: 2023-01-16T11:45:51Z
department:
- _id: '58'
language:
- iso: ger
publication: '17. Workshop Methoden und Beschreibungssprachen zur Modellierung und
Verifikation von Schaltungen und Systemen (MBMV 2014) '
status: public
title: Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer
Verikationsplan Verarbeitung
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25151'
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Bertrand Gilles
full_name: Defo, Bertrand Gilles
last_name: Defo
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: Kuznik C, Defo BG, Müller W. An Assisted Single Source Verification Metric
Model Code Generation Methodology. Electronic System Level Synthesis Conference
(ESLSyn). Published online 2014.
apa: Kuznik, C., Defo, B. G., & Müller, W. (2014). An Assisted Single Source
Verification Metric Model Code Generation Methodology. Electronic System Level
Synthesis Conference (ESLSyn).
bibtex: '@article{Kuznik_Defo_Müller_2014, title={An Assisted Single Source Verification
Metric Model Code Generation Methodology}, journal={Electronic System Level Synthesis
Conference (ESLSyn)}, author={Kuznik, Christoph and Defo, Bertrand Gilles and
Müller, Wolfgang}, year={2014} }'
chicago: Kuznik, Christoph, Bertrand Gilles Defo, and Wolfgang Müller. “An Assisted
Single Source Verification Metric Model Code Generation Methodology.” Electronic
System Level Synthesis Conference (ESLSyn), 2014.
ieee: C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification
Metric Model Code Generation Methodology,” Electronic System Level Synthesis
Conference (ESLSyn), 2014.
mla: Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model
Code Generation Methodology.” Electronic System Level Synthesis Conference
(ESLSyn), 2014.
short: C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference
(ESLSyn) (2014).
date_created: 2021-09-30T08:05:38Z
date_updated: 2023-01-16T11:44:46Z
department:
- _id: '58'
language:
- iso: eng
publication: Electronic System Level Synthesis Conference (ESLSyn)
status: public
title: An Assisted Single Source Verification Metric Model Code Generation Methodology
type: journal_article
user_id: '5786'
year: '2014'
...
---
_id: '34585'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual
Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design
and Verification Conference Europe (DVCON Europe). ; 2014.'
apa: Koppelmann, B., Messidat, B., Becker, M., Müller, W., & Scheytt, J. C.
(2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings
of the Design and Verification Conference Europe (DVCON Europe).
bibtex: '@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann,
Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and
J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs
Using QEMU.” In Proceedings of the Design and Verification Conference Europe
(DVCON Europe). München, 2014.
ieee: B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast
and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe
(DVCON Europe), 2014.
short: 'B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings
of the Design and Verification Conference Europe (DVCON Europe), München, 2014.'
date_created: 2022-12-20T10:48:25Z
date_updated: 2023-02-01T08:12:02Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: München
publication: Proceedings of the Design and Verification Conference Europe (DVCON Europe)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '34583'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and
Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of
the Design and Verification Conference Europe (DVCON Europe). ; 2014.'
apa: Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., & Scheytt,
J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU.
Proceedings of the Design and Verification Conference Europe (DVCON Europe).
bibtex: '@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann,
Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker,
Markus and Scheytt, J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller,
Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for
TriCore-Based SoCs Using QEMU.” In Proceedings of the Design and Verification
Conference Europe (DVCON Europe). München, 2014.
ieee: B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt,
“Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe
(DVCON Europe), 2014.
short: 'B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt,
in: Proceedings of the Design and Verification Conference Europe (DVCON Europe),
München, 2014.'
date_created: 2022-12-20T10:45:38Z
date_updated: 2025-02-26T14:42:18Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: München
publication: Proceedings of the Design and Verification Conference Europe (DVCON Europe)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '16243'
year: '2014'
...
---
_id: '34580'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Bastian
full_name: Koppelmann, Bastian
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
citation:
ama: 'Becker M, Kuznik C, Müller W, Koppelmann B, Messidat B. Fast and Open Virtual
Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design
and Verification Conference Europe . ; 2014.'
apa: Becker, M., Kuznik, C., Müller, W., Koppelmann, B., & Messidat, B. (2014).
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings
of the Design and Verification Conference Europe . DVCON Europe.
bibtex: '@inproceedings{Becker_Kuznik_Müller_Koppelmann_Messidat_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe }, author={Becker, Markus and
Kuznik, Christoph and Müller, Wolfgang and Koppelmann, Bastian and Messidat, Bernd},
year={2014} }'
chicago: Becker, Markus, Christoph Kuznik, Wolfgang Müller, Bastian Koppelmann,
and Bernd Messidat. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using
QEMU.” In Proceedings of the Design and Verification Conference Europe .
München, 2014.
ieee: M. Becker, C. Kuznik, W. Müller, B. Koppelmann, and B. Messidat, “Fast and
Open Virtual Platforms for TriCore-based SoCs Using QEMU,” presented at the DVCON
Europe, 2014.
mla: Becker, Markus, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs
Using QEMU.” Proceedings of the Design and Verification Conference Europe ,
2014.
short: 'M. Becker, C. Kuznik, W. Müller, B. Koppelmann, B. Messidat, in: Proceedings
of the Design and Verification Conference Europe , München, 2014.'
conference:
name: DVCON Europe
date_created: 2022-12-20T10:37:51Z
date_updated: 2025-02-26T14:44:30Z
language:
- iso: eng
place: München
publication: 'Proceedings of the Design and Verification Conference Europe '
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25117'
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: Koppelmann B, Messidat B, Becker M, Kuznik C, Müller W, Scheytt JC. Fast and
Open Virtual Platforms for TriCore-based SoCs Using QEMU. Design and Verification
Conference (DVCON EUROPE). Published online 2014.
apa: Koppelmann, B., Messidat, B., Becker, M., Kuznik, C., Müller, W., & Scheytt,
J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU.
Design and Verification Conference (DVCON EUROPE).
bibtex: '@article{Koppelmann_Messidat_Becker_Kuznik_Müller_Scheytt_2014, title={Fast
and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, journal={Design
and Verification Conference (DVCON EUROPE)}, author={Koppelmann, Bastian and Messidat,
Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Markus Becker, Christoph Kuznik, Wolfgang
Müller, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Design and Verification Conference (DVCON EUROPE), 2014.
ieee: B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and J. C. Scheytt,
“Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” Design
and Verification Conference (DVCON EUROPE), 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Design and Verification Conference (DVCON EUROPE), 2014.
short: B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, J.C. Scheytt,
Design and Verification Conference (DVCON EUROPE) (2014).
date_created: 2021-09-29T10:47:35Z
date_updated: 2025-02-26T14:44:48Z
department:
- _id: '672'
language:
- iso: eng
publication: Design and Verification Conference (DVCON EUROPE)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: journal_article
user_id: '5786'
year: '2014'
...
---
_id: '25162'
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Kuznik C, Müller W. Verific-MM: Systematized Verification Metrics Generation
with UCIS for Improved Automation on Verification Closure. Design, Automation
and Test in Europe DATE, University Booth, Dresden . Published online 2014.'
apa: 'Kuznik, C., & Müller, W. (2014). Verific-MM: Systematized Verification
Metrics Generation with UCIS for Improved Automation on Verification Closure.
Design, Automation and Test in Europe DATE, University Booth, Dresden .'
bibtex: '@article{Kuznik_Müller_2014, title={Verific-MM: Systematized Verification
Metrics Generation with UCIS for Improved Automation on Verification Closure},
journal={Design, Automation and Test in Europe DATE, University Booth, Dresden
}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2014} }'
chicago: 'Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification
Metrics Generation with UCIS for Improved Automation on Verification Closure.”
Design, Automation and Test in Europe DATE, University Booth, Dresden ,
2014.'
ieee: 'C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation
with UCIS for Improved Automation on Verification Closure,” Design, Automation
and Test in Europe DATE, University Booth, Dresden , 2014.'
mla: 'Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification
Metrics Generation with UCIS for Improved Automation on Verification Closure.”
Design, Automation and Test in Europe DATE, University Booth, Dresden ,
2014.'
short: C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University
Booth, Dresden (2014).
date_created: 2021-09-30T10:05:28Z
date_updated: 2025-02-26T14:45:04Z
department:
- _id: '672'
language:
- iso: eng
publication: 'Design, Automation and Test in Europe DATE, University Booth, Dresden '
status: public
title: 'Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved
Automation on Verification Closure'
type: journal_article
user_id: '5786'
year: '2014'
...
---
_id: '25169'
author:
- first_name: Jan-Hendrik
full_name: Oetjens, Jan-Hendrik
last_name: Oetjens
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Oetjens J-H, Becker M, Kuznik C, Müller W. Safety Evaluation of Automotive
Electronics Using Virtual Prototypes: State of the Art and Research Challenges.
In: Design Automation Conference (DAC). ; 2014.'
apa: 'Oetjens, J.-H., Becker, M., Kuznik, C., & Müller, W. (2014). Safety Evaluation
of Automotive Electronics Using Virtual Prototypes: State of the Art and Research
Challenges. Design Automation Conference (DAC).'
bibtex: '@inproceedings{Oetjens_Becker_Kuznik_Müller_2014, title={Safety Evaluation
of Automotive Electronics Using Virtual Prototypes: State of the Art and Research
Challenges}, booktitle={Design Automation Conference (DAC)}, author={Oetjens,
Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}, year={2014}
}'
chicago: 'Oetjens, Jan-Hendrik, Markus Becker, Christoph Kuznik, and Wolfgang Müller.
“Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of
the Art and Research Challenges.” In Design Automation Conference (DAC),
2014.'
ieee: 'J.-H. Oetjens, M. Becker, C. Kuznik, and W. Müller, “Safety Evaluation of
Automotive Electronics Using Virtual Prototypes: State of the Art and Research
Challenges,” 2014.'
mla: 'Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics
Using Virtual Prototypes: State of the Art and Research Challenges.” Design
Automation Conference (DAC), 2014.'
short: 'J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference
(DAC), 2014.'
date_created: 2021-09-30T11:01:14Z
date_updated: 2025-02-26T14:45:29Z
department:
- _id: '672'
language:
- iso: eng
publication: Design Automation Conference (DAC)
status: public
title: 'Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State
of the Art and Research Challenges'
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '25270'
author:
- first_name: M. tech. Mabel Mary
full_name: Joy, M. tech. Mabel Mary
last_name: Joy
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Franz-Josef
full_name: Rammig, Franz-Josef
last_name: Rammig
citation:
ama: 'Joy M tech. MM, Müller W, Rammig F-J. Early Phase Memory Leak Detection in
Embedded Software Designs with Virtual Memory Management Model. In: Proceedings
of AVICPS 2013, Dez. 2013 IEEE Computer Society,. Linköping University Electronic
Press; 2013.'
apa: Joy, M. tech. M. M., Müller, W., & Rammig, F.-J. (2013). Early Phase Memory
Leak Detection in Embedded Software Designs with Virtual Memory Management Model.
Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,.
bibtex: '@inproceedings{Joy_Müller_Rammig_2013, title={Early Phase Memory Leak Detection
in Embedded Software Designs with Virtual Memory Management Model}, booktitle={Proceedings
of AVICPS 2013, Dez. 2013 IEEE Computer Society,}, publisher={Linköping University
Electronic Press}, author={Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig,
Franz-Josef}, year={2013} }'
chicago: Joy, M. tech. Mabel Mary, Wolfgang Müller, and Franz-Josef Rammig. “Early
Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management
Model.” In Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,.
Linköping University Electronic Press, 2013.
ieee: M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Early Phase Memory Leak
Detection in Embedded Software Designs with Virtual Memory Management Model,”
2013.
mla: Joy, M. tech. Mabel Mary, et al. “Early Phase Memory Leak Detection in Embedded
Software Designs with Virtual Memory Management Model.” Proceedings of AVICPS
2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press,
2013.
short: 'M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: Proceedings of AVICPS 2013,
Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.'
date_created: 2021-10-04T08:25:24Z
date_updated: 2022-01-06T06:56:58Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,
publisher: Linköping University Electronic Press
status: public
title: Early Phase Memory Leak Detection in Embedded Software Designs with Virtual
Memory Management Model
type: conference
user_id: '21240'
year: '2013'
...
---
_id: '25271'
author:
- first_name: Da
full_name: He, Da
last_name: He
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'He D, Müller W. AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON
MULTI-CORE PROCESSORS. In: Proceedings of International Conference on Applied
Computing (AC). ; 2013.'
apa: He, D., & Müller, W. (2013). AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL-
TIME SYSTEM ON MULTI-CORE PROCESSORS. Proceedings of International Conference
on Applied Computing (AC).
bibtex: '@inproceedings{He_Müller_2013, title={AN ENERGY-EFFICIENT HEURISTIC FOR
HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS}, booktitle={Proceedings of International
Conference on Applied Computing (AC)}, author={He, Da and Müller, Wolfgang}, year={2013}
}'
chicago: He, Da, and Wolfgang Müller. “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL-
TIME SYSTEM ON MULTI-CORE PROCESSORS.” In Proceedings of International Conference
on Applied Computing (AC), 2013.
ieee: D. He and W. Müller, “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM
ON MULTI-CORE PROCESSORS,” 2013.
mla: He, Da, and Wolfgang Müller. “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL-
TIME SYSTEM ON MULTI-CORE PROCESSORS.” Proceedings of International Conference
on Applied Computing (AC), 2013.
short: 'D. He, W. Müller, in: Proceedings of International Conference on Applied
Computing (AC), 2013.'
date_created: 2021-10-04T08:30:39Z
date_updated: 2022-01-06T06:56:58Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of International Conference on Applied Computing (AC)
status: public
title: AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS
type: conference
user_id: '21240'
year: '2013'
...
---
_id: '25284'
author:
- first_name: Fabian
full_name: Mischkalla, Fabian
last_name: Mischkalla
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Mischkalla F, Müller W. Efficient Power Intent Validation Using Loosely-Timed
Simulation Models. In: 23rd International Workshop on Power And Timing Modeling,
Optimization and Simulation, Sep. 2013. ; 2013.'
apa: Mischkalla, F., & Müller, W. (2013). Efficient Power Intent Validation
Using Loosely-Timed Simulation Models. 23rd International Workshop on Power
And Timing Modeling, Optimization and Simulation, Sep. 2013.
bibtex: '@inproceedings{Mischkalla_Müller_2013, title={ Efficient Power Intent Validation
Using Loosely-Timed Simulation Models}, booktitle={ 23rd International Workshop
on Power And Timing Modeling, Optimization and Simulation, Sep. 2013}, author={Mischkalla,
Fabian and Müller, Wolfgang}, year={2013} }'
chicago: Mischkalla, Fabian, and Wolfgang Müller. “ Efficient Power Intent Validation
Using Loosely-Timed Simulation Models.” In 23rd International Workshop on
Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
ieee: F. Mischkalla and W. Müller, “ Efficient Power Intent Validation Using Loosely-Timed
Simulation Models,” 2013.
mla: Mischkalla, Fabian, and Wolfgang Müller. “ Efficient Power Intent Validation
Using Loosely-Timed Simulation Models.” 23rd International Workshop on Power
And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
short: 'F. Mischkalla, W. Müller, in: 23rd International Workshop on Power And
Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.'
date_created: 2021-10-04T11:15:10Z
date_updated: 2022-01-06T06:56:59Z
department:
- _id: '672'
language:
- iso: eng
publication: ' 23rd International Workshop on Power And Timing Modeling, Optimization
and Simulation, Sep. 2013'
status: public
title: ' Efficient Power Intent Validation Using Loosely-Timed Simulation Models'
type: conference
user_id: '21240'
year: '2013'
...
---
_id: '25291'
author:
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Ulrich
full_name: Kiffmeier, Ulrich
last_name: Kiffmeier
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Becker M, Kiffmeier U, Müller W. HeroeS: Virtual Platform Driven Integration
of Heterogeneous Software Components for Multi-Core Real-Time Architectures. In:
16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time
Distributed Computing. ; 2013.'
apa: 'Becker, M., Kiffmeier, U., & Müller, W. (2013). HeroeS: Virtual Platform
Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time
Architectures. 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented
Real-Time Distributed Computing.'
bibtex: '@inproceedings{Becker_Kiffmeier_Müller_2013, title={HeroeS: Virtual Platform
Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time
Architectures}, booktitle={16th IEEE Computer Society Symposium on Object/Component/Service-oriented
Real-time Distributed Computing}, author={Becker, Markus and Kiffmeier, Ulrich
and Müller, Wolfgang}, year={2013} }'
chicago: 'Becker, Markus, Ulrich Kiffmeier, and Wolfgang Müller. “HeroeS: Virtual
Platform Driven Integration of Heterogeneous Software Components for Multi-Core
Real-Time Architectures.” In 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented
Real-Time Distributed Computing, 2013.'
ieee: 'M. Becker, U. Kiffmeier, and W. Müller, “HeroeS: Virtual Platform Driven
Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures,”
2013.'
mla: 'Becker, Markus, et al. “HeroeS: Virtual Platform Driven Integration of Heterogeneous
Software Components for Multi-Core Real-Time Architectures.” 16th IEEE Computer
Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing,
2013.'
short: 'M. Becker, U. Kiffmeier, W. Müller, in: 16th IEEE Computer Society Symposium
on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.'
date_created: 2021-10-04T12:20:10Z
date_updated: 2022-01-06T06:56:59Z
department:
- _id: '672'
language:
- iso: eng
publication: 16th IEEE Computer Society Symposium on Object/Component/Service-oriented
Real-time Distributed Computing
status: public
title: 'HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components
for Multi-Core Real-Time Architectures'
type: conference
user_id: '21240'
year: '2013'
...