---
_id: '26080'
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: M. tech. Mabel
  full_name: Joy, M. tech. Mabel
  last_name: Joy
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Becker M, Kuznik C, Joy M tech. M, Xie T, Müller W. XEMU: A QEMU Based Binary
    Mutation Testing Framework. In: <i>Design, Automation and Test in Europe DATE</i>.
    ; 2012.'
  apa: 'Becker, M., Kuznik, C., Joy, M. tech. M., Xie, T., &#38; Müller, W. (2012).
    XEMU: A QEMU Based Binary Mutation Testing Framework. <i>Design, Automation and
    Test in Europe DATE</i>.'
  bibtex: '@inproceedings{Becker_Kuznik_Joy_Xie_Müller_2012, place={University Booth,
    Dresden}, title={XEMU: A QEMU Based Binary Mutation Testing Framework}, booktitle={Design,
    Automation and Test in Europe DATE}, author={Becker, Markus and Kuznik, Christoph
    and Joy, M. tech. Mabel and Xie, Tao and Müller, Wolfgang}, year={2012} }'
  chicago: 'Becker, Markus, Christoph Kuznik, M. tech. Mabel Joy, Tao Xie, and Wolfgang
    Müller. “XEMU: A QEMU Based Binary Mutation Testing Framework.” In <i>Design,
    Automation and Test in Europe DATE</i>. University Booth, Dresden, 2012.'
  ieee: 'M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, and W. Müller, “XEMU: A QEMU
    Based Binary Mutation Testing Framework,” 2012.'
  mla: 'Becker, Markus, et al. “XEMU: A QEMU Based Binary Mutation Testing Framework.”
    <i>Design, Automation and Test in Europe DATE</i>, 2012.'
  short: 'M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, W. Müller, in: Design, Automation
    and Test in Europe DATE, University Booth, Dresden, 2012.'
date_created: 2021-10-12T10:57:15Z
date_updated: 2022-01-06T06:57:16Z
department:
- _id: '672'
language:
- iso: eng
place: University Booth, Dresden
publication: Design, Automation and Test in Europe DATE
status: public
title: 'XEMU: A QEMU Based Binary Mutation Testing Framework'
type: conference
user_id: '21240'
year: '2012'
...
---
_id: '26092'
author:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Ahmed
  full_name: Elfeky, Ahmed
  last_name: Elfeky
- first_name: Anthony
  full_name: DiPasquale, Anthony
  last_name: DiPasquale
citation:
  ama: 'Müller W, Becker M, Zabel H, Elfeky A, DiPasquale A. Virtual Prototyping of
    Cyber-Physical Systems. In: <i>In Proceedings of 17th Asia and South Pacific Design
    Automation Conference (ASP-DAC 2012</i>. ; 2012.'
  apa: Müller, W., Becker, M., Zabel, H., Elfeky, A., &#38; DiPasquale, A. (2012).
    Virtual Prototyping of Cyber-Physical Systems. <i>In Proceedings of 17th Asia
    and South Pacific Design Automation Conference (ASP-DAC 2012</i>.
  bibtex: '@inproceedings{Müller_Becker_Zabel_Elfeky_DiPasquale_2012, place={Sydney},
    title={Virtual Prototyping of Cyber-Physical Systems}, booktitle={In Proceedings
    of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012}, author={Müller,
    Wolfgang and Becker, Markus and Zabel, Henning and Elfeky, Ahmed and DiPasquale,
    Anthony}, year={2012} }'
  chicago: Müller, Wolfgang, Markus Becker, Henning Zabel, Ahmed Elfeky, and Anthony
    DiPasquale. “Virtual Prototyping of Cyber-Physical Systems.” In <i>In Proceedings
    of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012</i>.
    Sydney, 2012.
  ieee: W. Müller, M. Becker, H. Zabel, A. Elfeky, and A. DiPasquale, “Virtual Prototyping
    of Cyber-Physical Systems,” 2012.
  mla: Müller, Wolfgang, et al. “Virtual Prototyping of Cyber-Physical Systems.” <i>In
    Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC
    2012</i>, 2012.
  short: 'W. Müller, M. Becker, H. Zabel, A. Elfeky, A. DiPasquale, in: In Proceedings
    of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, Sydney,
    2012.'
date_created: 2021-10-13T10:36:35Z
date_updated: 2022-01-06T06:57:16Z
department:
- _id: '672'
language:
- iso: eng
place: Sydney
publication: In Proceedings of 17th Asia and South Pacific Design Automation Conference
  (ASP-DAC 2012
status: public
title: Virtual Prototyping of Cyber-Physical Systems
type: conference
user_id: '21240'
year: '2012'
...
---
_id: '26695'
abstract:
- lang: eng
  text: The Unified Modeling Language (UML) is now widely accepted by the software
    community. More recently, UML has attracted attention as a unification language
    for systems description combining both hardware and software components. First,
    it has been recognized that electronic systems design can no longer be seen as
    an isolated hardware design activity. In addition, recent advances in tools supporting
    high level hardware synthesis from electronic system level languages, which are
    predominantly based on C/C++, open new perspectives for automatic code generation
    from UML models and opportunities to enhance the link between a high level specification
    and a concrete hardware/software implementation. Finally, UML has become a general
    purpose language which can be customized for specific purposes, such as the modelization
    of electronic systems. This chapter presents recent advances of the UML language
    applied to System-on-Chip (SoC) and hardware-related embedded systems design.
    In particular, several examples of specific UML customizations (UML profiles)
    relevant for SoC design are summarized. Various approaches associating UML with
    existing hardware/software design languages are presented. The question of tool
    support and association with well-known simulation environments, such as MATLAB/Simulink,
    is addressed as well. A concrete example of a UML profile for hardware/software
    co-modeling and code generation for hardware/software co-simulation is presented
    in more details for illustration purposes.
author:
- first_name: Yves
  full_name: Vanderperren, Yves
  last_name: Vanderperren
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Wim
  full_name: Dahaene, Wim
  last_name: Dahaene
citation:
  ama: 'Vanderperren Y, Müller W, He D, Mischkalla F, Dahaene W. Extending UML for
    Electronic Systems Design: A Code Generation Perspective. In: Nicolescu G, O’Connor
    I, Piguet C, eds. <i>Design Technology for Heterogeneous Embedded Systems</i>.
    1st Edition. Auflage. Springer Verlag; 2012:13-39.'
  apa: 'Vanderperren, Y., Müller, W., He, D., Mischkalla, F., &#38; Dahaene, W. (2012).
    Extending UML for Electronic Systems Design: A Code Generation Perspective. In
    G. Nicolescu, I. O’Connor, &#38; C. Piguet (Eds.), <i>Design Technology for Heterogeneous
    Embedded Systems</i> (1st Edition. Auflage, pp. 13–39). Springer Verlag.'
  bibtex: '@inbook{Vanderperren_Müller_He_Mischkalla_Dahaene_2012, edition={1st Edition.
    Auflage}, title={Extending UML for Electronic Systems Design: A Code Generation
    Perspective}, booktitle={Design Technology for Heterogeneous Embedded Systems},
    publisher={Springer Verlag}, author={Vanderperren, Yves and Müller, Wolfgang and
    He, Da and Mischkalla, Fabian and Dahaene, Wim}, editor={Nicolescu, Gabriela and
    O’Connor, Ian and Piguet, Christian}, year={2012}, pages={13–39} }'
  chicago: 'Vanderperren, Yves, Wolfgang Müller, Da He, Fabian Mischkalla, and Wim
    Dahaene. “Extending UML for Electronic Systems Design: A Code Generation Perspective.”
    In <i>Design Technology for Heterogeneous Embedded Systems</i>, edited by Gabriela
    Nicolescu, Ian O’Connor, and Christian Piguet, 1st Edition. Auflage., 13–39. Springer
    Verlag, 2012.'
  ieee: 'Y. Vanderperren, W. Müller, D. He, F. Mischkalla, and W. Dahaene, “Extending
    UML for Electronic Systems Design: A Code Generation Perspective,” in <i>Design
    Technology for Heterogeneous Embedded Systems</i>, 1st Edition. Auflage., G. Nicolescu,
    I. O’Connor, and C. Piguet, Eds. Springer Verlag, 2012, pp. 13–39.'
  mla: 'Vanderperren, Yves, et al. “Extending UML for Electronic Systems Design: A
    Code Generation Perspective.” <i>Design Technology for Heterogeneous Embedded
    Systems</i>, edited by Gabriela Nicolescu et al., 1st Edition. Auflage, Springer
    Verlag, 2012, pp. 13–39.'
  short: 'Y. Vanderperren, W. Müller, D. He, F. Mischkalla, W. Dahaene, in: G. Nicolescu,
    I. O’Connor, C. Piguet (Eds.), Design Technology for Heterogeneous Embedded Systems,
    1st Edition. Auflage, Springer Verlag, 2012, pp. 13–39.'
date_created: 2021-10-21T12:14:17Z
date_updated: 2022-10-18T09:53:40Z
department:
- _id: '672'
edition: 1st Edition. Auflage
editor:
- first_name: Gabriela
  full_name: Nicolescu, Gabriela
  last_name: Nicolescu
- first_name: Ian
  full_name: O'Connor, Ian
  last_name: O'Connor
- first_name: Christian
  full_name: Piguet, Christian
  last_name: Piguet
language:
- iso: eng
page: 13-39
publication: Design Technology for Heterogeneous Embedded Systems
publication_identifier:
  isbn:
  - 978-94-007-1125-9
publisher: Springer Verlag
status: public
title: 'Extending UML for Electronic Systems Design: A Code Generation Perspective'
type: book_chapter
user_id: '5786'
year: '2012'
...
---
_id: '26038'
abstract:
- lang: eng
  text: We present an enhanced UVM for SystemC library which incorporates verification
    best practices from OVM-ML and UVM as well as project partner implementations.
    Moreover, we extended functionality and implemented missing features, such as
    domain specific components, stimuli sequence generation and management, call-back
    facilities, response to request routing, transaction recording and many more.
    Apart from that, we added crucial verification components, such as functional
    coverage.
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Marcio F.
  full_name: Oliveira, Marcio F.
  last_name: Oliveira
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: Kuznik C, Oliveira MF, Müller W. SYSTEMC UVM VERIFICATION COMPONENTS. <i>Design,
    Automation and Test in Europe DATE</i>. Published online 2012.
  apa: Kuznik, C., Oliveira, M. F., &#38; Müller, W. (2012). SYSTEMC UVM VERIFICATION
    COMPONENTS. <i>Design, Automation and Test in Europe DATE</i>.
  bibtex: '@article{Kuznik_Oliveira_Müller_2012, title={SYSTEMC UVM VERIFICATION COMPONENTS},
    journal={Design, Automation and Test in Europe DATE}, author={Kuznik, Christoph
    and Oliveira, Marcio F. and Müller, Wolfgang}, year={2012} }'
  chicago: Kuznik, Christoph, Marcio F. Oliveira, and Wolfgang Müller. “SYSTEMC UVM
    VERIFICATION COMPONENTS.” <i>Design, Automation and Test in Europe DATE</i>, 2012.
  ieee: C. Kuznik, M. F. Oliveira, and W. Müller, “SYSTEMC UVM VERIFICATION COMPONENTS,”
    <i>Design, Automation and Test in Europe DATE</i>, 2012.
  mla: Kuznik, Christoph, et al. “SYSTEMC UVM VERIFICATION COMPONENTS.” <i>Design,
    Automation and Test in Europe DATE</i>, 2012.
  short: C. Kuznik, M.F. Oliveira, W. Müller, Design, Automation and Test in Europe
    DATE (2012).
conference:
  location: ' University Booth, Dresden , Mrz. 2012'
date_created: 2021-10-11T12:48:21Z
date_updated: 2024-04-18T21:07:25Z
department:
- _id: '672'
language:
- iso: eng
publication: Design, Automation and Test in Europe DATE
status: public
title: SYSTEMC UVM VERIFICATION COMPONENTS
type: journal_article
user_id: '5786'
year: '2012'
...
---
_id: '53593'
citation:
  ama: Müller W, Ecker W, eds. <i>Proceedings of the 1st Workshop on Metamodelling
    and Code Generation for Embedded Systems - MeCoEs </i>.; 2012.
  apa: Müller, W., &#38; Ecker, W. (Eds.). (2012). <i>Proceedings of the 1st Workshop
    on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>.
  bibtex: '@book{Müller_Ecker_2012, place={Tampere, Finland}, title={Proceedings of
    the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs
    }, year={2012} }'
  chicago: Müller, Wolfgang, and Wolfgang Ecker, eds. <i>Proceedings of the 1st Workshop
    on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. Tampere,
    Finland, 2012.
  ieee: W. Müller and W. Ecker, Eds., <i>Proceedings of the 1st Workshop on Metamodelling
    and Code Generation for Embedded Systems - MeCoEs </i>. Tampere, Finland, 2012.
  mla: Müller, Wolfgang, and Wolfgang Ecker, editors. <i>Proceedings of the 1st Workshop
    on Metamodelling and Code Generation for Embedded Systems - MeCoEs </i>. 2012.
  short: W. Müller, W. Ecker, eds., Proceedings of the 1st Workshop on Metamodelling
    and Code Generation for Embedded Systems - MeCoEs , Tampere, Finland, 2012.
date_created: 2024-04-18T21:48:40Z
date_updated: 2024-04-18T22:10:42Z
department:
- _id: '58'
editor:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Wolfgang
  full_name: Ecker, Wolfgang
  last_name: Ecker
language:
- iso: eng
place: Tampere, Finland
status: public
title: 'Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded
  Systems - MeCoEs '
type: book_editor
user_id: '16243'
year: '2012'
...
---
_id: '36922'
abstract:
- lang: eng
  text: In this paper we present an approach for the self reconfiguration of distributed
    micro-controllers for increased fault tolerance. Based on a modified distributed
    system topology utilizing a time division multiple access (TDMA) protocol, i.e.,
    Flex Ray, we present a self-organized distributed coordinator concept which performs
    the self-reconfiguration in the case of node failures. We introduce a distributed
    coordinator, which utilizes redundant slots in the Flex Ray communication schedule
    and combines messages in configured protocol frames and slots to avoid a complete
    bus restart. As such, the self-reconfiguration is realized by means of predetermined
    information about resulting changes in the communication dependencies and (re-)assignments
    determined in the design phase. To retrieve the necessary information, we present
    an analytical approach, which determines a combined solution for the initial configuration
    and all possible reconfigurations for the remaining nodes of the Flex Ray network
    in case of node failures. Hence, through this method we can design self-reconfiguring
    network-based systems enabling the handling of node failures for an increased
    fault tolerance.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Achim
  full_name: Rettberg, Achim
  last_name: Rettberg
citation:
  ama: 'Klobedanz K, Müller W, Rettberg A. An Approach for Self-Reconfiguring and
    Fault-Tolerant Distributed Real-Time Systems. In: IEEE; 2012. doi:<a href="https://doi.org/10.1109/ISORCW.2012.41">10.1109/ISORCW.2012.41</a>'
  apa: Klobedanz, K., Müller, W., &#38; Rettberg, A. (2012). <i>An Approach for Self-Reconfiguring
    and Fault-Tolerant Distributed Real-Time Systems</i>. IEEE 15th International
    Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
    Workshops. <a href="https://doi.org/10.1109/ISORCW.2012.41">https://doi.org/10.1109/ISORCW.2012.41</a>
  bibtex: '@inproceedings{Klobedanz_Müller_Rettberg_2012, place={Shenzhen, China },
    title={An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time
    Systems}, DOI={<a href="https://doi.org/10.1109/ISORCW.2012.41">10.1109/ISORCW.2012.41</a>},
    publisher={IEEE}, author={Klobedanz, Kay and Müller, Wolfgang and Rettberg, Achim},
    year={2012} }'
  chicago: 'Klobedanz, Kay, Wolfgang Müller, and Achim Rettberg. “An Approach for
    Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems.” Shenzhen,
    China : IEEE, 2012. <a href="https://doi.org/10.1109/ISORCW.2012.41">https://doi.org/10.1109/ISORCW.2012.41</a>.'
  ieee: 'K. Klobedanz, W. Müller, and A. Rettberg, “An Approach for Self-Reconfiguring
    and Fault-Tolerant Distributed Real-Time Systems,” presented at the IEEE 15th
    International Symposium on Object/Component/Service-Oriented Real-Time Distributed
    Computing Workshops, 2012, doi: <a href="https://doi.org/10.1109/ISORCW.2012.41">10.1109/ISORCW.2012.41</a>.'
  mla: Klobedanz, Kay, et al. <i>An Approach for Self-Reconfiguring and Fault-Tolerant
    Distributed Real-Time Systems</i>. IEEE, 2012, doi:<a href="https://doi.org/10.1109/ISORCW.2012.41">10.1109/ISORCW.2012.41</a>.
  short: 'K. Klobedanz, W. Müller, A. Rettberg, in: IEEE, Shenzhen, China , 2012.'
conference:
  name: IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time
    Distributed Computing Workshops
date_created: 2023-01-16T12:23:50Z
date_updated: 2023-01-16T12:25:33Z
department:
- _id: '672'
doi: 10.1109/ISORCW.2012.41
keyword:
- Real time systems
- Fault tolerant systems
- Schedules
- Protocols
- Redundancy
- Delay
language:
- iso: eng
place: 'Shenzhen, China '
publication_identifier:
  eisbn:
  - 978-0-7695-4669-8
publisher: IEEE
status: public
title: An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time
  Systems
type: conference
user_id: '5786'
year: '2012'
...
---
_id: '36921'
author:
- first_name: M. F.
  full_name: Oliveira, M. F.
  last_name: Oliveira
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: V.
  full_name: Esen, V.
  last_name: Esen
- first_name: W.
  full_name: Ecker, W.
  last_name: Ecker
citation:
  ama: 'Oliveira MF, Kuznik C, Müller W, Esen V, Ecker W. Towards an Enhanced UVM
    for SystemC. In: <i>Proceedings of the Design &#38; Verification Conference (DVCon)</i>.
    ; 2012.'
  apa: Oliveira, M. F., Kuznik, C., Müller, W., Esen, V., &#38; Ecker, W. (2012).
    Towards an Enhanced UVM for SystemC. <i>Proceedings of the Design &#38; Verification
    Conference (DVCon)</i>.
  bibtex: '@inproceedings{Oliveira_Kuznik_Müller_Esen_Ecker_2012, place={San Jose},
    title={Towards an Enhanced UVM for SystemC}, booktitle={Proceedings of the Design
    &#38; Verification Conference (DVCon)}, author={Oliveira, M. F. and Kuznik, Christoph
    and Müller, Wolfgang and Esen, V. and Ecker, W.}, year={2012} }'
  chicago: Oliveira, M. F., Christoph Kuznik, Wolfgang Müller, V. Esen, and W. Ecker.
    “Towards an Enhanced UVM for SystemC.” In <i>Proceedings of the Design &#38; Verification
    Conference (DVCon)</i>. San Jose, 2012.
  ieee: M. F. Oliveira, C. Kuznik, W. Müller, V. Esen, and W. Ecker, “Towards an Enhanced
    UVM for SystemC,” 2012.
  mla: Oliveira, M. F., et al. “Towards an Enhanced UVM for SystemC.” <i>Proceedings
    of the Design &#38; Verification Conference (DVCon)</i>, 2012.
  short: 'M.F. Oliveira, C. Kuznik, W. Müller, V. Esen, W. Ecker, in: Proceedings
    of the Design &#38; Verification Conference (DVCon), San Jose, 2012.'
date_created: 2023-01-16T12:19:39Z
date_updated: 2023-01-16T12:21:17Z
department:
- _id: '672'
language:
- iso: eng
place: San Jose
publication: Proceedings of the Design & Verification Conference (DVCon)
status: public
title: Towards an Enhanced UVM for SystemC
type: conference
user_id: '5786'
year: '2012'
...
---
_id: '36994'
abstract:
- lang: eng
  text: This paper proposes a quality driven, simulation based approach to functional
    design verification, which applies mainly to IP-level HDL designs with well specified
    test instruction format and is evaluated on a soft microprocessor core MB-LITE
    [5]. The approach utilizes mutation analysis as the quality metric to steer an
    automated simulation data generation process. It leads to a simulation flow with
    two phases towards an enhanced mutation analysis result. First in a random simulation
    phase, an in-loop heuristics is deployed and adjusts dynamically the test probability
    distribution so as to improve the coverage efficiency. Next, for each remaining
    hard-to-kill mutant, a search heuristics on test input space is developed to iteratively
    locate a target test, using a specific objective cost function for the goal of
    killing HDL mutant. The effectiveness of this integrated two-phase simulation
    flow is demonstrated by the results with the MB-LITE microprocessor IP.
author:
- first_name: 'Tao '
  full_name: 'Xie, Tao '
  last_name: Xie
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Florian
  full_name: Letombe, Florian
  last_name: Letombe
citation:
  ama: 'Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification
    of a Soft Microprocessor. In: <i>Proceedings of SOCC2012</i>. IEEE; 2012. doi:<a
    href="https://doi.org/10.1109/SOCC.2012.6398362">10.1109/SOCC.2012.6398362</a>'
  apa: Xie, T., Müller, W., &#38; Letombe, F. (2012). Mutation-Analysis Driven Functional
    Verification of a Soft Microprocessor. <i>Proceedings of SOCC2012</i>. <a href="https://doi.org/10.1109/SOCC.2012.6398362">https://doi.org/10.1109/SOCC.2012.6398362</a>
  bibtex: '@inproceedings{Xie_Müller_Letombe_2012, place={ Niagara Falls, NY, USA
    }, title={Mutation-Analysis Driven Functional Verification of a Soft Microprocessor},
    DOI={<a href="https://doi.org/10.1109/SOCC.2012.6398362">10.1109/SOCC.2012.6398362</a>},
    booktitle={Proceedings of SOCC2012}, publisher={IEEE}, author={Xie, Tao  and Müller,
    Wolfgang and Letombe, Florian}, year={2012} }'
  chicago: 'Xie, Tao , Wolfgang Müller, and Florian Letombe. “Mutation-Analysis Driven
    Functional Verification of a Soft Microprocessor.” In <i>Proceedings of SOCC2012</i>.  Niagara
    Falls, NY, USA : IEEE, 2012. <a href="https://doi.org/10.1109/SOCC.2012.6398362">https://doi.org/10.1109/SOCC.2012.6398362</a>.'
  ieee: 'T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification
    of a Soft Microprocessor,” 2012, doi: <a href="https://doi.org/10.1109/SOCC.2012.6398362">10.1109/SOCC.2012.6398362</a>.'
  mla: Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft
    Microprocessor.” <i>Proceedings of SOCC2012</i>, IEEE, 2012, doi:<a href="https://doi.org/10.1109/SOCC.2012.6398362">10.1109/SOCC.2012.6398362</a>.
  short: 'T. Xie, W. Müller, F. Letombe, in: Proceedings of SOCC2012, IEEE,  Niagara
    Falls, NY, USA , 2012.'
date_created: 2023-01-17T08:46:14Z
date_updated: 2023-01-17T08:46:29Z
department:
- _id: '672'
doi: 10.1109/SOCC.2012.6398362
keyword:
- Analytical models
- Hardware design languages
- Microprocessors
- Cost function
- Data models
- Search problems
- IP networks
language:
- iso: eng
place: ' Niagara Falls, NY, USA '
publication: Proceedings of SOCC2012
publication_identifier:
  eisbn:
  - 978-1-4673-1295-0
publisher: IEEE
status: public
title: Mutation-Analysis Driven Functional Verification of a Soft Microprocessor
type: conference
user_id: '5786'
year: '2012'
...
---
_id: '36997'
author:
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Xie T, Müller W. An IP-XACT-TO-SystemC Model Generator for Mutation Analysis.
    In: <i>Proceedings of the MeCoES’12</i>. ; 2012.'
  apa: Xie, T., &#38; Müller, W. (2012). An IP-XACT-TO-SystemC Model Generator for
    Mutation Analysis. <i>Proceedings of the MeCoES’12</i>.
  bibtex: '@inproceedings{Xie_Müller_2012, place={Tampere, Finnland}, title={An IP-XACT-TO-SystemC
    Model Generator for Mutation Analysis}, booktitle={Proceedings of the MeCoES’12},
    author={Xie, Tao and Müller, Wolfgang}, year={2012} }'
  chicago: Xie, Tao, and Wolfgang Müller. “An IP-XACT-TO-SystemC Model Generator for
    Mutation Analysis.” In <i>Proceedings of the MeCoES’12</i>. Tampere, Finnland,
    2012.
  ieee: T. Xie and W. Müller, “An IP-XACT-TO-SystemC Model Generator for Mutation
    Analysis,” 2012.
  mla: Xie, Tao, and Wolfgang Müller. “An IP-XACT-TO-SystemC Model Generator for Mutation
    Analysis.” <i>Proceedings of the MeCoES’12</i>, 2012.
  short: 'T. Xie, W. Müller, in: Proceedings of the MeCoES’12, Tampere, Finnland,
    2012.'
date_created: 2023-01-17T08:52:59Z
date_updated: 2023-01-17T08:53:54Z
department:
- _id: '672'
language:
- iso: eng
place: Tampere, Finnland
publication: Proceedings of the MeCoES’12
status: public
title: An IP-XACT-TO-SystemC Model Generator for Mutation Analysis
type: conference
user_id: '5786'
year: '2012'
...
---
_id: '26667'
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Kuznik C, Müller W. Aspect enhanced functional coverage driven verification
    in the SystemC HDVL. In: <i>Proc. of the 8th International SoC Design Conference
    2011 (ISOCC 2011)</i>. ; 2011.'
  apa: Kuznik, C., &#38; Müller, W. (2011). Aspect enhanced functional coverage driven
    verification in the SystemC HDVL. <i>Proc. of the 8th International SoC Design
    Conference 2011 (ISOCC 2011)</i>.
  bibtex: '@inproceedings{Kuznik_Müller_2011, title={Aspect enhanced functional coverage
    driven verification in the SystemC HDVL}, booktitle={Proc. of the 8th International
    SoC Design Conference 2011 (ISOCC 2011)}, author={Kuznik, Christoph and Müller,
    Wolfgang}, year={2011} }'
  chicago: Kuznik, Christoph, and Wolfgang Müller. “Aspect Enhanced Functional Coverage
    Driven Verification in the SystemC HDVL.” In <i>Proc. of the 8th International
    SoC Design Conference 2011 (ISOCC 2011)</i>, 2011.
  ieee: C. Kuznik and W. Müller, “Aspect enhanced functional coverage driven verification
    in the SystemC HDVL,” 2011.
  mla: Kuznik, Christoph, and Wolfgang Müller. “Aspect Enhanced Functional Coverage
    Driven Verification in the SystemC HDVL.” <i>Proc. of the 8th International SoC
    Design Conference 2011 (ISOCC 2011)</i>, 2011.
  short: 'C. Kuznik, W. Müller, in: Proc. of the 8th International SoC Design Conference
    2011 (ISOCC 2011), 2011.'
date_created: 2021-10-21T10:59:51Z
date_updated: 2022-01-06T06:57:25Z
department:
- _id: '672'
language:
- iso: eng
publication: Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011)
status: public
title: Aspect enhanced functional coverage driven verification in the SystemC HDVL
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26669'
author:
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Xie T, Müller W. IP-XACT based System Level Mutation Testing. In: <i>Proceedings
    of the 16th IEEE International High Level Design Validation and Test Workshop
    (HLDVT)</i>. ; 2011.'
  apa: Xie, T., &#38; Müller, W. (2011). IP-XACT based System Level Mutation Testing.
    <i>Proceedings of the 16th IEEE International High Level Design Validation and
    Test Workshop (HLDVT)</i>.
  bibtex: '@inproceedings{Xie_Müller_2011, title={IP-XACT based System Level Mutation
    Testing}, booktitle={Proceedings of the 16th IEEE International High Level Design
    Validation and Test Workshop (HLDVT)}, author={Xie, Tao and Müller, Wolfgang},
    year={2011} }'
  chicago: Xie, Tao, and Wolfgang Müller. “IP-XACT Based System Level Mutation Testing.”
    In <i>Proceedings of the 16th IEEE International High Level Design Validation
    and Test Workshop (HLDVT)</i>, 2011.
  ieee: T. Xie and W. Müller, “IP-XACT based System Level Mutation Testing,” 2011.
  mla: Xie, Tao, and Wolfgang Müller. “IP-XACT Based System Level Mutation Testing.”
    <i>Proceedings of the 16th IEEE International High Level Design Validation and
    Test Workshop (HLDVT)</i>, 2011.
  short: 'T. Xie, W. Müller, in: Proceedings of the 16th IEEE International High Level
    Design Validation and Test Workshop (HLDVT), 2011.'
date_created: 2021-10-21T11:04:35Z
date_updated: 2022-01-06T06:57:25Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of the 16th IEEE International High Level Design Validation
  and Test Workshop (HLDVT)
status: public
title: IP-XACT based System Level Mutation Testing
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26698'
author:
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Xie T, Müller W. HDL-Mutation Based Simulation Data Generation by Propagation
    Guided Search. In: <i>Proceedings of the 14th Euromicro Conference on Digital
    System Design (DSD)</i>. ; 2011.'
  apa: Xie, T., &#38; Müller, W. (2011). HDL-Mutation Based Simulation Data Generation
    by Propagation Guided Search. <i>Proceedings of the 14th Euromicro Conference
    on Digital System Design (DSD)</i>.
  bibtex: '@inproceedings{Xie_Müller_2011, title={HDL-Mutation Based Simulation Data
    Generation by Propagation Guided Search}, booktitle={Proceedings of the 14th Euromicro
    Conference on Digital System Design (DSD)}, author={Xie, Tao and Müller, Wolfgang},
    year={2011} }'
  chicago: Xie, Tao, and Wolfgang Müller. “HDL-Mutation Based Simulation Data Generation
    by Propagation Guided Search.” In <i>Proceedings of the 14th Euromicro Conference
    on Digital System Design (DSD)</i>, 2011.
  ieee: T. Xie and W. Müller, “HDL-Mutation Based Simulation Data Generation by Propagation
    Guided Search,” 2011.
  mla: Xie, Tao, and Wolfgang Müller. “HDL-Mutation Based Simulation Data Generation
    by Propagation Guided Search.” <i>Proceedings of the 14th Euromicro Conference
    on Digital System Design (DSD)</i>, 2011.
  short: 'T. Xie, W. Müller, in: Proceedings of the 14th Euromicro Conference on Digital
    System Design (DSD), 2011.'
date_created: 2021-10-21T12:22:19Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of the 14th Euromicro Conference on Digital System Design
  (DSD)
status: public
title: HDL-Mutation Based Simulation Data Generation by Propagation Guided Search
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26705'
abstract:
- lang: eng
  text: "In the area of dynamic verification of virtual prototypes, functional coverage
    is a valuable tool for answering the \"Are we done?\" question and achieving verification
    closure. Recent verification methodologies such as OVM and UVM contain multi-language
    support that provides a basic SystemC version. However, due to language shortcoming
    they cannot be utilized for the same amount of verification tasks in the SystemC
    ecosystem as in other supported hardware design and verification languages. In
    this presentation, we propose to boost the verification capabilities of SystemC
    by implementing functional coverage collection and evaluation according to the
    same metric as defined in the widely accepted IEEE-1800 SystemVerilog cover group
    feature. We implement a functional coverage library to enable coverage-driven
    verification of SystemC designs on multiple levels of abstraction enabling value,
    transition, and expression coverage. To our knowledge, the overall functionalities
    are not available in the IEEE-1666 SystemC standard or the SCV add-on library,
    nor are they complete compared to the aforementioned in any publicly available
    SystemC library.\r\n"
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: Kuznik C, Müller W. Verification Closure of SystemC Designs with Functional
    Coverage. <i>North American SystemC User Group Meeting (16th)</i>. Published online
    2011.
  apa: Kuznik, C., &#38; Müller, W. (2011). Verification Closure of SystemC Designs
    with Functional Coverage. <i>North American SystemC User Group Meeting (16th)</i>.
    Jun. 2011 - 16th North American User Group Meeting (NASCUG).
  bibtex: '@article{Kuznik_Müller_2011, title={Verification Closure of SystemC Designs
    with Functional Coverage}, journal={North American SystemC User Group Meeting
    (16th)}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2011} }'
  chicago: Kuznik, Christoph, and Wolfgang Müller. “Verification Closure of SystemC
    Designs with Functional Coverage.” <i>North American SystemC User Group Meeting
    (16th)</i>, 2011.
  ieee: C. Kuznik and W. Müller, “Verification Closure of SystemC Designs with Functional
    Coverage,” <i>North American SystemC User Group Meeting (16th)</i>, 2011.
  mla: Kuznik, Christoph, and Wolfgang Müller. “Verification Closure of SystemC Designs
    with Functional Coverage.” <i>North American SystemC User Group Meeting (16th)</i>,
    2011.
  short: C. Kuznik, W. Müller, North American SystemC User Group Meeting (16th) (2011).
conference:
  name: Jun. 2011 - 16th North American User Group Meeting (NASCUG)
date_created: 2021-10-21T12:37:44Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: North American SystemC User Group Meeting (16th)
status: public
title: Verification Closure of SystemC Designs with Functional Coverage
type: journal_article
user_id: '21240'
year: '2011'
...
---
_id: '26710'
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Ahmed
  full_name: Elfeky, Ahmed
  last_name: Elfeky
- first_name: Anthony
  full_name: DiPasquale, Anthony
  last_name: DiPasquale
citation:
  ama: "Becker M, Zabel H, Müller W, Elfeky A, DiPasquale A. Virtual Prototyping softwareintensiver
    mechatronischer Systeme \x96 Eine Fallstudie. In: <i>8. Paderborner Workshop Entwurf
    Mechatronischer Systeme, Band 294</i>. Vol 294. Verlagsschriftenreihe des Heinz
    Nixdorf Instituts, Paderborn; 2011:315-327."
  apa: "Becker, M., Zabel, H., Müller, W., Elfeky, A., &#38; DiPasquale, A. (2011).
    Virtual Prototyping softwareintensiver mechatronischer Systeme \x96 Eine Fallstudie.
    <i>8. Paderborner Workshop Entwurf Mechatronischer Systeme, Band 294</i>, <i>294</i>,
    315–327."
  bibtex: "@inproceedings{Becker_Zabel_Müller_Elfeky_DiPasquale_2011, title={Virtual
    Prototyping softwareintensiver mechatronischer Systeme \x96 Eine Fallstudie},
    volume={294}, booktitle={8. Paderborner Workshop Entwurf mechatronischer Systeme,
    Band 294}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn},
    author={Becker, Markus and Zabel, Henning and Müller, Wolfgang and Elfeky, Ahmed
    and DiPasquale, Anthony}, year={2011}, pages={315–327} }"
  chicago: "Becker, Markus, Henning Zabel, Wolfgang Müller, Ahmed Elfeky, and Anthony
    DiPasquale. “Virtual Prototyping Softwareintensiver Mechatronischer Systeme \x96
    Eine Fallstudie.” In <i>8. Paderborner Workshop Entwurf Mechatronischer Systeme,
    Band 294</i>, 294:315–27. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn,
    2011."
  ieee: "M. Becker, H. Zabel, W. Müller, A. Elfeky, and A. DiPasquale, “Virtual Prototyping
    softwareintensiver mechatronischer Systeme \x96 Eine Fallstudie,” in <i>8. Paderborner
    Workshop Entwurf mechatronischer Systeme, Band 294</i>, 2011, vol. 294, pp. 315–327."
  mla: "Becker, Markus, et al. “Virtual Prototyping Softwareintensiver Mechatronischer
    Systeme \x96 Eine Fallstudie.” <i>8. Paderborner Workshop Entwurf Mechatronischer
    Systeme, Band 294</i>, vol. 294, Verlagsschriftenreihe des Heinz Nixdorf Instituts,
    Paderborn, 2011, pp. 315–27."
  short: 'M. Becker, H. Zabel, W. Müller, A. Elfeky, A. DiPasquale, in: 8. Paderborner
    Workshop Entwurf Mechatronischer Systeme, Band 294, Verlagsschriftenreihe des
    Heinz Nixdorf Instituts, Paderborn, 2011, pp. 315–327.'
date_created: 2021-10-21T12:46:10Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
intvolume: '       294'
language:
- iso: eng
page: 315-327
publication: 8. Paderborner Workshop Entwurf mechatronischer Systeme, Band 294
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
status: public
title: "Virtual Prototyping softwareintensiver mechatronischer Systeme \x96 Eine Fallstudie"
type: conference
user_id: '21240'
volume: 294
year: '2011'
...
---
_id: '26713'
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: A.
  full_name: König, A.
  last_name: König
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Klobedanz K, König A, Müller W. A Reconfiguration Approach for Fault-Tolerant
    FlexRay Networks. In: <i>Proceedings of Design, Automation, Test Europe - DATE2011</i>.
    IEEE Computer Society Press; 2011.'
  apa: Klobedanz, K., König, A., &#38; Müller, W. (2011). A Reconfiguration Approach
    for Fault-Tolerant FlexRay Networks. <i>Proceedings of Design, Automation, Test
    Europe - DATE2011</i>.
  bibtex: '@inproceedings{Klobedanz_König_Müller_2011, place={Grenoble, France}, title={A
    Reconfiguration Approach for Fault-Tolerant FlexRay Networks}, booktitle={Proceedings
    of Design, Automation, Test Europe - DATE2011}, publisher={IEEE Computer Society
    Press}, author={Klobedanz, Kay and König, A. and Müller, Wolfgang}, year={2011}
    }'
  chicago: 'Klobedanz, Kay, A. König, and Wolfgang Müller. “A Reconfiguration Approach
    for Fault-Tolerant FlexRay Networks.” In <i>Proceedings of Design, Automation,
    Test Europe - DATE2011</i>. Grenoble, France: IEEE Computer Society Press, 2011.'
  ieee: K. Klobedanz, A. König, and W. Müller, “A Reconfiguration Approach for Fault-Tolerant
    FlexRay Networks,” 14. - 18. Mrz. 2011, 2011.
  mla: Klobedanz, Kay, et al. “A Reconfiguration Approach for Fault-Tolerant FlexRay
    Networks.” <i>Proceedings of Design, Automation, Test Europe - DATE2011</i>, IEEE
    Computer Society Press, 2011.
  short: 'K. Klobedanz, A. König, W. Müller, in: Proceedings of Design, Automation,
    Test Europe - DATE2011, IEEE Computer Society Press, Grenoble, France, 2011.'
conference:
  location: 14. - 18. Mrz. 2011
date_created: 2021-10-21T13:01:47Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
place: Grenoble, France
publication: Proceedings of Design, Automation, Test Europe - DATE2011
publisher: IEEE Computer Society Press
status: public
title: A Reconfiguration Approach for Fault-Tolerant FlexRay Networks
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26714'
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: A.
  full_name: König, A.
  last_name: König
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Achim
  full_name: Rettberg, Achim
  last_name: Rettberg
citation:
  ama: 'Klobedanz K, König A, Müller W, Rettberg A. Self-Reconfiguration for Fault-Tolerant
    FlexRay Networks. In: <i>Second IEEE Workshop on Self-Organizing Real-Time Systems
    - SORT 2011</i>. IEEE Computer Society Press; 2011.'
  apa: Klobedanz, K., König, A., Müller, W., &#38; Rettberg, A. (2011). Self-Reconfiguration
    for Fault-Tolerant FlexRay Networks. <i>Second IEEE Workshop on Self-Organizing
    Real-Time Systems - SORT 2011</i>.
  bibtex: '@inproceedings{Klobedanz_König_Müller_Rettberg_2011, place={Newport Beach,
    California, USA}, title={Self-Reconfiguration for Fault-Tolerant FlexRay Networks},
    booktitle={Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011},
    publisher={IEEE Computer Society Press}, author={Klobedanz, Kay and König, A.
    and Müller, Wolfgang and Rettberg, Achim}, year={2011} }'
  chicago: 'Klobedanz, Kay, A. König, Wolfgang Müller, and Achim Rettberg. “Self-Reconfiguration
    for Fault-Tolerant FlexRay Networks.” In <i>Second IEEE Workshop on Self-Organizing
    Real-Time Systems - SORT 2011</i>. Newport Beach, California, USA: IEEE Computer
    Society Press, 2011.'
  ieee: K. Klobedanz, A. König, W. Müller, and A. Rettberg, “Self-Reconfiguration
    for Fault-Tolerant FlexRay Networks,” 2011.
  mla: Klobedanz, Kay, et al. “Self-Reconfiguration for Fault-Tolerant FlexRay Networks.”
    <i>Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011</i>,
    IEEE Computer Society Press, 2011.
  short: 'K. Klobedanz, A. König, W. Müller, A. Rettberg, in: Second IEEE Workshop
    on Self-Organizing Real-Time Systems - SORT 2011, IEEE Computer Society Press,
    Newport Beach, California, USA, 2011.'
date_created: 2021-10-21T13:06:26Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
place: Newport Beach, California, USA
publication: Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011
publisher: IEEE Computer Society Press
status: public
title: Self-Reconfiguration for Fault-Tolerant FlexRay Networks
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26715'
abstract:
- lang: eng
  text: SystemC is a versatile C++ based design and verification language, offering
    various mechanisms and constructs required for embedded systems modeling. Using
    the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli
    techniques may be used for verification. However, SCV has several drawbacks such
    as lack of a functional coverage facility supporting coverage collection on RTL
    and TLM models. In this article we present a functional coverage library which
    implements parts of the IEEE 1800-2005 SystemVerilog standard capturing functional
    coverage throughout the design and verification process, and allows to facilitate
    coverage-driven verification in SystemC.
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Kuznik C, Müller W. Functional Coverage-driven Verification with SystemC on
    Multiple Level of Abstraction. In: <i>Proceedings of DVCON </i>. ; 2011.'
  apa: Kuznik, C., &#38; Müller, W. (2011). Functional Coverage-driven Verification
    with SystemC on Multiple Level of Abstraction. <i>Proceedings of DVCON </i>.
  bibtex: '@inproceedings{Kuznik_Müller_2011, title={Functional Coverage-driven Verification
    with SystemC on Multiple Level of Abstraction}, booktitle={Proceedings of DVCON
    }, author={Kuznik, Christoph and Müller, Wolfgang}, year={2011} }'
  chicago: Kuznik, Christoph, and Wolfgang Müller. “Functional Coverage-Driven Verification
    with SystemC on Multiple Level of Abstraction.” In <i>Proceedings of DVCON </i>,
    2011.
  ieee: C. Kuznik and W. Müller, “Functional Coverage-driven Verification with SystemC
    on Multiple Level of Abstraction,” 2011.
  mla: Kuznik, Christoph, and Wolfgang Müller. “Functional Coverage-Driven Verification
    with SystemC on Multiple Level of Abstraction.” <i>Proceedings of DVCON </i>,
    2011.
  short: 'C. Kuznik, W. Müller, in: Proceedings of DVCON , 2011.'
date_created: 2021-10-21T13:10:10Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: 'Proceedings of DVCON '
status: public
title: Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26716'
abstract:
- lang: eng
  text: UML profiles like SysML and MARTE have been a major research topic in electronic
    system design, but are mainly applied for specification and analysis in early
    design phases. High-Level Synthesis (HLS), however, addresses the physical implementation
    aspect of electronic systems, and thus leads to different requirements on the
    accuracy of models. For this, modular interfaces are a novel object-oriented synthesizable
    technique to overcome the conflict between a higher degree of abstraction and
    necessary details for further synthesis. In this paper, we present our approach
    to use SysML as an adequate modeling language for modular interfaces and C/C++/SystemC-based
    HLS. We extended SysML with annotations for synthesizable SystemC and high-level
    synthesis constraints and implemented a code generation scheme to achieve design
    flow automation. Based on the SysML editor Artisan Studio and an industrial case
    study, we demonstrate the applicability of SysML as a retargetable front-end for
    HLS design flows.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Mischkalla F, He D, Müller W. A Retargetable SysML-based Front-End for High-Level
    Synthesis. In: <i>Proceedings of 2nd Workshop on Model Based Engineering for Embedded
    Systems Design (M-BED)</i>. ; 2011.'
  apa: Mischkalla, F., He, D., &#38; Müller, W. (2011). A Retargetable SysML-based
    Front-End for High-Level Synthesis. <i>Proceedings of 2nd Workshop on Model Based
    Engineering for Embedded Systems Design (M-BED)</i>.
  bibtex: '@inproceedings{Mischkalla_He_Müller_2011, title={A Retargetable SysML-based
    Front-End for High-Level Synthesis}, booktitle={Proceedings of 2nd Workshop on
    Model Based Engineering for Embedded Systems Design (M-BED)}, author={Mischkalla,
    Fabian and He, Da and Müller, Wolfgang}, year={2011} }'
  chicago: Mischkalla, Fabian, Da He, and Wolfgang Müller. “A Retargetable SysML-Based
    Front-End for High-Level Synthesis.” In <i>Proceedings of 2nd Workshop on Model
    Based Engineering for Embedded Systems Design (M-BED)</i>, 2011.
  ieee: F. Mischkalla, D. He, and W. Müller, “A Retargetable SysML-based Front-End
    for High-Level Synthesis,” 2011.
  mla: Mischkalla, Fabian, et al. “A Retargetable SysML-Based Front-End for High-Level
    Synthesis.” <i>Proceedings of 2nd Workshop on Model Based Engineering for Embedded
    Systems Design (M-BED)</i>, 2011.
  short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of 2nd Workshop on Model
    Based Engineering for Embedded Systems Design (M-BED), 2011.'
date_created: 2021-10-21T13:16:24Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems
  Design (M-BED)
status: public
title: A Retargetable SysML-based Front-End for High-Level Synthesis
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26717'
author:
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'He D, Mischkalla F, Müller W. A SysML-based Framework with QEMU-SystemC Code
    Generation. In: <i>Proceedings of 1st International QEMU Users Forum</i>. ; 2011.'
  apa: He, D., Mischkalla, F., &#38; Müller, W. (2011). A SysML-based Framework with
    QEMU-SystemC Code Generation. <i>Proceedings of 1st International QEMU Users Forum</i>.
  bibtex: '@inproceedings{He_Mischkalla_Müller_2011, title={A SysML-based Framework
    with QEMU-SystemC Code Generation}, booktitle={Proceedings of 1st international
    QEMU Users Forum}, author={He, Da and Mischkalla, Fabian and Müller, Wolfgang},
    year={2011} }'
  chicago: He, Da, Fabian Mischkalla, and Wolfgang Müller. “A SysML-Based Framework
    with QEMU-SystemC Code Generation.” In <i>Proceedings of 1st International QEMU
    Users Forum</i>, 2011.
  ieee: D. He, F. Mischkalla, and W. Müller, “A SysML-based Framework with QEMU-SystemC
    Code Generation,” 2011.
  mla: He, Da, et al. “A SysML-Based Framework with QEMU-SystemC Code Generation.”
    <i>Proceedings of 1st International QEMU Users Forum</i>, 2011.
  short: 'D. He, F. Mischkalla, W. Müller, in: Proceedings of 1st International QEMU
    Users Forum, 2011.'
date_created: 2021-10-21T13:18:27Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of 1st international QEMU Users Forum
status: public
title: A SysML-based Framework with QEMU-SystemC Code Generation
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26784'
author:
- first_name: Gilles Bertrand
  full_name: Gnokam Defo, Gilles Bertrand
  last_name: Gnokam Defo
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Gnokam Defo GB, Müller W. Synchronisation eines SystemC Restbus-Simulators
    mit einem Hardware-In-the-Loop FlexRay Netzwerk. In: <i>Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>. ; 2011.'
  apa: Gnokam Defo, G. B., &#38; Müller, W. (2011). Synchronisation eines SystemC
    Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk. <i>Methoden
    Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und
    Systemen (MBMV)</i>.
  bibtex: '@inproceedings{Gnokam Defo_Müller_2011, title={Synchronisation eines SystemC
    Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk}, booktitle={Methoden
    und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
    Systemen (MBMV)}, author={Gnokam Defo, Gilles Bertrand and Müller, Wolfgang},
    year={2011} }'
  chicago: Gnokam Defo, Gilles Bertrand, and Wolfgang Müller. “Synchronisation Eines
    SystemC Restbus-Simulators Mit Einem Hardware-In-the-Loop FlexRay Netzwerk.” In
    <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
    Und Systemen (MBMV)</i>, 2011.
  ieee: G. B. Gnokam Defo and W. Müller, “Synchronisation eines SystemC Restbus-Simulators
    mit einem Hardware-In-the-Loop FlexRay Netzwerk,” 2011.
  mla: Gnokam Defo, Gilles Bertrand, and Wolfgang Müller. “Synchronisation Eines SystemC
    Restbus-Simulators Mit Einem Hardware-In-the-Loop FlexRay Netzwerk.” <i>Methoden
    Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und
    Systemen (MBMV)</i>, 2011.
  short: 'G.B. Gnokam Defo, W. Müller, in: Methoden Und Beschreibungssprachen Zur
    Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), 2011.'
date_created: 2021-10-25T09:57:05Z
date_updated: 2022-01-06T06:57:28Z
department:
- _id: '672'
language:
- iso: eng
publication: Methoden und Beschreibungssprachen zur Modellierung und Verifikation
  von Schaltungen und Systemen (MBMV)
status: public
title: Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop
  FlexRay Netzwerk
type: conference
user_id: '21240'
year: '2011'
...