---
_id: '26714'
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: A.
  full_name: König, A.
  last_name: König
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Achim
  full_name: Rettberg, Achim
  last_name: Rettberg
citation:
  ama: 'Klobedanz K, König A, Müller W, Rettberg A. Self-Reconfiguration for Fault-Tolerant
    FlexRay Networks. In: <i>Second IEEE Workshop on Self-Organizing Real-Time Systems
    - SORT 2011</i>. IEEE Computer Society Press; 2011.'
  apa: Klobedanz, K., König, A., Müller, W., &#38; Rettberg, A. (2011). Self-Reconfiguration
    for Fault-Tolerant FlexRay Networks. <i>Second IEEE Workshop on Self-Organizing
    Real-Time Systems - SORT 2011</i>.
  bibtex: '@inproceedings{Klobedanz_König_Müller_Rettberg_2011, place={Newport Beach,
    California, USA}, title={Self-Reconfiguration for Fault-Tolerant FlexRay Networks},
    booktitle={Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011},
    publisher={IEEE Computer Society Press}, author={Klobedanz, Kay and König, A.
    and Müller, Wolfgang and Rettberg, Achim}, year={2011} }'
  chicago: 'Klobedanz, Kay, A. König, Wolfgang Müller, and Achim Rettberg. “Self-Reconfiguration
    for Fault-Tolerant FlexRay Networks.” In <i>Second IEEE Workshop on Self-Organizing
    Real-Time Systems - SORT 2011</i>. Newport Beach, California, USA: IEEE Computer
    Society Press, 2011.'
  ieee: K. Klobedanz, A. König, W. Müller, and A. Rettberg, “Self-Reconfiguration
    for Fault-Tolerant FlexRay Networks,” 2011.
  mla: Klobedanz, Kay, et al. “Self-Reconfiguration for Fault-Tolerant FlexRay Networks.”
    <i>Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011</i>,
    IEEE Computer Society Press, 2011.
  short: 'K. Klobedanz, A. König, W. Müller, A. Rettberg, in: Second IEEE Workshop
    on Self-Organizing Real-Time Systems - SORT 2011, IEEE Computer Society Press,
    Newport Beach, California, USA, 2011.'
date_created: 2021-10-21T13:06:26Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
place: Newport Beach, California, USA
publication: Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011
publisher: IEEE Computer Society Press
status: public
title: Self-Reconfiguration for Fault-Tolerant FlexRay Networks
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26715'
abstract:
- lang: eng
  text: SystemC is a versatile C++ based design and verification language, offering
    various mechanisms and constructs required for embedded systems modeling. Using
    the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli
    techniques may be used for verification. However, SCV has several drawbacks such
    as lack of a functional coverage facility supporting coverage collection on RTL
    and TLM models. In this article we present a functional coverage library which
    implements parts of the IEEE 1800-2005 SystemVerilog standard capturing functional
    coverage throughout the design and verification process, and allows to facilitate
    coverage-driven verification in SystemC.
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Kuznik C, Müller W. Functional Coverage-driven Verification with SystemC on
    Multiple Level of Abstraction. In: <i>Proceedings of DVCON </i>. ; 2011.'
  apa: Kuznik, C., &#38; Müller, W. (2011). Functional Coverage-driven Verification
    with SystemC on Multiple Level of Abstraction. <i>Proceedings of DVCON </i>.
  bibtex: '@inproceedings{Kuznik_Müller_2011, title={Functional Coverage-driven Verification
    with SystemC on Multiple Level of Abstraction}, booktitle={Proceedings of DVCON
    }, author={Kuznik, Christoph and Müller, Wolfgang}, year={2011} }'
  chicago: Kuznik, Christoph, and Wolfgang Müller. “Functional Coverage-Driven Verification
    with SystemC on Multiple Level of Abstraction.” In <i>Proceedings of DVCON </i>,
    2011.
  ieee: C. Kuznik and W. Müller, “Functional Coverage-driven Verification with SystemC
    on Multiple Level of Abstraction,” 2011.
  mla: Kuznik, Christoph, and Wolfgang Müller. “Functional Coverage-Driven Verification
    with SystemC on Multiple Level of Abstraction.” <i>Proceedings of DVCON </i>,
    2011.
  short: 'C. Kuznik, W. Müller, in: Proceedings of DVCON , 2011.'
date_created: 2021-10-21T13:10:10Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: 'Proceedings of DVCON '
status: public
title: Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26716'
abstract:
- lang: eng
  text: UML profiles like SysML and MARTE have been a major research topic in electronic
    system design, but are mainly applied for specification and analysis in early
    design phases. High-Level Synthesis (HLS), however, addresses the physical implementation
    aspect of electronic systems, and thus leads to different requirements on the
    accuracy of models. For this, modular interfaces are a novel object-oriented synthesizable
    technique to overcome the conflict between a higher degree of abstraction and
    necessary details for further synthesis. In this paper, we present our approach
    to use SysML as an adequate modeling language for modular interfaces and C/C++/SystemC-based
    HLS. We extended SysML with annotations for synthesizable SystemC and high-level
    synthesis constraints and implemented a code generation scheme to achieve design
    flow automation. Based on the SysML editor Artisan Studio and an industrial case
    study, we demonstrate the applicability of SysML as a retargetable front-end for
    HLS design flows.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Mischkalla F, He D, Müller W. A Retargetable SysML-based Front-End for High-Level
    Synthesis. In: <i>Proceedings of 2nd Workshop on Model Based Engineering for Embedded
    Systems Design (M-BED)</i>. ; 2011.'
  apa: Mischkalla, F., He, D., &#38; Müller, W. (2011). A Retargetable SysML-based
    Front-End for High-Level Synthesis. <i>Proceedings of 2nd Workshop on Model Based
    Engineering for Embedded Systems Design (M-BED)</i>.
  bibtex: '@inproceedings{Mischkalla_He_Müller_2011, title={A Retargetable SysML-based
    Front-End for High-Level Synthesis}, booktitle={Proceedings of 2nd Workshop on
    Model Based Engineering for Embedded Systems Design (M-BED)}, author={Mischkalla,
    Fabian and He, Da and Müller, Wolfgang}, year={2011} }'
  chicago: Mischkalla, Fabian, Da He, and Wolfgang Müller. “A Retargetable SysML-Based
    Front-End for High-Level Synthesis.” In <i>Proceedings of 2nd Workshop on Model
    Based Engineering for Embedded Systems Design (M-BED)</i>, 2011.
  ieee: F. Mischkalla, D. He, and W. Müller, “A Retargetable SysML-based Front-End
    for High-Level Synthesis,” 2011.
  mla: Mischkalla, Fabian, et al. “A Retargetable SysML-Based Front-End for High-Level
    Synthesis.” <i>Proceedings of 2nd Workshop on Model Based Engineering for Embedded
    Systems Design (M-BED)</i>, 2011.
  short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of 2nd Workshop on Model
    Based Engineering for Embedded Systems Design (M-BED), 2011.'
date_created: 2021-10-21T13:16:24Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems
  Design (M-BED)
status: public
title: A Retargetable SysML-based Front-End for High-Level Synthesis
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26717'
author:
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'He D, Mischkalla F, Müller W. A SysML-based Framework with QEMU-SystemC Code
    Generation. In: <i>Proceedings of 1st International QEMU Users Forum</i>. ; 2011.'
  apa: He, D., Mischkalla, F., &#38; Müller, W. (2011). A SysML-based Framework with
    QEMU-SystemC Code Generation. <i>Proceedings of 1st International QEMU Users Forum</i>.
  bibtex: '@inproceedings{He_Mischkalla_Müller_2011, title={A SysML-based Framework
    with QEMU-SystemC Code Generation}, booktitle={Proceedings of 1st international
    QEMU Users Forum}, author={He, Da and Mischkalla, Fabian and Müller, Wolfgang},
    year={2011} }'
  chicago: He, Da, Fabian Mischkalla, and Wolfgang Müller. “A SysML-Based Framework
    with QEMU-SystemC Code Generation.” In <i>Proceedings of 1st International QEMU
    Users Forum</i>, 2011.
  ieee: D. He, F. Mischkalla, and W. Müller, “A SysML-based Framework with QEMU-SystemC
    Code Generation,” 2011.
  mla: He, Da, et al. “A SysML-Based Framework with QEMU-SystemC Code Generation.”
    <i>Proceedings of 1st International QEMU Users Forum</i>, 2011.
  short: 'D. He, F. Mischkalla, W. Müller, in: Proceedings of 1st International QEMU
    Users Forum, 2011.'
date_created: 2021-10-21T13:18:27Z
date_updated: 2022-01-06T06:57:26Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of 1st international QEMU Users Forum
status: public
title: A SysML-based Framework with QEMU-SystemC Code Generation
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26784'
author:
- first_name: Gilles Bertrand
  full_name: Gnokam Defo, Gilles Bertrand
  last_name: Gnokam Defo
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Gnokam Defo GB, Müller W. Synchronisation eines SystemC Restbus-Simulators
    mit einem Hardware-In-the-Loop FlexRay Netzwerk. In: <i>Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV)</i>. ; 2011.'
  apa: Gnokam Defo, G. B., &#38; Müller, W. (2011). Synchronisation eines SystemC
    Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk. <i>Methoden
    Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und
    Systemen (MBMV)</i>.
  bibtex: '@inproceedings{Gnokam Defo_Müller_2011, title={Synchronisation eines SystemC
    Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk}, booktitle={Methoden
    und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
    Systemen (MBMV)}, author={Gnokam Defo, Gilles Bertrand and Müller, Wolfgang},
    year={2011} }'
  chicago: Gnokam Defo, Gilles Bertrand, and Wolfgang Müller. “Synchronisation Eines
    SystemC Restbus-Simulators Mit Einem Hardware-In-the-Loop FlexRay Netzwerk.” In
    <i>Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
    Und Systemen (MBMV)</i>, 2011.
  ieee: G. B. Gnokam Defo and W. Müller, “Synchronisation eines SystemC Restbus-Simulators
    mit einem Hardware-In-the-Loop FlexRay Netzwerk,” 2011.
  mla: Gnokam Defo, Gilles Bertrand, and Wolfgang Müller. “Synchronisation Eines SystemC
    Restbus-Simulators Mit Einem Hardware-In-the-Loop FlexRay Netzwerk.” <i>Methoden
    Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und
    Systemen (MBMV)</i>, 2011.
  short: 'G.B. Gnokam Defo, W. Müller, in: Methoden Und Beschreibungssprachen Zur
    Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), 2011.'
date_created: 2021-10-25T09:57:05Z
date_updated: 2022-01-06T06:57:28Z
department:
- _id: '672'
language:
- iso: eng
publication: Methoden und Beschreibungssprachen zur Modellierung und Verifikation
  von Schaltungen und Systemen (MBMV)
status: public
title: Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop
  FlexRay Netzwerk
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '26789'
abstract:
- lang: eng
  text: Mutation analysis is a powerful tool for white-box testing of the verification
    environment in order to produce dependable and higher quality software products.
    However, due to high computational costs and the focus on high-level software
    languages such as Java mutation analysis is not yet widely used in commercial
    design flows targeting embedded (software) systems. Here the industry is modeling
    both hardware and related software parts at higher levels of abstraction, called
    virtual prototypes, to accelerate parallel development and shorten time-to-market.
    In this paper we propose a mutation testing verification flow for SystemC based
    virtual prototypes that may not rely on source code only but on annotated basic
    blocks and enables mutant creation at assembler level to heavily reduce execution
    costs and equivalence mutants likelihood.
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Kuznik C, Müller W. Native binary mutation analysis for embedded software
    and virtual prototypes in SystemC. In: <i>Proceedings of the 17th IEEE Pacific
    Rim International Symposium on Dependable Computing</i>. ; 2011.'
  apa: Kuznik, C., &#38; Müller, W. (2011). Native binary mutation analysis for embedded
    software and virtual prototypes in SystemC. <i>Proceedings of the 17th IEEE Pacific
    Rim International Symposium on Dependable Computing</i>.
  bibtex: '@inproceedings{Kuznik_Müller_2011, title={Native binary mutation analysis
    for embedded software and virtual prototypes in SystemC}, booktitle={Proceedings
    of the 17th IEEE Pacific Rim International Symposium on Dependable Computing},
    author={Kuznik, Christoph and Müller, Wolfgang}, year={2011} }'
  chicago: Kuznik, Christoph, and Wolfgang Müller. “Native Binary Mutation Analysis
    for Embedded Software and Virtual Prototypes in SystemC.” In <i>Proceedings of
    the 17th IEEE Pacific Rim International Symposium on Dependable Computing</i>,
    2011.
  ieee: C. Kuznik and W. Müller, “Native binary mutation analysis for embedded software
    and virtual prototypes in SystemC,” 2011.
  mla: Kuznik, Christoph, and Wolfgang Müller. “Native Binary Mutation Analysis for
    Embedded Software and Virtual Prototypes in SystemC.” <i>Proceedings of the 17th
    IEEE Pacific Rim International Symposium on Dependable Computing</i>, 2011.
  short: 'C. Kuznik, W. Müller, in: Proceedings of the 17th IEEE Pacific Rim International
    Symposium on Dependable Computing, 2011.'
date_created: 2021-10-25T10:02:47Z
date_updated: 2022-01-06T06:57:28Z
department:
- _id: '672'
language:
- iso: eng
publication: Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable
  Computing
status: public
title: Native binary mutation analysis for embedded software and virtual prototypes
  in SystemC
type: conference
user_id: '21240'
year: '2011'
...
---
_id: '53580'
citation:
  ama: Müller W, Petrot F, eds. <i>Proceedings of the 1st International QEMU Users’
    Forum</i>.; 2011.
  apa: Müller, W., &#38; Petrot, F. (Eds.). (2011). <i>Proceedings of the 1st International
    QEMU Users’ Forum</i>.
  bibtex: '@book{Müller_Petrot_2011, title={Proceedings of the 1st International QEMU
    Users’ Forum}, year={2011} }'
  chicago: Müller, Wolfgang, and Frederic Petrot, eds. <i>Proceedings of the 1st International
    QEMU Users’ Forum</i>, 2011.
  ieee: W. Müller and F. Petrot, Eds., <i>Proceedings of the 1st International QEMU
    Users’ Forum</i>. 2011.
  mla: Müller, Wolfgang, and Frederic Petrot, editors. <i>Proceedings of the 1st International
    QEMU Users’ Forum</i>. 2011.
  short: W. Müller, F. Petrot, eds., Proceedings of the 1st International QEMU Users’
    Forum, 2011.
conference:
  location: Grenoble, France
date_created: 2024-04-18T20:38:07Z
date_updated: 2024-04-18T22:16:00Z
department:
- _id: '58'
editor:
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Frederic
  full_name: Petrot, Frederic
  last_name: Petrot
language:
- iso: eng
status: public
title: Proceedings of the 1st International QEMU Users' Forum
type: book_editor
user_id: '16243'
year: '2011'
...
---
_id: '37001'
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Ahmed
  full_name: Elfeky, Ahmed
  last_name: Elfeky
citation:
  ama: 'Becker M, Zabel H, Müller W, Elfeky A. Virtual Prototyping software-intensiver
    mechatronischer Systeme - Eine Fallstudie. In: ; 2011.'
  apa: Becker, M., Zabel, H., Müller, W., &#38; Elfeky, A. (2011). <i>Virtual Prototyping
    software-intensiver mechatronischer Systeme - Eine Fallstudie</i>. 8. Paderborner
    Workshop Entwurf Mechatronischer Systeme.
  bibtex: '@inproceedings{Becker_Zabel_Müller_Elfeky_2011, place={Paderborn}, title={Virtual
    Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie}, author={Becker,
    Markus and Zabel, Henning and Müller, Wolfgang and Elfeky, Ahmed}, year={2011}
    }'
  chicago: Becker, Markus, Henning Zabel, Wolfgang Müller, and Ahmed Elfeky. “Virtual
    Prototyping Software-Intensiver Mechatronischer Systeme - Eine Fallstudie.” Paderborn,
    2011.
  ieee: M. Becker, H. Zabel, W. Müller, and A. Elfeky, “Virtual Prototyping software-intensiver
    mechatronischer Systeme - Eine Fallstudie,” presented at the 8. Paderborner Workshop
    Entwurf Mechatronischer Systeme, 2011.
  mla: Becker, Markus, et al. <i>Virtual Prototyping Software-Intensiver Mechatronischer
    Systeme - Eine Fallstudie</i>. 2011.
  short: 'M. Becker, H. Zabel, W. Müller, A. Elfeky, in: Paderborn, 2011.'
conference:
  name: 8. Paderborner Workshop Entwurf Mechatronischer Systeme
date_created: 2023-01-17T08:59:23Z
date_updated: 2023-01-17T08:59:47Z
department:
- _id: '672'
language:
- iso: eng
place: Paderborn
status: public
title: Virtual Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie
type: conference
user_id: '5786'
year: '2011'
...
---
_id: '37005'
author:
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Kuznik C, Müller W. A SystemC Based Library for Functional Coverage. In: ;
    2011.'
  apa: Kuznik, C., &#38; Müller, W. (2011). <i>A SystemC Based Library for Functional
    Coverage</i>. Proceedings of the Design and Verification Conference (DVCON 2011),
    San Jose, CA.
  bibtex: '@inproceedings{Kuznik_Müller_2011, title={A SystemC Based Library for Functional
    Coverage}, author={Kuznik, Christoph and Müller, Wolfgang}, year={2011} }'
  chicago: Kuznik, Christoph, and Wolfgang Müller. “A SystemC Based Library for Functional
    Coverage,” 2011.
  ieee: C. Kuznik and W. Müller, “A SystemC Based Library for Functional Coverage,”
    presented at the Proceedings of the Design and Verification Conference (DVCON
    2011), San Jose, CA, 2011.
  mla: Kuznik, Christoph, and Wolfgang Müller. <i>A SystemC Based Library for Functional
    Coverage</i>. 2011.
  short: 'C. Kuznik, W. Müller, in: 2011.'
conference:
  location: San Jose, CA
  name: Proceedings of the Design and Verification Conference (DVCON 2011)
date_created: 2023-01-17T09:05:48Z
date_updated: 2023-01-17T09:05:58Z
department:
- _id: '672'
language:
- iso: eng
status: public
title: A SystemC Based Library for Functional Coverage
type: conference
user_id: '5786'
year: '2011'
...
---
_id: '37006'
abstract:
- lang: eng
  text: In this paper we present an approach for the configuration and reconfiguration
    of FlexRay networks to increase their fault tolerance. To guarantee a correct
    and deterministic system behavior, the FlexRay specification does not allow a
    reconfiguration of the schedapproachule during run time. To avoid the necessity
    of a complete bus restart in case of a node failure, we propose a reconfiguration
    using redundant slots in the schedule and/or combine messages in existing frames
    and slots, to compensate node failures and increase robustness. Our approach supports
    the developer to increase the fault tolerance of the system during the design
    phase. It is a heuristic, which, additionally to a determined initial configuration,
    calculates possible reconfigurations for the remaining nodes of the FlexRay network
    in case of a node failure, to keep the system working properly. An evaluation
    by means of realistic safety-critical automotive real-time systems revealed that
    it determines valid reconfigurations for up to 80% of possible individual node
    failures. In summary, our approach offers major support for the developer of FlexRay
    networks since the results provide helpful feedback about reconfiguration capabilities.
    In an iterative design process these information can be used to determine and
    optimize valid reconfigurations.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Andreas
  full_name: König, Andreas
  last_name: König
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Klobedanz K, König A, Müller W. A Reconfiguration Approach for Faul-Tolerant
    FlexRay Networks. In: <i>Proceedings of DATE’11</i>. IEEE; 2011. doi:<a href="https://doi.org/10.1109/DATE.2011.5763022">10.1109/DATE.2011.5763022</a>'
  apa: Klobedanz, K., König, A., &#38; Müller, W. (2011). A Reconfiguration Approach
    for Faul-Tolerant FlexRay Networks. <i>Proceedings of DATE’11</i>. 2011 Design,
    Automation &#38; Test in Europe, Grenoble, France. <a href="https://doi.org/10.1109/DATE.2011.5763022">https://doi.org/10.1109/DATE.2011.5763022</a>
  bibtex: '@inproceedings{Klobedanz_König_Müller_2011, place={Grenoble, France}, title={A
    Reconfiguration Approach for Faul-Tolerant FlexRay Networks}, DOI={<a href="https://doi.org/10.1109/DATE.2011.5763022">10.1109/DATE.2011.5763022</a>},
    booktitle={Proceedings of DATE’11}, publisher={IEEE}, author={Klobedanz, Kay and
    König, Andreas and Müller, Wolfgang}, year={2011} }'
  chicago: 'Klobedanz, Kay, Andreas König, and Wolfgang Müller. “A Reconfiguration
    Approach for Faul-Tolerant FlexRay Networks.” In <i>Proceedings of DATE’11</i>.
    Grenoble, France: IEEE, 2011. <a href="https://doi.org/10.1109/DATE.2011.5763022">https://doi.org/10.1109/DATE.2011.5763022</a>.'
  ieee: 'K. Klobedanz, A. König, and W. Müller, “A Reconfiguration Approach for Faul-Tolerant
    FlexRay Networks,” presented at the 2011 Design, Automation &#38; Test in Europe,
    Grenoble, France, 2011, doi: <a href="https://doi.org/10.1109/DATE.2011.5763022">10.1109/DATE.2011.5763022</a>.'
  mla: Klobedanz, Kay, et al. “A Reconfiguration Approach for Faul-Tolerant FlexRay
    Networks.” <i>Proceedings of DATE’11</i>, IEEE, 2011, doi:<a href="https://doi.org/10.1109/DATE.2011.5763022">10.1109/DATE.2011.5763022</a>.
  short: 'K. Klobedanz, A. König, W. Müller, in: Proceedings of DATE’11, IEEE, Grenoble,
    France, 2011.'
conference:
  location: Grenoble, France
  name: 2011 Design, Automation & Test in Europe
date_created: 2023-01-17T09:09:25Z
date_updated: 2023-01-17T09:09:33Z
department:
- _id: '672'
doi: 10.1109/DATE.2011.5763022
keyword:
- Schedules
- Fault tolerant systems
- Redundancy
- Protocols
- Automotive engineering
- Genetic algorithms
language:
- iso: eng
place: Grenoble, France
publication: Proceedings of DATE'11
publisher: IEEE
status: public
title: A Reconfiguration Approach for Faul-Tolerant FlexRay Networks
type: conference
user_id: '5786'
year: '2011'
...
---
_id: '37002'
abstract:
- lang: eng
  text: HDL-mutation based fault injection and analysis is considered as an important
    coverage metric for measuring the quality of design simulation processes [20,
    3, 1, 2]. In this work, we try to solve the problem of automatic simulation data
    generation targeting HDL mutation faults. We follow a search based approach and
    eliminate the need for symbolic execution and mathematical constraint solving
    from existing work. An objective cost function is defined on the test input space
    and serves the guidance of search for fault-detecting test data. This is done
    by first mapping the simulation traces under a test onto a control and data flow
    graph structure which is extracted from the design. Then the progress of fault
    detection can be measured quantitatively on this graph to be the cost value. By
    minimizing this cost we approach the target test data. The effectiveness of the
    cost function is investigated under an example neighborhood search scheme. Case
    study with a floating point arithmetic IP design has shown that the cost function
    is able to guide effectively the search procedure towards a fault-detecting test.
    The cost calculation time as the search overhead was also observed to be minor
    compared to the actual design simulation time.
author:
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Florian
  full_name: Letombe, Florian
  last_name: Letombe
citation:
  ama: 'Xie T, Müller W, Letombe F. HDL-Mutation Based Simulation Data Generation
    by Propagation Guided Search. In: <i>Proceedings of Euromicro DSD 2011</i>. IEEE;
    2011. doi:<a href="https://doi.org/10.1109/DSD.2011.83">10.1109/DSD.2011.83</a>'
  apa: Xie, T., Müller, W., &#38; Letombe, F. (2011). HDL-Mutation Based Simulation
    Data Generation by Propagation Guided Search. <i>Proceedings of Euromicro DSD
    2011</i>. <a href="https://doi.org/10.1109/DSD.2011.83">https://doi.org/10.1109/DSD.2011.83</a>
  bibtex: '@inproceedings{Xie_Müller_Letombe_2011, place={Oulu, Finnland}, title={HDL-Mutation
    Based Simulation Data Generation by Propagation Guided Search}, DOI={<a href="https://doi.org/10.1109/DSD.2011.83">10.1109/DSD.2011.83</a>},
    booktitle={Proceedings of Euromicro DSD 2011}, publisher={IEEE}, author={Xie,
    Tao and Müller, Wolfgang and Letombe, Florian}, year={2011} }'
  chicago: 'Xie, Tao, Wolfgang Müller, and Florian Letombe. “HDL-Mutation Based Simulation
    Data Generation by Propagation Guided Search.” In <i>Proceedings of Euromicro
    DSD 2011</i>. Oulu, Finnland: IEEE, 2011. <a href="https://doi.org/10.1109/DSD.2011.83">https://doi.org/10.1109/DSD.2011.83</a>.'
  ieee: 'T. Xie, W. Müller, and F. Letombe, “HDL-Mutation Based Simulation Data Generation
    by Propagation Guided Search,” 2011, doi: <a href="https://doi.org/10.1109/DSD.2011.83">10.1109/DSD.2011.83</a>.'
  mla: Xie, Tao, et al. “HDL-Mutation Based Simulation Data Generation by Propagation
    Guided Search.” <i>Proceedings of Euromicro DSD 2011</i>, IEEE, 2011, doi:<a href="https://doi.org/10.1109/DSD.2011.83">10.1109/DSD.2011.83</a>.
  short: 'T. Xie, W. Müller, F. Letombe, in: Proceedings of Euromicro DSD 2011, IEEE,
    Oulu, Finnland, 2011.'
date_created: 2023-01-17T09:02:48Z
date_updated: 2025-02-26T14:44:15Z
department:
- _id: '672'
doi: 10.1109/DSD.2011.83
keyword:
- Hardware design languages
- Cost function
- Computational modeling
- Fault detection
- Data models
- Analytical models
- Testing
language:
- iso: eng
place: Oulu, Finnland
publication: Proceedings of Euromicro DSD 2011
publication_identifier:
  isbn:
  - 978-1-4577-1048-3
publisher: IEEE
status: public
title: HDL-Mutation Based Simulation Data Generation by Propagation Guided Search
type: conference
user_id: '5786'
year: '2011'
...
---
_id: '36999'
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Ahmed
  full_name: Elfeky, Ahmed
  last_name: Elfeky
citation:
  ama: 'Becker M, Zabel H, Müller W, Elfeky A. Virtual Prototyping software-intensiver
    mechatronischer Systeme - Eine Fallstudie. In: ; 2011.'
  apa: Becker, M., Zabel, H., Müller, W., &#38; Elfeky, A. (2011). <i>Virtual Prototyping
    software-intensiver mechatronischer Systeme - Eine Fallstudie</i>. 8. Paderborner
    Workshop Entwurf Mechatronischer Systeme.
  bibtex: '@inproceedings{Becker_Zabel_Müller_Elfeky_2011, place={Paderborn}, title={Virtual
    Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie}, author={Becker,
    Markus and Zabel, Henning and Müller, Wolfgang and Elfeky, Ahmed}, year={2011}
    }'
  chicago: Becker, Markus, Henning Zabel, Wolfgang Müller, and Ahmed Elfeky. “Virtual
    Prototyping Software-Intensiver Mechatronischer Systeme - Eine Fallstudie.” Paderborn,
    2011.
  ieee: M. Becker, H. Zabel, W. Müller, and A. Elfeky, “Virtual Prototyping software-intensiver
    mechatronischer Systeme - Eine Fallstudie,” presented at the 8. Paderborner Workshop
    Entwurf Mechatronischer Systeme, 2011.
  mla: Becker, Markus, et al. <i>Virtual Prototyping Software-Intensiver Mechatronischer
    Systeme - Eine Fallstudie</i>. 2011.
  short: 'M. Becker, H. Zabel, W. Müller, A. Elfeky, in: Paderborn, 2011.'
conference:
  name: 8. Paderborner Workshop Entwurf Mechatronischer Systeme
date_created: 2023-01-17T08:56:55Z
date_updated: 2025-03-12T16:39:22Z
language:
- iso: eng
place: Paderborn
status: public
title: Virtual Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie
type: conference
user_id: '5786'
year: '2011'
...
---
_id: '53582'
citation:
  ama: Gerard S, Müller W, Rioux L, Selic B, eds. <i>Proceedings of the 1st Workshop
    on Model Based Engineering for Embedded Systems Design</i>.; 2010.
  apa: Gerard, S., Müller, W., Rioux, L., &#38; Selic, B. (Eds.). (2010). <i>Proceedings
    of the 1st Workshop on Model Based Engineering for Embedded Systems Design</i>.
  bibtex: '@book{Gerard_Müller_Rioux_Selic_2010, place={Dresden, Germany}, title={Proceedings
    of the 1st Workshop on Model Based Engineering for Embedded Systems Design}, year={2010}
    }'
  chicago: Gerard, Sebatian, Wolfgang Müller, L. Rioux, and Brand Selic, eds. <i>Proceedings
    of the 1st Workshop on Model Based Engineering for Embedded Systems Design</i>.
    Dresden, Germany, 2010.
  ieee: S. Gerard, W. Müller, L. Rioux, and B. Selic, Eds., <i>Proceedings of the
    1st Workshop on Model Based Engineering for Embedded Systems Design</i>. Dresden,
    Germany, 2010.
  mla: Gerard, Sebatian, et al., editors. <i>Proceedings of the 1st Workshop on Model
    Based Engineering for Embedded Systems Design</i>. 2010.
  short: S. Gerard, W. Müller, L. Rioux, B. Selic, eds., Proceedings of the 1st Workshop
    on Model Based Engineering for Embedded Systems Design, Dresden, Germany, 2010.
date_created: 2024-04-18T20:43:03Z
date_updated: 2024-04-18T22:15:27Z
department:
- _id: '58'
editor:
- first_name: Sebatian
  full_name: Gerard, Sebatian
  last_name: Gerard
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: L.
  full_name: Rioux, L.
  last_name: Rioux
- first_name: Brand
  full_name: Selic, Brand
  last_name: Selic
language:
- iso: eng
place: Dresden, Germany
status: public
title: Proceedings of the 1st Workshop on Model Based Engineering for Embedded Systems
  Design
type: book_editor
user_id: '16243'
year: '2010'
...
---
_id: '37007'
abstract:
- lang: eng
  text: UML is widely applied for the specification and modeling of software and some
    studies have demonstrated that it is applicable for HW/SW codesign. However, in
    this area there is still a big gap from UML modeling to SystemC-based verification
    and synthesis environments. This paper presents an efficient approach to bridge
    this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework
    for the seamless integration of a customized SysML entry with code generation
    for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the
    SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate
    the applicability of our approach.
author:
- first_name: Fabian
  full_name: Mischkalla, Fabian
  last_name: Mischkalla
- first_name: Da
  full_name: He, Da
  last_name: He
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and
    Simulation of Combined HW/SW Systems. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>'
  apa: Mischkalla, F., He, D., &#38; Müller, W. (2010). Closing the Gap between UML-based
    Modeling and Simulation of Combined HW/SW Systems. <i>Proceedings of DATE’10</i>.
    2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE
    2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456990">https://doi.org/10.1109/DATE.2010.5456990</a>
  bibtex: '@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing
    the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems},
    DOI={<a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian
    and He, Da and Müller, Wolfgang}, year={2010} }'
  chicago: 'Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between
    UML-Based Modeling and Simulation of Combined HW/SW Systems.” In <i>Proceedings
    of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456990">https://doi.org/10.1109/DATE.2010.5456990</a>.'
  ieee: 'F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling
    and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation
    &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi:
    <a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>.'
  mla: Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and
    Simulation of Combined HW/SW Systems.” <i>Proceedings of DATE’10</i>, IEEE, 2010,
    doi:<a href="https://doi.org/10.1109/DATE.2010.5456990">10.1109/DATE.2010.5456990</a>.
  short: 'F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden,
    2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:12:35Z
date_updated: 2023-01-17T09:12:44Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456990
keyword:
- Unified modeling language
- Field programmable gate arrays
- Bridges
- Helium
- Real time systems
- Operating systems
- Documentation
- Application software
- XML
- Space exploration
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW
  Systems
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37009'
abstract:
- lang: eng
  text: Today, mobile and embedded real time systems have to cope with the migration
    and allocation of multiple software tasks running on top of a real time operating
    system (RTOS) residing on one or several processors. For scaling of each task
    set and processor configuration, instruction set simulation and worst case timing
    analysis are typically applied. This paper presents a complementary approach for
    the verification of RTOS properties based on an abstract RTOS-Model in SystemC.
    We apply IEEE P1850 PSL for which we present an approach and first experiences
    for the assertion-based verification of RTOS properties.
author:
- first_name: Marcio F. S.
  full_name: Oliveira, Marcio F. S.
  last_name: Oliveira
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties.
    In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>'
  apa: Oliveira, M. F. S., Zabel, H., &#38; Müller, W. (2010). Assertion-Based Verification
    of RTOS Properties. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38;
    Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457130">https://doi.org/10.1109/DATE.2010.5457130</a>
  bibtex: '@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based
    Verification of RTOS Properties}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio
    F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }'
  chicago: 'Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based
    Verification of RTOS Properties.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE,
    2010. <a href="https://doi.org/10.1109/DATE.2010.5457130">https://doi.org/10.1109/DATE.2010.5457130</a>.'
  ieee: 'M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification
    of RTOS Properties,” presented at the 2010 Design, Automation &#38; Test in Europe
    Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>.'
  mla: Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5457130">10.1109/DATE.2010.5457130</a>.
  short: 'M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE,
    Dresden, 2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:15:10Z
date_updated: 2023-01-17T09:15:18Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457130
keyword:
- Operating systems
- Real time systems
- Timing
- Hardware
- Analytical models
- Embedded software
- Software systems
- Processor scheduling
- Software performance
- Performance analysis
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publisher: IEEE
status: public
title: Assertion-Based Verification of RTOS Properties
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37011'
abstract:
- lang: eng
  text: Safety-critical automotive systems must fulfill hard real-time constraints
    for reliability and safety. This paper presents a case study for the application
    of an AUTOSAR-based language for timing modeling and analysis. We present and
    apply the Timing Augmented Description Language (TADL) and demonstrate a methodology
    for the development of a speed-adaptive steer-by-wire system. We examine the impact
    of TADL and the methodology on the development process and the suitability and
    interoperability of the applied tools with respect to the AUTOSAR-based tool chain
    in the context of our case study.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Christoph
  full_name: Kuznik, Christoph
  last_name: Kuznik
- first_name: Andre
  full_name: Thuy, Andre
  last_name: Thuy
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Klobedanz K, Kuznik C, Thuy A, Müller W. Timing Modeling and Analysis for
    AUTOSAR-Based Software Development - A Case Study. In: <i>Proceedings of DATE’10,
    Dresden</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>'
  apa: Klobedanz, K., Kuznik, C., Thuy, A., &#38; Müller, W. (2010). Timing Modeling
    and Analysis for AUTOSAR-Based Software Development - A Case Study. <i>Proceedings
    of DATE’10, Dresden</i>. 2010 Design, Automation &#38; Test in Europe Conference
    &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457125">https://doi.org/10.1109/DATE.2010.5457125</a>
  bibtex: '@inproceedings{Klobedanz_Kuznik_Thuy_Müller_2010, place={Dresden}, title={Timing
    Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study},
    DOI={<a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>},
    booktitle={Proceedings of DATE’10, Dresden}, publisher={IEEE}, author={Klobedanz,
    Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}, year={2010} }'
  chicago: 'Klobedanz, Kay, Christoph Kuznik, Andre Thuy, and Wolfgang Müller. “Timing
    Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study.”
    In <i>Proceedings of DATE’10, Dresden</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5457125">https://doi.org/10.1109/DATE.2010.5457125</a>.'
  ieee: 'K. Klobedanz, C. Kuznik, A. Thuy, and W. Müller, “Timing Modeling and Analysis
    for AUTOSAR-Based Software Development - A Case Study,” presented at the 2010
    Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010),
    Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>.'
  mla: Klobedanz, Kay, et al. “Timing Modeling and Analysis for AUTOSAR-Based Software
    Development - A Case Study.” <i>Proceedings of DATE’10, Dresden</i>, IEEE, 2010,
    doi:<a href="https://doi.org/10.1109/DATE.2010.5457125">10.1109/DATE.2010.5457125</a>.
  short: 'K. Klobedanz, C. Kuznik, A. Thuy, W. Müller, in: Proceedings of DATE’10,
    Dresden, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T09:19:36Z
date_updated: 2023-01-17T09:19:46Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457125
keyword:
- Timing
- Programming
- Automotive engineering
- Application software
- Hardware
- Computer architecture
- Communication system software
- Software architecture
- Delay
- Software standards
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10, Dresden
publisher: IEEE
status: public
title: Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case
  Study
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37037'
abstract:
- lang: eng
  text: Today we can identify a big gap between requirement specification and the
    generation of test environments. This article extends the Classification Tree
    Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the
    precise specification of stimuli for operational ranges of continuous control
    systems. It introduces novel means for continuous acceptance criteria definition
    and for functional coverage definition.
author:
- first_name: Alexander
  full_name: Krupp, Alexander
  last_name: Krupp
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Krupp A, Müller W. A Systematic Approach to Combined HW/SW System Test. In:
    <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>'
  apa: Krupp, A., &#38; Müller, W. (2010). A Systematic Approach to Combined HW/SW
    System Test. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe
    Conference &#38; Exhibition (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5457186">https://doi.org/10.1109/DATE.2010.5457186</a>
  bibtex: '@inproceedings{Krupp_Müller_2010, place={Dresden}, title={A Systematic
    Approach to Combined HW/SW System Test}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Krupp, Alexander
    and Müller, Wolfgang}, year={2010} }'
  chicago: 'Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined
    HW/SW System Test.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a
    href="https://doi.org/10.1109/DATE.2010.5457186">https://doi.org/10.1109/DATE.2010.5457186</a>.'
  ieee: 'A. Krupp and W. Müller, “A Systematic Approach to Combined HW/SW System Test,”
    presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden, 2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>.'
  mla: Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined HW/SW
    System Test.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5457186">10.1109/DATE.2010.5457186</a>.
  short: 'A. Krupp, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:41:15Z
date_updated: 2023-01-17T10:41:25Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5457186
keyword:
- System testing
- Automatic testing
- Object oriented modeling
- Classification tree analysis
- Automotive engineering
- Mathematical model
- Embedded system
- Control systems
- Electronic equipment testing
- Software testing
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publisher: IEEE
status: public
title: A Systematic Approach to Combined HW/SW System Test
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37040'
abstract:
- lang: eng
  text: Refinement of untimed TLM models into a timed HW/SW platform is a step by
    step design process which is a trade-off between timing accuracy of the used models
    and correct estimation of the final timing performance. The use of an RTOS on
    the target platform is mandatory in the case real-time properties must be guaranteed.
    Thus, the question is when the RTOS must be introduced in this step by step refinement
    process. This paper proposes a four-level RTOS-aware refinement methodology that,
    starting from an untimed TLM SystemC description of the whole system, progressively
    introduce HW/SW partitioning, timing, device driver and RTOS functionalities,
    till to obtain an accurate model of the final platform, where SW tasks run upon
    an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions.
    Each refinement level allows the designer to estimate more and more accurate timing
    properties, thus anticipating design decisions without being constrained to leave
    timing analysis to the final step of the refinement. The effectiveness of the
    methodology has been evaluated in the design of two complex platforms.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Giuseppe
  full_name: Di Guglielmo, Giuseppe
  last_name: Di Guglielmo
- first_name: Franco
  full_name: Fummi, Franco
  last_name: Fummi
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Graziano
  full_name: Pravadelli, Graziano
  last_name: Pravadelli
- first_name: Tao
  full_name: Xie, Tao
  last_name: Xie
citation:
  ama: 'Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware
    Refinement for TLM2.0-based HW/SW Design. In: <i>Proceedings of DATE’10</i>. IEEE;
    2010. doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>'
  apa: Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., &#38;
    Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. <i>Proceedings
    of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition
    (DATE 2010), Dresden. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>
  bibtex: '@inproceedings{Becker_Di Guglielmo_Fummi_Müller_Pravadelli_Xie_2010, place={Dresden},
    title={RTOS-Aware Refinement for TLM2.0-based HW/SW Design}, DOI={<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>},
    booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Becker, Markus and
    Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli,
    Graziano and Xie, Tao}, year={2010} }'
  chicago: 'Becker, Markus, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller,
    Graziano Pravadelli, and Tao Xie. “RTOS-Aware Refinement for TLM2.0-Based HW/SW
    Design.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href="https://doi.org/10.1109/DATE.2010.5456965">https://doi.org/10.1109/DATE.2010.5456965</a>.'
  ieee: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie,
    “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design,
    Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden,
    2010, doi: <a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.'
  mla: Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.”
    <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href="https://doi.org/10.1109/DATE.2010.5456965">10.1109/DATE.2010.5456965</a>.
  short: 'M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, T. Xie,
    in: Proceedings of DATE’10, IEEE, Dresden, 2010.'
conference:
  location: Dresden
  name: Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
date_created: 2023-01-17T10:47:29Z
date_updated: 2023-01-17T10:47:37Z
department:
- _id: '672'
doi: 10.1109/DATE.2010.5456965
keyword:
- Timing
- Hardware
- Operating systems
- Process design
- Accuracy
- Standards development
- Context modeling
- Real time systems
- Communication channels
- Microprogramming
language:
- iso: eng
place: Dresden
publication: Proceedings of DATE’10
publication_identifier:
  eisbn:
  - 978-3-9810801-6-2
publisher: IEEE
status: public
title: RTOS-Aware Refinement for TLM2.0-based HW/SW Design
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37046'
abstract:
- lang: eng
  text: In this article, we present a flexible simulation environment for embedded
    real-time software refinement by a mixed level cosimulation. For this, we combine
    the native speed of an abstract real-time operating system (RTOS) model in SystemC
    with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU.
    In order to support stepwise RTOS software refinement from system level to the
    target software, each task can be separately migrated between the native execution
    and the ISS. By adapting the dynamic binary translation approach to an efficient
    but yet very accurate synchronization scheme the overhead of QEMU user mode execution
    is only factor two compared to native SystemC. Furthermore, the simulation speed
    increases almost linearly according to the utilization of the task set abstracted
    by the native execution. Hereby, the simulation time can be considerably reduced
    by cosimulating just a subset of tasks on QEMU.
author:
- first_name: Markus
  full_name: Becker, Markus
  last_name: Becker
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Becker M, Zabel H, Müller W. A Mixed Level Simulation Environment for Stepwise
    RTOS Software Refinement. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag;
    2010. doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>'
  apa: Becker, M., Zabel, H., &#38; Müller, W. (2010). <i>A Mixed Level Simulation
    Environment for Stepwise RTOS Software Refinement</i> (L. Kleinjohann &#38; B.
    Kleinjohann, Eds.). Springer Verlag. <a href="https://doi.org/10.1007/978-3-642-15234-4_15">https://doi.org/10.1007/978-3-642-15234-4_15</a>
  bibtex: '@inproceedings{Becker_Zabel_Müller_2010, place={Dordrecht}, title={A Mixed
    Level Simulation Environment for Stepwise RTOS Software Refinement}, DOI={<a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>},
    publisher={Springer Verlag}, author={Becker, Markus and Zabel, Henning and Müller,
    Wolfgang}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }'
  chicago: 'Becker, Markus, Henning Zabel, and Wolfgang Müller. “A Mixed Level Simulation
    Environment for Stepwise RTOS Software Refinement.” edited by L. Kleinjohann and
    B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href="https://doi.org/10.1007/978-3-642-15234-4_15">https://doi.org/10.1007/978-3-642-15234-4_15</a>.'
  ieee: 'M. Becker, H. Zabel, and W. Müller, “A Mixed Level Simulation Environment
    for Stepwise RTOS Software Refinement,” 2010, doi: <a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>.'
  mla: Becker, Markus, et al. <i>A Mixed Level Simulation Environment for Stepwise
    RTOS Software Refinement</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer
    Verlag, 2010, doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_15">10.1007/978-3-642-15234-4_15</a>.
  short: 'M. Becker, H. Zabel, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.),
    Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T11:01:30Z
date_updated: 2023-01-17T11:03:00Z
department:
- _id: '672'
doi: 10.1007/978-3-642-15234-4_15
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
keyword:
- Application Programming Interface     User Mode     Kernel Space     System Level
  Design     Mixed Level
language:
- iso: eng
place: Dordrecht
publication_identifier:
  isbn:
  - 978-3-642-15233-7
publisher: Springer Verlag
status: public
title: A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37044'
abstract:
- lang: eng
  text: In this paper we present new concepts to resolve ECU (Electronic Control Unit)
    failures in FlexRay networks. Our approach extends the FlexRay bus schedule by
    redundant slots with modifications in the communication and slot assignment. We
    introduce additional backup nodes to replace faulty nodes. To reduce the required
    memory resources of the backup nodes, we distribute redundant tasks over different
    nodes and propose the migration of tasks to the backup node at runtime. We investigate
    different solutions to migrate the redundant tasks to the backup node by time-triggered
    and event-triggered transmissions.
author:
- first_name: Kay
  full_name: Klobedanz, Kay
  last_name: Klobedanz
- first_name: Gilles B.
  full_name: Defo, Gilles B.
  last_name: Defo
- first_name: Henning
  full_name: Zabel, Henning
  last_name: Zabel
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Yuan
  full_name: Zhi, Yuan
  last_name: Zhi
citation:
  ama: 'Klobedanz K, Defo GB, Zabel H, Müller W, Zhi Y. Task Migration for Fault-Tolerant
    FlexRay Networks. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010.
    doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>'
  apa: Klobedanz, K., Defo, G. B., Zabel, H., Müller, W., &#38; Zhi, Y. (2010). <i>Task
    Migration for Fault-Tolerant FlexRay Networks</i> (L. Kleinjohann &#38; B. Kleinjohann,
    Eds.). Springer Verlag. <a href="https://doi.org/10.1007/978-3-642-15234-4_7">https://doi.org/10.1007/978-3-642-15234-4_7</a>
  bibtex: '@inproceedings{Klobedanz_Defo_Zabel_Müller_Zhi_2010, place={Dordrecht},
    title={Task Migration for Fault-Tolerant FlexRay Networks}, DOI={<a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>},
    publisher={Springer Verlag}, author={Klobedanz, Kay and Defo, Gilles B. and Zabel,
    Henning and Müller, Wolfgang and Zhi, Yuan}, editor={Kleinjohann, L. and Kleinjohann,
    B.}, year={2010} }'
  chicago: 'Klobedanz, Kay, Gilles B. Defo, Henning Zabel, Wolfgang Müller, and Yuan
    Zhi. “Task Migration for Fault-Tolerant FlexRay Networks.” edited by L. Kleinjohann
    and B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href="https://doi.org/10.1007/978-3-642-15234-4_7">https://doi.org/10.1007/978-3-642-15234-4_7</a>.'
  ieee: 'K. Klobedanz, G. B. Defo, H. Zabel, W. Müller, and Y. Zhi, “Task Migration
    for Fault-Tolerant FlexRay Networks,” 2010, doi: <a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>.'
  mla: Klobedanz, Kay, et al. <i>Task Migration for Fault-Tolerant FlexRay Networks</i>.
    Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href="https://doi.org/10.1007/978-3-642-15234-4_7">10.1007/978-3-642-15234-4_7</a>.
  short: 'K. Klobedanz, G.B. Defo, H. Zabel, W. Müller, Y. Zhi, in: L. Kleinjohann,
    B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.'
conference:
  name: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES
    2010)
date_created: 2023-01-17T10:59:52Z
date_updated: 2023-01-17T11:00:00Z
department:
- _id: '672'
doi: 10.1007/978-3-642-15234-4_7
editor:
- first_name: L.
  full_name: Kleinjohann, L.
  last_name: Kleinjohann
- first_name: B.
  full_name: Kleinjohann, B.
  last_name: Kleinjohann
keyword:
- Faulty Node     Static Segment     Slot Assignment     Task Migration     Communication
  Controller
language:
- iso: eng
place: Dordrecht
publication_identifier:
  isbn:
  - 978-3-642-15233-7
publisher: Springer Verlag
status: public
title: Task Migration for Fault-Tolerant FlexRay Networks
type: conference
user_id: '5786'
year: '2010'
...