@inproceedings{52744,
  author       = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  booktitle    = {{European Test Symposium, The Hague, Netherlands, May 20-24, 2024}},
  location     = {{The Hague, NL}},
  pages        = {{6}},
  publisher    = {{IEEE}},
  title        = {{{Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations}}},
  year         = {{2024}},
}

@inproceedings{52742,
  author       = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  booktitle    = {{IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}},
  location     = {{Maceió}},
  pages        = {{6}},
  publisher    = {{IEEE}},
  title        = {{{Vmin Testing under Variations: Defect vs. Fault Coverage}}},
  year         = {{2024}},
}

@inproceedings{52743,
  author       = {{Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}},
  booktitle    = {{International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024}},
  location     = {{Xi'an, China}},
  pages        = {{1}},
  title        = {{{Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}}},
  year         = {{2024}},
}

@inproceedings{52745,
  author       = {{Wunderlich, Hans-Joachim and Jafarzadeh, Hanieh and Hellebrand, Sybille}},
  booktitle    = {{International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}},
  location     = {{Xi’an, China}},
  pages        = {{1}},
  title        = {{{Robust Test of Small Delay Faults under  PVT-Variations}}},
  year         = {{2024}},
}

@misc{50284,
  author       = {{Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}},
  publisher    = {{37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"  (TuZ'24), Feb. 2024}},
  title        = {{{Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}}},
  year         = {{2024}},
}

@misc{51799,
  author       = {{Ustimova, Magdalina  and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}},
  publisher    = {{37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"  (TuZ'24), Feb. 2024}},
  title        = {{{Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks}}},
  year         = {{2024}},
}

@inproceedings{56014,
  author       = {{Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and  Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  booktitle    = {{In: IEEE International Test Conference (ITC'24), San Diego, CA, USA, November 2024}},
  location     = {{San Diego, CA, USA}},
  publisher    = {{IEEE}},
  title        = {{{Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing}}},
  year         = {{2024}},
}

@inproceedings{46738,
  author       = {{Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  booktitle    = {{IEEE Asian Test Symposium (ATS'23), October 2023}},
  title        = {{{Optimizing the Streaming of Sensor Data with Approximate Communication}}},
  year         = {{2023}},
}

@article{46264,
  abstract     = {{System-level interconnects provide the
backbone for increasingly complex systems on a chip. Their
vulnerability to electromigration and crosstalk can lead to
serious reliability and safety issues during the system lifetime.
This article presents an approach for periodic in-system testing
which maintains a reliability profile to detect potential
problems before they actually cause a failure. Relying on a
common infrastructure for EM-aware system workload
management and test, it minimizes the stress induced by the
test itself and contributes to the self-healing of system-induced
electromigration degradations. }},
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  issn         = {{2168-2356}},
  journal      = {{IEEE Design &Test}},
  keywords     = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}},
  pages        = {{1--1}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Workload-Aware Periodic Interconnect BIST}}},
  doi          = {{10.1109/mdat.2023.3298849}},
  year         = {{2023}},
}

@inproceedings{45830,
  author       = {{Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and  Amrouch, Hussam and Hellebrand, Sybille and  Wunderlich, Hans-Joachim}},
  booktitle    = {{IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023}},
  location     = {{Anaheim, USA}},
  publisher    = {{IEEE}},
  title        = {{{Robust Pattern Generation for Small Delay Faults under Process Variations}}},
  year         = {{2023}},
}

@misc{35204,
  author       = {{Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}},
  keywords     = {{WORKSHOP}},
  pages        = {{2}},
  publisher    = {{35. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'23), Feb. 2023}},
  title        = {{{On Cryptography Effects on Interconnect Reliability}}},
  year         = {{2023}},
}

@inproceedings{41875,
  author       = {{Badran, Abdalrhman  and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}},
  booktitle    = {{28th IEEE European Test Symposium (ETS'23), May 2023}},
  title        = {{{Approximate Computing: Balancing Performance, Power, Reliability, and Safety}}},
  year         = {{2023}},
}

@inproceedings{46739,
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  booktitle    = {{2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}},
  publisher    = {{IEEE}},
  title        = {{{Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}}},
  doi          = {{10.1109/dsn-w58399.2023.00056}},
  year         = {{2023}},
}

@article{29351,
  abstract     = {{Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.}},
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  issn         = {{0923-8174}},
  journal      = {{Journal of Electronic Testing}},
  keywords     = {{Electrical and Electronic Engineering}},
  publisher    = {{Springer Science and Business Media LLC}},
  title        = {{{Stress-Aware Periodic Test of Interconnects}}},
  doi          = {{10.1007/s10836-021-05979-5}},
  year         = {{2022}},
}

@misc{29890,
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}},
  keywords     = {{WORKSHOP}},
  pages        = {{2}},
  publisher    = {{European Workshop on Silicon Lifecycle Management, March 18, 2022}},
  title        = {{{EM-Aware Interconnect BIST}}},
  year         = {{2022}},
}

@inproceedings{19422,
  author       = {{Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}},
  booktitle    = {{IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}},
  title        = {{{Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}}},
  year         = {{2020}},
}

@misc{15419,
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}},
  keywords     = {{WORKSHOP}},
  pages        = {{4}},
  publisher    = {{32. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'20), 16. - 18. Februar 2020}},
  title        = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}},
  year         = {{2020}},
}

@inproceedings{29200,
  author       = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}},
  booktitle    = {{38th IEEE VLSI Test Symposium (VTS)}},
  publisher    = {{IEEE}},
  title        = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}},
  doi          = {{10.1109/vts48691.2020.9107591}},
  year         = {{2020}},
}

@inproceedings{19421,
  author       = {{Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}},
  booktitle    = {{IEEE International Test Conference (ITC'20), November 2020}},
  title        = {{{Logic Fault Diagnosis of Hidden Delay Defects}}},
  year         = {{2020}},
}

@misc{8112,
  author       = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}},
  keywords     = {{WORKSHOP}},
  publisher    = {{31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'19)}},
  title        = {{{A Hybrid Space Compactor for Varying X-Rates}}},
  year         = {{2019}},
}