[{"extern":"1","language":[{"iso":"eng"}],"_id":"13010","department":[{"_id":"48"}],"user_id":"209","status":"public","publication":"IEEE International Test Conference (ITC'96)","type":"conference","title":"Mixed-Mode BIST Using Embedded Processors","doi":"10.1109/test.1996.556962","publisher":"IEEE","date_updated":"2022-05-11T16:54:33Z","date_created":"2019-08-28T10:25:42Z","author":[{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"},{"full_name":"Hertwig, Andre","last_name":"Hertwig","first_name":"Andre"}],"place":"Washington, DC, USA","year":"1996","page":"195-204","citation":{"apa":"Hellebrand, S., Wunderlich, H.-J., &#38; Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. <i>IEEE International Test Conference (ITC’96)</i>, 195–204. <a href=\"https://doi.org/10.1109/test.1996.556962\">https://doi.org/10.1109/test.1996.556962</a>","bibtex":"@inproceedings{Hellebrand_Wunderlich_Hertwig_1996, place={Washington, DC, USA}, title={Mixed-Mode BIST Using Embedded Processors}, DOI={<a href=\"https://doi.org/10.1109/test.1996.556962\">10.1109/test.1996.556962</a>}, booktitle={IEEE International Test Conference (ITC’96)}, publisher={IEEE}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim and Hertwig, Andre}, year={1996}, pages={195–204} }","short":"S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: IEEE International Test Conference (ITC’96), IEEE, Washington, DC, USA, 1996, pp. 195–204.","mla":"Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” <i>IEEE International Test Conference (ITC’96)</i>, IEEE, 1996, pp. 195–204, doi:<a href=\"https://doi.org/10.1109/test.1996.556962\">10.1109/test.1996.556962</a>.","ieee":"S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in <i>IEEE International Test Conference (ITC’96)</i>, 1996, pp. 195–204, doi: <a href=\"https://doi.org/10.1109/test.1996.556962\">10.1109/test.1996.556962</a>.","chicago":"Hellebrand, Sybille, Hans-Joachim Wunderlich, and Andre Hertwig. “Mixed-Mode BIST Using Embedded Processors.” In <i>IEEE International Test Conference (ITC’96)</i>, 195–204. Washington, DC, USA: IEEE, 1996. <a href=\"https://doi.org/10.1109/test.1996.556962\">https://doi.org/10.1109/test.1996.556962</a>.","ama":"Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: <i>IEEE International Test Conference (ITC’96)</i>. IEEE; 1996:195-204. doi:<a href=\"https://doi.org/10.1109/test.1996.556962\">10.1109/test.1996.556962</a>"}},{"year":"1995","place":"University of Siegen, Germany","citation":{"chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. <i>Synthesis Procedures for Self-Testable Controllers</i>. University of Siegen, Germany, 1995.","ieee":"S. Hellebrand and H.-J. Wunderlich, <i>Synthesis Procedures for Self-Testable Controllers</i>. University of Siegen, Germany, 1995.","ama":"Hellebrand S, Wunderlich H-J. <i>Synthesis Procedures for Self-Testable Controllers</i>. University of Siegen, Germany; 1995.","bibtex":"@book{Hellebrand_Wunderlich_1995, place={University of Siegen, Germany}, title={Synthesis Procedures for Self-Testable Controllers}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={1995} }","mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. <i>Synthesis Procedures for Self-Testable Controllers</i>. 1995.","short":"S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.","apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (1995). <i>Synthesis Procedures for Self-Testable Controllers</i>. University of Siegen, Germany."},"title":"Synthesis Procedures for Self-Testable Controllers","date_updated":"2022-01-06T06:51:27Z","author":[{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T10:32:24Z","status":"public","type":"report","extern":"1","language":[{"iso":"eng"}],"_id":"13026","department":[{"_id":"48"}],"user_id":"659"},{"language":[{"iso":"eng"}],"extern":"1","_id":"13027","department":[{"_id":"48"}],"user_id":"659","status":"public","type":"report","title":"Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis","date_updated":"2022-01-06T06:51:27Z","date_created":"2019-08-28T10:32:25Z","author":[{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"},{"first_name":"F.","full_name":"Goncalves, F.","last_name":"Goncalves"},{"first_name":"Joao","full_name":"Paulo Teixeira, Joao","last_name":"Paulo Teixeira"}],"year":"1995","place":"University Siegen, Germany","citation":{"ama":"Hellebrand S, Wunderlich H-J, Goncalves F, Paulo Teixeira J. <i>Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis</i>. University Siegen, Germany; 1995.","ieee":"S. Hellebrand, H.-J. Wunderlich, F. Goncalves, and J. Paulo Teixeira, <i>Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis</i>. University Siegen, Germany, 1995.","chicago":"Hellebrand, Sybille, Hans-Joachim Wunderlich, F. Goncalves, and Joao Paulo Teixeira. <i>Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis</i>. University Siegen, Germany, 1995.","mla":"Hellebrand, Sybille, et al. <i>Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis</i>. 1995.","short":"S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.","bibtex":"@book{Hellebrand_Wunderlich_Goncalves_Paulo Teixeira_1995, place={University Siegen, Germany}, title={Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim and Goncalves, F. and Paulo Teixeira, Joao}, year={1995} }","apa":"Hellebrand, S., Wunderlich, H.-J., Goncalves, F., &#38; Paulo Teixeira, J. (1995). <i>Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis</i>. University Siegen, Germany."}},{"citation":{"ama":"Hellebrand S, Herzog M, Wunderlich H-J. <i>Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing</i>. University of Siegen, Germany; 1995.","ieee":"S. Hellebrand, M. Herzog, and H.-J. Wunderlich, <i>Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing</i>. University of Siegen, Germany, 1995.","chicago":"Hellebrand, Sybille, Maik Herzog, and Hans-Joachim Wunderlich. <i>Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing</i>. University of Siegen, Germany, 1995.","short":"S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.","bibtex":"@book{Hellebrand_Herzog_Wunderlich_1995, place={University of Siegen, Germany}, title={Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing}, author={Hellebrand, Sybille and Herzog, Maik and Wunderlich, Hans-Joachim}, year={1995} }","mla":"Hellebrand, Sybille, et al. <i>Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing</i>. 1995.","apa":"Hellebrand, S., Herzog, M., &#38; Wunderlich, H.-J. (1995). <i>Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing</i>. University of Siegen, Germany."},"year":"1995","place":"University of Siegen, Germany","author":[{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"first_name":"Maik","last_name":"Herzog","full_name":"Herzog, Maik"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T10:32:26Z","date_updated":"2022-01-06T06:51:27Z","title":"Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing","type":"report","status":"public","department":[{"_id":"48"}],"user_id":"659","_id":"13028","extern":"1","language":[{"iso":"eng"}]},{"keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"extern":"1","_id":"13086","department":[{"_id":"48"}],"user_id":"659","status":"public","type":"misc","title":"Pattern Generation for a Deterministic BIST Scheme","date_updated":"2022-01-06T06:51:28Z","author":[{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"full_name":"Reeb, Birgit","last_name":"Reeb","first_name":"Birgit"},{"first_name":"Steffen","last_name":"Tarnick","full_name":"Tarnick, Steffen"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2019-08-28T12:13:37Z","place":"2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA","year":"1995","citation":{"mla":"Hellebrand, Sybille, et al. <i>Pattern Generation for a Deterministic BIST Scheme</i>. 1995.","short":"S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.","bibtex":"@book{Hellebrand_Reeb_Tarnick_Wunderlich_1995, place={2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA}, title={Pattern Generation for a Deterministic BIST Scheme}, author={Hellebrand, Sybille and Reeb, Birgit and Tarnick, Steffen and Wunderlich, Hans-Joachim}, year={1995} }","apa":"Hellebrand, S., Reeb, B., Tarnick, S., &#38; Wunderlich, H.-J. (1995). <i>Pattern Generation for a Deterministic BIST Scheme</i>. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA.","ieee":"S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, <i>Pattern Generation for a Deterministic BIST Scheme</i>. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.","chicago":"Hellebrand, Sybille, Birgit Reeb, Steffen Tarnick, and Hans-Joachim Wunderlich. <i>Pattern Generation for a Deterministic BIST Scheme</i>. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.","ama":"Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. <i>Pattern Generation for a Deterministic BIST Scheme</i>. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1995."}},{"status":"public","type":"journal_article","publication":"IEEE Transactions on Computers","language":[{"iso":"eng"}],"extern":"1","user_id":"209","department":[{"_id":"48"}],"_id":"13011","citation":{"ieee":"S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” <i>IEEE Transactions on Computers</i>, vol. 44, no. 2, pp. 223–233, 1995, doi: <a href=\"https://doi.org/10.1109/12.364534\">10.1109/12.364534</a>.","chicago":"Hellebrand, Sybille, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, and B. Courtois. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” <i>IEEE Transactions on Computers</i> 44, no. 2 (1995): 223–33. <a href=\"https://doi.org/10.1109/12.364534\">https://doi.org/10.1109/12.364534</a>.","ama":"Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. <i>IEEE Transactions on Computers</i>. 1995;44(2):223-233. doi:<a href=\"https://doi.org/10.1109/12.364534\">10.1109/12.364534</a>","short":"S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, IEEE Transactions on Computers 44 (1995) 223–233.","bibtex":"@article{Hellebrand_Rajski_Tarnick_Venkataraman_Courtois_1995, title={Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers}, volume={44}, DOI={<a href=\"https://doi.org/10.1109/12.364534\">10.1109/12.364534</a>}, number={2}, journal={IEEE Transactions on Computers}, publisher={IEEE}, author={Hellebrand, Sybille and Rajski, Janusz and Tarnick, Steffen and Venkataraman, Srikanth and Courtois, B.}, year={1995}, pages={223–233} }","mla":"Hellebrand, Sybille, et al. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” <i>IEEE Transactions on Computers</i>, vol. 44, no. 2, IEEE, 1995, pp. 223–33, doi:<a href=\"https://doi.org/10.1109/12.364534\">10.1109/12.364534</a>.","apa":"Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., &#38; Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. <i>IEEE Transactions on Computers</i>, <i>44</i>(2), 223–233. <a href=\"https://doi.org/10.1109/12.364534\">https://doi.org/10.1109/12.364534</a>"},"page":"223-233","intvolume":"        44","year":"1995","issue":"2","doi":"10.1109/12.364534","title":"Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers","date_created":"2019-08-28T10:26:37Z","author":[{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Janusz","last_name":"Rajski","full_name":"Rajski, Janusz"},{"first_name":"Steffen","full_name":"Tarnick, Steffen","last_name":"Tarnick"},{"first_name":"Srikanth","full_name":"Venkataraman, Srikanth","last_name":"Venkataraman"},{"last_name":"Courtois","full_name":"Courtois, B.","first_name":"B."}],"volume":44,"publisher":"IEEE","date_updated":"2022-05-11T16:55:15Z"},{"department":[{"_id":"48"}],"user_id":"209","_id":"13012","language":[{"iso":"eng"}],"extern":"1","publication":"ACM/IEEE International Conference on Computer Aided Design (ICCAD'95)","type":"conference","status":"public","date_created":"2019-08-28T10:26:38Z","author":[{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"full_name":"Reeb, Birgit","last_name":"Reeb","first_name":"Birgit"},{"first_name":"Steffen","last_name":"Tarnick","full_name":"Tarnick, Steffen"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_updated":"2022-05-11T16:55:51Z","publisher":"IEEE","doi":"10.1109/iccad.1995.479997","title":"Pattern Generation for a Deterministic BIST Scheme","page":"88-94","citation":{"short":"S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, San Jose, CA, USA, 1995, pp. 88–94.","bibtex":"@inproceedings{Hellebrand_Reeb_Tarnick_Wunderlich_1995, place={San Jose, CA, USA}, title={Pattern Generation for a Deterministic BIST Scheme}, DOI={<a href=\"https://doi.org/10.1109/iccad.1995.479997\">10.1109/iccad.1995.479997</a>}, booktitle={ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)}, publisher={IEEE}, author={Hellebrand, Sybille and Reeb, Birgit and Tarnick, Steffen and Wunderlich, Hans-Joachim}, year={1995}, pages={88–94} }","mla":"Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.” <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)</i>, IEEE, 1995, pp. 88–94, doi:<a href=\"https://doi.org/10.1109/iccad.1995.479997\">10.1109/iccad.1995.479997</a>.","apa":"Hellebrand, S., Reeb, B., Tarnick, S., &#38; Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)</i>, 88–94. <a href=\"https://doi.org/10.1109/iccad.1995.479997\">https://doi.org/10.1109/iccad.1995.479997</a>","chicago":"Hellebrand, Sybille, Birgit Reeb, Steffen Tarnick, and Hans-Joachim Wunderlich. “Pattern Generation for a Deterministic BIST Scheme.” In <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)</i>, 88–94. San Jose, CA, USA: IEEE, 1995. <a href=\"https://doi.org/10.1109/iccad.1995.479997\">https://doi.org/10.1109/iccad.1995.479997</a>.","ieee":"S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,” in <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)</i>, 1995, pp. 88–94, doi: <a href=\"https://doi.org/10.1109/iccad.1995.479997\">10.1109/iccad.1995.479997</a>.","ama":"Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)</i>. IEEE; 1995:88-94. doi:<a href=\"https://doi.org/10.1109/iccad.1995.479997\">10.1109/iccad.1995.479997</a>"},"place":"San Jose, CA, USA","year":"1995"},{"type":"report","status":"public","department":[{"_id":"48"}],"user_id":"659","_id":"13024","language":[{"iso":"eng"}],"extern":"1","citation":{"chicago":"Hellebrand, Sybille, Arne Juergensen, and Hans-Joachim Wunderlich. <i>Synthesis for Off-Line Testability</i>. University of Siegen, Germany, 1994.","ieee":"S. Hellebrand, A. Juergensen, and H.-J. Wunderlich, <i>Synthesis for Off-line Testability</i>. University of Siegen, Germany, 1994.","ama":"Hellebrand S, Juergensen A, Wunderlich H-J. <i>Synthesis for Off-Line Testability</i>. University of Siegen, Germany; 1994.","apa":"Hellebrand, S., Juergensen, A., &#38; Wunderlich, H.-J. (1994). <i>Synthesis for Off-line Testability</i>. University of Siegen, Germany.","mla":"Hellebrand, Sybille, et al. <i>Synthesis for Off-Line Testability</i>. 1994.","bibtex":"@book{Hellebrand_Juergensen_Wunderlich_1994, place={University of Siegen, Germany}, title={Synthesis for Off-line Testability}, author={Hellebrand, Sybille and Juergensen, Arne and Wunderlich, Hans-Joachim}, year={1994} }","short":"S. Hellebrand, A. Juergensen, H.-J. Wunderlich, Synthesis for Off-Line Testability, University of Siegen, Germany, 1994."},"place":"University of Siegen, Germany","year":"1994","author":[{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"},{"first_name":"Arne","full_name":"Juergensen, Arne","last_name":"Juergensen"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T10:31:16Z","date_updated":"2022-01-06T06:51:27Z","title":"Synthesis for Off-line Testability"},{"language":[{"iso":"eng"}],"extern":"1","department":[{"_id":"48"}],"user_id":"659","_id":"13025","status":"public","type":"report","title":"Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time","date_created":"2019-08-28T10:31:17Z","author":[{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"full_name":"Juergensen, Arne","last_name":"Juergensen","first_name":"Arne"},{"full_name":"Stroele, Albrecht","last_name":"Stroele","first_name":"Albrecht"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_updated":"2022-01-06T06:51:27Z","citation":{"chicago":"Hellebrand, Sybille, Arne Juergensen, Albrecht Stroele, and Hans-Joachim Wunderlich. <i>Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time</i>. University of Siegen, Germany, 1994.","ieee":"S. Hellebrand, A. Juergensen, A. Stroele, and H.-J. Wunderlich, <i>Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time</i>. University of Siegen, Germany, 1994.","ama":"Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. <i>Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time</i>. University of Siegen, Germany; 1994.","bibtex":"@book{Hellebrand_Juergensen_Stroele_Wunderlich_1994, place={University of Siegen, Germany}, title={Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time}, author={Hellebrand, Sybille and Juergensen, Arne and Stroele, Albrecht and Wunderlich, Hans-Joachim}, year={1994} }","mla":"Hellebrand, Sybille, et al. <i>Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time</i>. 1994.","short":"S. Hellebrand, A. Juergensen, A. Stroele, H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time, University of Siegen, Germany, 1994.","apa":"Hellebrand, S., Juergensen, A., Stroele, A., &#38; Wunderlich, H.-J. (1994). <i>Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time</i>. University of Siegen, Germany."},"place":"University of Siegen, Germany","year":"1994"},{"date_created":"2019-08-28T12:11:20Z","author":[{"full_name":"Venkataraman, Srikanth","last_name":"Venkataraman","first_name":"Srikanth"},{"full_name":"Rajski, Janusz","last_name":"Rajski","first_name":"Janusz"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"full_name":"Tarnick, Steffen","last_name":"Tarnick","first_name":"Steffen"}],"date_updated":"2022-01-06T06:51:28Z","title":"Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen","citation":{"ama":"Venkataraman S, Rajski J, Hellebrand S, Tarnick S. <i>Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.","ieee":"S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, <i>Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.","chicago":"Venkataraman, Srikanth, Janusz Rajski, Sybille Hellebrand, and Steffen Tarnick. <i>Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.","apa":"Venkataraman, S., Rajski, J., Hellebrand, S., &#38; Tarnick, S. (1994). <i>Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.","short":"S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.","bibtex":"@book{Venkataraman_Rajski_Hellebrand_Tarnick_1994, place={6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands}, title={Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen}, author={Venkataraman, Srikanth and Rajski, Janusz and Hellebrand, Sybille and Tarnick, Steffen}, year={1994} }","mla":"Venkataraman, Srikanth, et al. <i>Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen</i>. 1994."},"year":"1994","place":"6th ITG/GI/GME Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Vaals, The Netherlands","user_id":"659","department":[{"_id":"48"}],"_id":"13083","language":[{"iso":"eng"}],"extern":"1","keyword":["WORKSHOP"],"type":"misc","status":"public"},{"citation":{"ama":"Hellebrand S, Wunderlich H-J. <i>Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.","chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. <i>Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.","ieee":"S. Hellebrand and H.-J. Wunderlich, <i>Ein Verfahren zur testfreundlichen Steuerwerkssynthese</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.","short":"S. Hellebrand, H.-J. Wunderlich, Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.","mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. <i>Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese</i>. 1994.","bibtex":"@book{Hellebrand_Wunderlich_1994, place={6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands}, title={Ein Verfahren zur testfreundlichen Steuerwerkssynthese}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={1994} }","apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (1994). <i>Ein Verfahren zur testfreundlichen Steuerwerkssynthese</i>. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands."},"year":"1994","place":"6th ITG/GI/GME Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Vaals, The Netherlands","title":"Ein Verfahren zur testfreundlichen Steuerwerkssynthese","date_created":"2019-08-28T12:11:57Z","author":[{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_updated":"2022-01-06T06:51:28Z","status":"public","type":"misc","language":[{"iso":"eng"}],"extern":"1","keyword":["WORKSHOP"],"department":[{"_id":"48"}],"user_id":"659","_id":"13084"},{"title":"Synthesis for Testability - the ARCHIMEDES Approach","author":[{"full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"},{"first_name":"Joao","full_name":"Paulo Teixeira, Joao","last_name":"Paulo Teixeira"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T12:13:01Z","date_updated":"2022-01-06T06:51:28Z","citation":{"mla":"Hellebrand, Sybille, et al. <i>Synthesis for Testability - the ARCHIMEDES Approach</i>. 1994.","short":"S. Hellebrand, J. Paulo Teixeira, H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach, 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.","bibtex":"@book{Hellebrand_Paulo Teixeira_Wunderlich_1994, place={1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA}, title={Synthesis for Testability - the ARCHIMEDES Approach}, author={Hellebrand, Sybille and Paulo Teixeira, Joao and Wunderlich, Hans-Joachim}, year={1994} }","apa":"Hellebrand, S., Paulo Teixeira, J., &#38; Wunderlich, H.-J. (1994). <i>Synthesis for Testability - the ARCHIMEDES Approach</i>. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.","chicago":"Hellebrand, Sybille, Joao Paulo Teixeira, and Hans-Joachim Wunderlich. <i>Synthesis for Testability - the ARCHIMEDES Approach</i>. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.","ieee":"S. Hellebrand, J. Paulo Teixeira, and H.-J. Wunderlich, <i>Synthesis for Testability - the ARCHIMEDES Approach</i>. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.","ama":"Hellebrand S, Paulo Teixeira J, Wunderlich H-J. <i>Synthesis for Testability - the ARCHIMEDES Approach</i>. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1994."},"year":"1994","place":"1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA","extern":"1","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"department":[{"_id":"48"}],"user_id":"659","_id":"13085","status":"public","type":"misc"},{"status":"public","publication":"ACM/IEEE International Conference on Computer-Aided Design (ICCAD'94)","type":"conference","language":[{"iso":"eng"}],"extern":"1","department":[{"_id":"48"}],"user_id":"209","_id":"13014","page":"110-116","citation":{"ama":"Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: <i>ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)</i>. IEEE; 1994:110-116. doi:<a href=\"https://doi.org/10.1109/iccad.1994.629752\">10.1109/iccad.1994.629752</a>","chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.” In <i>ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)</i>, 110–16. San Jose, CA, USA: IEEE, 1994. <a href=\"https://doi.org/10.1109/iccad.1994.629752\">https://doi.org/10.1109/iccad.1994.629752</a>.","ieee":"S. Hellebrand and H.-J. Wunderlich, “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures,” in <i>ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)</i>, 1994, pp. 110–116, doi: <a href=\"https://doi.org/10.1109/iccad.1994.629752\">10.1109/iccad.1994.629752</a>.","mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.” <i>ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)</i>, IEEE, 1994, pp. 110–16, doi:<a href=\"https://doi.org/10.1109/iccad.1994.629752\">10.1109/iccad.1994.629752</a>.","bibtex":"@inproceedings{Hellebrand_Wunderlich_1994, place={San Jose, CA, USA}, title={An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures}, DOI={<a href=\"https://doi.org/10.1109/iccad.1994.629752\">10.1109/iccad.1994.629752</a>}, booktitle={ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)}, publisher={IEEE}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={1994}, pages={110–116} }","short":"S. Hellebrand, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, San Jose, CA, USA, 1994, pp. 110–116.","apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. <i>ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)</i>, 110–116. <a href=\"https://doi.org/10.1109/iccad.1994.629752\">https://doi.org/10.1109/iccad.1994.629752</a>"},"year":"1994","place":"San Jose, CA, USA","doi":"10.1109/iccad.1994.629752","title":"An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures","author":[{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2019-08-28T10:27:43Z","publisher":"IEEE","date_updated":"2022-05-11T16:57:22Z"},{"page":"3-11","citation":{"ama":"Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: <i>Tagungsband Der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme</i>. ; 1994:3-11.","ieee":"S. Hellebrand and H.-J. Wunderlich, “Synthese schneller selbsttestbarer Steuerwerke,” in <i>Tagungsband der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme</i>, 1994, pp. 3–11.","chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” In <i>Tagungsband Der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme</i>, 3–11. Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994.","mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” <i>Tagungsband Der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme</i>, 1994, pp. 3–11.","bibtex":"@inproceedings{Hellebrand_Wunderlich_1994, place={Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany}, title={Synthese schneller selbsttestbarer Steuerwerke}, booktitle={Tagungsband der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={1994}, pages={3–11} }","short":"S. Hellebrand, H.-J. Wunderlich, in: Tagungsband Der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994, pp. 3–11.","apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. <i>Tagungsband Der GI/GME/ITG-Fachtagung \\&#38; Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme</i>, 3–11."},"place":"Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany","year":"1994","title":"Synthese schneller selbsttestbarer Steuerwerke","date_created":"2019-08-28T11:50:08Z","author":[{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich","first_name":"Hans-Joachim"}],"date_updated":"2022-05-11T16:58:10Z","status":"public","publication":"Tagungsband der GI/GME/ITG-Fachtagung \\& Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme","type":"conference","extern":"1","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"13059"},{"publication":"European Design and Test Conference (EDAC/ETC/EUROASIC)","type":"conference","status":"public","_id":"13013","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"extern":"1","year":"1994","place":"Paris, France","page":"580-585","citation":{"apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. <i>European Design and Test Conference (EDAC/ETC/EUROASIC)</i>, 580–585. <a href=\"https://doi.org/10.1109/edtc.1994.326815\">https://doi.org/10.1109/edtc.1994.326815</a>","mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.” <i>European Design and Test Conference (EDAC/ETC/EUROASIC)</i>, 1994, pp. 580–85, doi:<a href=\"https://doi.org/10.1109/edtc.1994.326815\">10.1109/edtc.1994.326815</a>.","short":"S. Hellebrand, H.-J. Wunderlich, in: European Design and Test Conference (EDAC/ETC/EUROASIC), Paris, France, 1994, pp. 580–585.","bibtex":"@inproceedings{Hellebrand_Wunderlich_1994, place={Paris, France}, title={Synthesis of Self-Testable Controllers}, DOI={<a href=\"https://doi.org/10.1109/edtc.1994.326815\">10.1109/edtc.1994.326815</a>}, booktitle={European Design and Test Conference (EDAC/ETC/EUROASIC)}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={1994}, pages={580–585} }","ama":"Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: <i>European Design and Test Conference (EDAC/ETC/EUROASIC)</i>. ; 1994:580-585. doi:<a href=\"https://doi.org/10.1109/edtc.1994.326815\">10.1109/edtc.1994.326815</a>","ieee":"S. Hellebrand and H.-J. Wunderlich, “Synthesis of Self-Testable Controllers,” in <i>European Design and Test Conference (EDAC/ETC/EUROASIC)</i>, 1994, pp. 580–585, doi: <a href=\"https://doi.org/10.1109/edtc.1994.326815\">10.1109/edtc.1994.326815</a>.","chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.” In <i>European Design and Test Conference (EDAC/ETC/EUROASIC)</i>, 580–85. Paris, France, 1994. <a href=\"https://doi.org/10.1109/edtc.1994.326815\">https://doi.org/10.1109/edtc.1994.326815</a>."},"date_updated":"2022-05-11T16:56:37Z","author":[{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T10:26:39Z","title":"Synthesis of Self-Testable Controllers","doi":"10.1109/edtc.1994.326815"},{"status":"public","type":"misc","extern":"1","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"user_id":"659","department":[{"_id":"48"}],"_id":"13081","citation":{"chicago":"Hellebrand, Sybille, Steffen Tarnick, Janusz Rajski, and Bernard Courtois. <i>Effiziente Erzeugung Deterministischer Muster Im Selbsttest</i>. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.","ieee":"S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, <i>Effiziente Erzeugung deterministischer Muster im Selbsttest</i>. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.","ama":"Hellebrand S, Tarnick S, Rajski J, Courtois B. <i>Effiziente Erzeugung Deterministischer Muster Im Selbsttest</i>. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany; 1993.","apa":"Hellebrand, S., Tarnick, S., Rajski, J., &#38; Courtois, B. (1993). <i>Effiziente Erzeugung deterministischer Muster im Selbsttest</i>. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany.","short":"S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Effiziente Erzeugung Deterministischer Muster Im Selbsttest, 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.","mla":"Hellebrand, Sybille, et al. <i>Effiziente Erzeugung Deterministischer Muster Im Selbsttest</i>. 1993.","bibtex":"@book{Hellebrand_Tarnick_Rajski_Courtois_1993, place={5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany}, title={Effiziente Erzeugung deterministischer Muster im Selbsttest}, author={Hellebrand, Sybille and Tarnick, Steffen and Rajski, Janusz and Courtois, Bernard}, year={1993} }"},"place":"5th ITG/GI/GME Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\", Holzhau, Germany","year":"1993","title":"Effiziente Erzeugung deterministischer Muster im Selbsttest","author":[{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Steffen","last_name":"Tarnick","full_name":"Tarnick, Steffen"},{"first_name":"Janusz","full_name":"Rajski, Janusz","last_name":"Rajski"},{"last_name":"Courtois","full_name":"Courtois, Bernard","first_name":"Bernard"}],"date_created":"2019-08-28T12:10:08Z","date_updated":"2022-01-06T06:51:28Z"},{"status":"public","type":"misc","keyword":["WORKSHOP"],"extern":"1","language":[{"iso":"eng"}],"_id":"13082","department":[{"_id":"48"}],"user_id":"659","year":"1993","place":"ARCHIMEDES Open Workshop on \"Synthesis - Architectural Testability Support\", Montpellier, France","citation":{"ieee":"S. Hellebrand and H.-J. Wunderlich, <i>Synthesis of Self-Testable Controllers</i>. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.","chicago":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. <i>Synthesis of Self-Testable Controllers</i>. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.","ama":"Hellebrand S, Wunderlich H-J. <i>Synthesis of Self-Testable Controllers</i>. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France; 1993.","apa":"Hellebrand, S., &#38; Wunderlich, H.-J. (1993). <i>Synthesis of Self-Testable Controllers</i>. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.","mla":"Hellebrand, Sybille, and Hans-Joachim Wunderlich. <i>Synthesis of Self-Testable Controllers</i>. 1993.","short":"S. Hellebrand, H.-J. Wunderlich, Synthesis of Self-Testable Controllers, ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.","bibtex":"@book{Hellebrand_Wunderlich_1993, place={ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France}, title={Synthesis of Self-Testable Controllers}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={1993} }"},"title":"Synthesis of Self-Testable Controllers","date_updated":"2022-01-06T06:51:28Z","date_created":"2019-08-28T12:10:50Z","author":[{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}]},{"type":"conference","publication":"ACM/IEEE International Conference on Computer Aided Design (ICCAD'93)","status":"public","user_id":"209","department":[{"_id":"48"}],"_id":"13015","extern":"1","language":[{"iso":"eng"}],"citation":{"short":"S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93), IEEE, 1993.","bibtex":"@inproceedings{Venkataraman_Rajski_Hellebrand_Tarnick_1993, title={An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers}, DOI={<a href=\"https://doi.org/10.1109/iccad.1993.580117\">10.1109/iccad.1993.580117</a>}, booktitle={ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)}, publisher={IEEE}, author={Venkataraman, Srikanth and Rajski, Janusz and Hellebrand, Sybille and Tarnick, Steffen}, year={1993} }","mla":"Venkataraman, Srikanth, et al. “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers.” <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)</i>, IEEE, 1993, doi:<a href=\"https://doi.org/10.1109/iccad.1993.580117\">10.1109/iccad.1993.580117</a>.","apa":"Venkataraman, S., Rajski, J., Hellebrand, S., &#38; Tarnick, S. (1993). An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)</i>. <a href=\"https://doi.org/10.1109/iccad.1993.580117\">https://doi.org/10.1109/iccad.1993.580117</a>","ama":"Venkataraman S, Rajski J, Hellebrand S, Tarnick S. An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. In: <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)</i>. IEEE; 1993. doi:<a href=\"https://doi.org/10.1109/iccad.1993.580117\">10.1109/iccad.1993.580117</a>","chicago":"Venkataraman, Srikanth, Janusz Rajski, Sybille Hellebrand, and Steffen Tarnick. “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers.” In <i>ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)</i>. IEEE, 1993. <a href=\"https://doi.org/10.1109/iccad.1993.580117\">https://doi.org/10.1109/iccad.1993.580117</a>.","ieee":"S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers,” 1993, doi: <a href=\"https://doi.org/10.1109/iccad.1993.580117\">10.1109/iccad.1993.580117</a>."},"year":"1993","date_created":"2019-08-28T10:27:44Z","author":[{"first_name":"Srikanth","full_name":"Venkataraman, Srikanth","last_name":"Venkataraman"},{"last_name":"Rajski","full_name":"Rajski, Janusz","first_name":"Janusz"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"},{"full_name":"Tarnick, Steffen","last_name":"Tarnick","first_name":"Steffen"}],"publisher":"IEEE","date_updated":"2022-05-11T16:58:55Z","doi":"10.1109/iccad.1993.580117","title":"An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers"},{"date_updated":"2022-01-06T06:51:27Z","date_created":"2019-08-28T10:31:14Z","author":[{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Steffen","full_name":"Tarnick, Steffen","last_name":"Tarnick"},{"first_name":"Janusz","last_name":"Rajski","full_name":"Rajski, Janusz"},{"last_name":"Courtois","full_name":"Courtois, Bernard","first_name":"Bernard"}],"title":"Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs","place":"Institut National Polytechnique de Grenoble, Grenoble, France","year":"1992","citation":{"bibtex":"@book{Hellebrand_Tarnick_Rajski_Courtois_1992, place={Institut National Polytechnique de Grenoble, Grenoble, France}, title={Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs}, author={Hellebrand, Sybille and Tarnick, Steffen and Rajski, Janusz and Courtois, Bernard}, year={1992} }","short":"S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Institut National Polytechnique de Grenoble, Grenoble, France, 1992.","mla":"Hellebrand, Sybille, et al. <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. 1992.","apa":"Hellebrand, S., Tarnick, S., Rajski, J., &#38; Courtois, B. (1992). <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. Institut National Polytechnique de Grenoble, Grenoble, France.","ama":"Hellebrand S, Tarnick S, Rajski J, Courtois B. <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. Institut National Polytechnique de Grenoble, Grenoble, France; 1992.","chicago":"Hellebrand, Sybille, Steffen Tarnick, Janusz Rajski, and Bernard Courtois. <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. Institut National Polytechnique de Grenoble, Grenoble, France, 1992.","ieee":"S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. Institut National Polytechnique de Grenoble, Grenoble, France, 1992."},"_id":"13023","department":[{"_id":"48"}],"user_id":"659","language":[{"iso":"eng"}],"extern":"1","type":"report","status":"public"},{"type":"misc","status":"public","department":[{"_id":"48"}],"user_id":"659","_id":"13076","extern":"1","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"citation":{"bibtex":"@book{Hellebrand_Tarnick_Rajski_Courtois_1992, place={IEEE Design for Testability Workshop, Vail, CO, USA}, title={Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs}, author={Hellebrand, Sybille and Tarnick, Steffen and Rajski, Janusz and Courtois, Bernard}, year={1992} }","mla":"Hellebrand, Sybille, et al. <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. 1992.","short":"S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, IEEE Design for Testability Workshop, Vail, CO, USA, 1992.","apa":"Hellebrand, S., Tarnick, S., Rajski, J., &#38; Courtois, B. (1992). <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. IEEE Design for Testability Workshop, Vail, CO, USA.","ama":"Hellebrand S, Tarnick S, Rajski J, Courtois B. <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. IEEE Design for Testability Workshop, Vail, CO, USA; 1992.","ieee":"S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. IEEE Design for Testability Workshop, Vail, CO, USA, 1992.","chicago":"Hellebrand, Sybille, Steffen Tarnick, Janusz Rajski, and Bernard Courtois. <i>Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs</i>. IEEE Design for Testability Workshop, Vail, CO, USA, 1992."},"year":"1992","place":"IEEE Design for Testability Workshop, Vail, CO, USA","date_created":"2019-08-28T12:05:09Z","author":[{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"},{"full_name":"Tarnick, Steffen","last_name":"Tarnick","first_name":"Steffen"},{"first_name":"Janusz","last_name":"Rajski","full_name":"Rajski, Janusz"},{"full_name":"Courtois, Bernard","last_name":"Courtois","first_name":"Bernard"}],"date_updated":"2022-01-06T06:51:28Z","title":"Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs"}]