[{"title":"Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test","date_created":"2019-03-27T08:57:42Z","publisher":"World Scientific Publishing Company","year":"2019","issue":"1","language":[{"iso":"eng"}],"publication":"Journal of Circuits, Systems and Computers","doi":"10.1142/s0218126619400012","volume":28,"author":[{"first_name":"Alexander","full_name":"Sprenger, Alexander","id":"22707","last_name":"Sprenger"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}],"date_updated":"2022-01-06T07:03:58Z","intvolume":"        28","page":"1-23","citation":{"bibtex":"@article{Sprenger_Hellebrand_2019, title={Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}, volume={28}, DOI={<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>}, number={1}, journal={Journal of Circuits, Systems and Computers}, publisher={World Scientific Publishing Company}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–23} }","short":"A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.","mla":"Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” <i>Journal of Circuits, Systems and Computers</i>, vol. 28, no. 1, World Scientific Publishing Company, 2019, pp. 1–23, doi:<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>.","apa":"Sprenger, A., &#38; Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. <i>Journal of Circuits, Systems and Computers</i>, <i>28</i>(1), 1–23. <a href=\"https://doi.org/10.1142/s0218126619400012\">https://doi.org/10.1142/s0218126619400012</a>","ama":"Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. <i>Journal of Circuits, Systems and Computers</i>. 2019;28(1):1-23. doi:<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>","ieee":"A. Sprenger and S. Hellebrand, “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test,” <i>Journal of Circuits, Systems and Computers</i>, vol. 28, no. 1, pp. 1–23, 2019.","chicago":"Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” <i>Journal of Circuits, Systems and Computers</i> 28, no. 1 (2019): 1–23. <a href=\"https://doi.org/10.1142/s0218126619400012\">https://doi.org/10.1142/s0218126619400012</a>."},"publication_identifier":{"issn":["0218-1266","1793-6454"]},"publication_status":"published","department":[{"_id":"48"}],"user_id":"59789","_id":"8667","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","type":"journal_article"},{"status":"public","abstract":[{"lang":"eng","text":"Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test."}],"type":"journal_article","publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"13048","citation":{"chicago":"Kampmann, Matthias, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Built-in Test for Hidden Delay Faults.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i> 38, no. 10 (2019): 1956–68.","ieee":"M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, and H.-J. Wunderlich, “Built-in Test for Hidden Delay Faults,” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, vol. 38, no. 10, pp. 1956–1968, 2019.","ama":"Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>. 2019;38(10):1956-1968.","bibtex":"@article{Kampmann_A. Kochte_Liu_Schneider_Hellebrand_Wunderlich_2019, title={Built-in Test for Hidden Delay Faults}, volume={38}, number={10}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, publisher={IEEE}, author={Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2019}, pages={1956–1968} }","short":"M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.","mla":"Kampmann, Matthias, et al. “Built-in Test for Hidden Delay Faults.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, vol. 38, no. 10, IEEE, 2019, pp. 1956–68.","apa":"Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &#38; Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, <i>38</i>(10), 1956–1968."},"intvolume":"        38","page":"1956 - 1968","year":"2019","issue":"10","publication_status":"published","publication_identifier":{"eissn":["1937-4151"]},"title":"Built-in Test for Hidden Delay Faults","author":[{"full_name":"Kampmann, Matthias","id":"10935","last_name":"Kampmann","first_name":"Matthias"},{"first_name":"Michael","full_name":"A. Kochte, Michael","last_name":"A. Kochte"},{"first_name":"Chang","full_name":"Liu, Chang","last_name":"Liu"},{"first_name":"Eric","last_name":"Schneider","full_name":"Schneider, Eric"},{"full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T11:44:25Z","volume":38,"publisher":"IEEE","date_updated":"2022-01-06T06:51:27Z"},{"title":"A Hybrid Space Compactor for Adaptive X-Handling","conference":{"location":"Washington, DC, USA","end_date":"2019-11-14","start_date":"2019-11-12","name":"50th IEEE International Test Conference (ITC)"},"date_updated":"2022-05-11T17:09:35Z","publisher":"IEEE","date_created":"2019-08-14T06:59:04Z","author":[{"last_name":"Maaz","full_name":"Maaz, Mohammad Urf","id":"49274","first_name":"Mohammad Urf"},{"first_name":"Alexander","last_name":"Sprenger","full_name":"Sprenger, Alexander","id":"22707"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"place":"Washington, DC, USA","year":"2019","page":"1-8","citation":{"apa":"Maaz, M. U., Sprenger, A., &#38; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. <i>50th IEEE International Test Conference (ITC)</i>, 1–8.","bibtex":"@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA}, title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8} }","short":"M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.","mla":"Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” <i>50th IEEE International Test Conference (ITC)</i>, IEEE, 2019, pp. 1–8.","ieee":"M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in <i>50th IEEE International Test Conference (ITC)</i>, Washington, DC, USA, 2019, pp. 1–8.","chicago":"Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid Space Compactor for Adaptive X-Handling.” In <i>50th IEEE International Test Conference (ITC)</i>, 1–8. Washington, DC, USA: IEEE, 2019.","ama":"Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: <i>50th IEEE International Test Conference (ITC)</i>. IEEE; 2019:1-8."},"quality_controlled":"1","publication_status":"published","keyword":["Faster-than-at-speed test","BIST","DFT","Test response compaction","Stochastic compactor","X-handling"],"language":[{"iso":"eng"}],"_id":"12918","department":[{"_id":"48"}],"user_id":"209","abstract":[{"text":"The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. ","lang":"eng"}],"status":"public","publication":"50th IEEE International Test Conference (ITC)","type":"conference"},{"status":"public","type":"misc","keyword":["WORKSHOP"],"language":[{"iso":"ger"}],"_id":"4576","user_id":"22707","department":[{"_id":"48"}],"year":"2018","place":"Freiburg, Germany","citation":{"apa":"Sprenger, A., &#38; Hellebrand, S. (2018). <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).","bibtex":"@book{Sprenger_Hellebrand_2018, place={Freiburg, Germany}, title={Stochastische Kompaktierung für den Hochgeschwindigkeitstest}, publisher={30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18)}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }","short":"A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.","mla":"Sprenger, Alexander, and Sybille Hellebrand. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","ieee":"A. Sprenger and S. Hellebrand, <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","chicago":"Sprenger, Alexander, and Sybille Hellebrand. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","ama":"Sprenger A, Hellebrand S. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018."},"title":"Stochastische Kompaktierung für den Hochgeschwindigkeitstest","publisher":"30. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'18)","date_updated":"2022-01-06T07:01:13Z","author":[{"first_name":"Alexander","id":"22707","full_name":"Sprenger, Alexander","last_name":"Sprenger"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_created":"2018-10-02T12:29:44Z"},{"language":[{"iso":"eng"}],"_id":"12974","user_id":"209","department":[{"_id":"48"}],"status":"public","type":"journal_article","publication":"IEEE Embedded Systems Letters","title":"Guest Editors' Introduction - Special Issue on Approximate Computing","doi":"10.1109/les.2018.2789942","publisher":"IEEE","date_updated":"2022-01-06T06:51:27Z","date_created":"2019-08-28T08:40:58Z","author":[{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"first_name":"Joerg","last_name":"Henkel","full_name":"Henkel, Joerg"},{"first_name":"Anand","last_name":"Raghunathan","full_name":"Raghunathan, Anand"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"volume":10,"year":"2018","citation":{"chicago":"Hellebrand, Sybille, Joerg Henkel, Anand Raghunathan, and Hans-Joachim Wunderlich. “Guest Editors’ Introduction - Special Issue on Approximate Computing.” <i>IEEE Embedded Systems Letters</i> 10, no. 1 (2018): 1–1. <a href=\"https://doi.org/10.1109/les.2018.2789942\">https://doi.org/10.1109/les.2018.2789942</a>.","ieee":"S. Hellebrand, J. Henkel, A. Raghunathan, and H.-J. Wunderlich, “Guest Editors’ Introduction - Special Issue on Approximate Computing,” <i>IEEE Embedded Systems Letters</i>, vol. 10, no. 1, pp. 1–1, 2018.","ama":"Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. <i>IEEE Embedded Systems Letters</i>. 2018;10(1):1-1. doi:<a href=\"https://doi.org/10.1109/les.2018.2789942\">10.1109/les.2018.2789942</a>","bibtex":"@article{Hellebrand_Henkel_Raghunathan_Wunderlich_2018, title={Guest Editors’ Introduction - Special Issue on Approximate Computing}, volume={10}, DOI={<a href=\"https://doi.org/10.1109/les.2018.2789942\">10.1109/les.2018.2789942</a>}, number={1}, journal={IEEE Embedded Systems Letters}, publisher={IEEE}, author={Hellebrand, Sybille and Henkel, Joerg and Raghunathan, Anand and Wunderlich, Hans-Joachim}, year={2018}, pages={1–1} }","short":"S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.","mla":"Hellebrand, Sybille, et al. “Guest Editors’ Introduction - Special Issue on Approximate Computing.” <i>IEEE Embedded Systems Letters</i>, vol. 10, no. 1, IEEE, 2018, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/les.2018.2789942\">10.1109/les.2018.2789942</a>.","apa":"Hellebrand, S., Henkel, J., Raghunathan, A., &#38; Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. <i>IEEE Embedded Systems Letters</i>, <i>10</i>(1), 1–1. <a href=\"https://doi.org/10.1109/les.2018.2789942\">https://doi.org/10.1109/les.2018.2789942</a>"},"intvolume":"        10","page":"1-1","issue":"1"},{"type":"journal_article","publication":"Microelectronics Reliability","status":"public","user_id":"659","department":[{"_id":"48"}],"_id":"13057","language":[{"iso":"eng"}],"citation":{"ama":"Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. <i>Microelectronics Reliability</i>. 2018;80:124-133.","chicago":"Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test - A Simulation Study.” <i>Microelectronics Reliability</i> 80 (2018): 124–33.","ieee":"M. Kampmann and S. Hellebrand, “Design For Small Delay Test - A Simulation Study,” <i>Microelectronics Reliability</i>, vol. 80, pp. 124–133, 2018.","mla":"Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test - A Simulation Study.” <i>Microelectronics Reliability</i>, vol. 80, 2018, pp. 124–33.","bibtex":"@article{Kampmann_Hellebrand_2018, title={Design For Small Delay Test - A Simulation Study}, volume={80}, journal={Microelectronics Reliability}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2018}, pages={124–133} }","short":"M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.","apa":"Kampmann, M., &#38; Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. <i>Microelectronics Reliability</i>, <i>80</i>, 124–133."},"intvolume":"        80","page":"124-133","year":"2018","author":[{"full_name":"Kampmann, Matthias","id":"10935","last_name":"Kampmann","first_name":"Matthias"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"date_created":"2019-08-28T11:49:25Z","volume":80,"date_updated":"2022-01-06T06:51:27Z","title":"Design For Small Delay Test - A Simulation Study"},{"doi":"10.1109/ddecs.2018.00020","title":"Tuning Stochastic Space Compaction to Faster-than-at-Speed Test","author":[{"first_name":"Alexander","id":"22707","full_name":"Sprenger, Alexander","last_name":"Sprenger"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"date_created":"2018-10-02T12:18:46Z","date_updated":"2022-05-11T17:10:37Z","publisher":"IEEE","citation":{"ieee":"A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>.","chicago":"Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” In <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. Budapest, Hungary: IEEE, 2018. <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">https://doi.org/10.1109/ddecs.2018.00020</a>.","ama":"Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>","apa":"Sprenger, A., &#38; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">https://doi.org/10.1109/ddecs.2018.00020</a>","bibtex":"@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>}, booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)}, publisher={IEEE}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }","mla":"Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>.","short":"A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS), IEEE, Budapest, Hungary, 2018."},"year":"2018","place":"Budapest, Hungary","publication_identifier":{"isbn":["9781538657546"]},"publication_status":"published","language":[{"iso":"eng"}],"department":[{"_id":"48"}],"user_id":"209","_id":"4575","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","publication":"2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","type":"conference"},{"publication":"27th IEEE Asian Test Symposium (ATS'18)","type":"conference","status":"public","department":[{"_id":"48"}],"user_id":"209","_id":"10575","language":[{"iso":"eng"}],"publication_identifier":{"isbn":["9781538694664"]},"publication_status":"published","citation":{"apa":"Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., &#38; Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. <i>27th IEEE Asian Test Symposium (ATS’18)</i>. <a href=\"https://doi.org/10.1109/ats.2018.00028\">https://doi.org/10.1109/ats.2018.00028</a>","bibtex":"@inproceedings{Liu_Schneider_Kampmann_Hellebrand_Wunderlich_2018, title={Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}, DOI={<a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>}, booktitle={27th IEEE Asian Test Symposium (ATS’18)}, author={Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2018} }","short":"C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.","mla":"Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” <i>27th IEEE Asian Test Symposium (ATS’18)</i>, 2018, doi:<a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>.","ama":"Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: <i>27th IEEE Asian Test Symposium (ATS’18)</i>. ; 2018. doi:<a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>","chicago":"Liu, Chang, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” In <i>27th IEEE Asian Test Symposium (ATS’18)</i>, 2018. <a href=\"https://doi.org/10.1109/ats.2018.00028\">https://doi.org/10.1109/ats.2018.00028</a>.","ieee":"C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: <a href=\"https://doi.org/10.1109/ats.2018.00028\">10.1109/ats.2018.00028</a>."},"year":"2018","author":[{"first_name":"Chang","full_name":"Liu, Chang","last_name":"Liu"},{"last_name":"Schneider","full_name":"Schneider, Eric","first_name":"Eric"},{"id":"10935","full_name":"Kampmann, Matthias","last_name":"Kampmann","first_name":"Matthias"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"date_created":"2019-07-05T08:14:58Z","date_updated":"2022-05-11T17:11:53Z","doi":"10.1109/ats.2018.00028","title":"Extending Aging Monitors for Early Life and Wear-Out Failure Prevention"},{"publication":"35th IEEE VLSI Test Symposium (VTS'17)","type":"conference","status":"public","department":[{"_id":"48"}],"user_id":"209","_id":"12973","language":[{"iso":"eng"}],"citation":{"ama":"Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: <i>35th IEEE VLSI Test Symposium (VTS’17)</i>. Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:<a href=\"https://doi.org/10.1109/vts.2017.7928933\">10.1109/vts.2017.7928933</a>","chicago":"Deshmukh, Jyotirmoy, Wolfgang Kunz, Hans-Joachim Wunderlich, and Sybille Hellebrand. “Special Session on Early Life Failures.” In <i>35th IEEE VLSI Test Symposium (VTS’17)</i>. Caesars Palace, Las Vegas, Nevada, USA: IEEE, 2017. <a href=\"https://doi.org/10.1109/vts.2017.7928933\">https://doi.org/10.1109/vts.2017.7928933</a>.","ieee":"J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session on Early Life Failures,” in <i>35th IEEE VLSI Test Symposium (VTS’17)</i>, 2017.","short":"J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. 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