---
_id: '24'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL.
In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing
(H2RC). ; 2016.'
apa: Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA
using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC).
bibtex: '@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation
on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian},
year={2016} }'
chicago: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation
on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC), 2016.
ieee: T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,”
2016.
mla: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on
FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC), 2016.
short: 'T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC), 2016.'
date_created: 2017-07-26T15:00:43Z
date_updated: 2023-09-26T13:26:17Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: kenter
date_created: 2018-11-14T12:38:45Z
date_updated: 2018-11-14T12:38:45Z
file_id: '5602'
file_name: paper_26.pdf
file_size: 129552
relation: main_file
success: 1
file_date_updated: 2018-11-14T12:38:45Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '32'
grant_number: PL 595/2-1 / 320898746
name: Performance and Efficiency in HPC with Custom Computing
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
publication: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing
(H2RC)
quality_controlled: '1'
status: public
title: Microdisk Cavity FDTD Simulation on FPGA using OpenCL
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '165'
abstract:
- lang: eng
text: A broad spectrum of applications can be accelerated by offloading computation
intensive parts to reconfigurable hardware. However, to achieve speedups, the
number of loop it- erations (trip count) needs to be sufficiently large to amortize
offloading overheads. Trip counts are frequently not known at compile time, but
only at runtime just before entering a loop. Therefore, we propose to generate
code for both the CPU and the coprocessor, and defer the offloading decision to
the application runtime. We demonstrate how a toolflow, based on the LLVM compiler
framework, can automatically embed dynamic offloading de- cisions into the application
code. We perform in-depth static and dynamic analysis of pop- ular benchmarks,
which confirm the general potential of such an approach. We also pro- pose to
optimize the offloading process by decoupling the runtime decision from the loop
execution (decision slack). The feasibility of our approach is demonstrated by
a toolflow that automatically identifies suitable data-parallel loops and generates
code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow
with representative loops executed for different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding
Dynamic Offloading Decisions into Application Code. Computers and Electrical
Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and
Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers
and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021
bibtex: '@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for
Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021},
journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz,
Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian},
year={2016}, pages={91–111} }'
chicago: 'Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Potential and Methods for Embedding Dynamic Offloading Decisions into Application
Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.'
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for
Embedding Dynamic Offloading Decisions into Application Code,” Computers and
Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.'
mla: Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading
Decisions into Application Code.” Computers and Electrical Engineering,
vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.
short: G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering
55 (2016) 91–111.
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:26:38Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
doi: 10.1016/j.compeleceng.2016.04.021
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:45:47Z
date_updated: 2018-03-21T12:45:47Z
file_id: '1544'
file_name: 165-1-s2.0-S0045790616301021-main.pdf
file_size: 3037854
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:45:47Z
has_accepted_license: '1'
intvolume: ' 55'
language:
- iso: eng
page: 91-111
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Computers and Electrical Engineering
publication_identifier:
issn:
- 0045-7906
publisher: Elsevier
quality_controlled: '1'
status: public
title: Potential and Methods for Embedding Dynamic Offloading Decisions into Application
Code
type: journal_article
user_id: '15278'
volume: 55
year: '2016'
...
---
_id: '168'
abstract:
- lang: eng
text: The use of heterogeneous computing resources, such as Graphic Processing Units
or other specialized coprocessors, has become widespread in recent years because
of their per- formance and energy efficiency advantages. Approaches for managing
and scheduling tasks to heterogeneous resources are still subject to research.
Although queuing systems have recently been extended to support accelerator resources,
a general solution that manages heterogeneous resources at the operating system-
level to exploit a global view of the system state is still missing.In this paper
we present a user space scheduler that enables task scheduling and migration on
heterogeneous processing resources in Linux. Using run queues for available resources
we perform scheduling decisions based on the system state and on task characterization
from earlier measurements. With a pro- gramming pattern that supports the integration
of checkpoints into applications, we preempt tasks and migrate them between three
very different compute resources. Considering static and dynamic workload scenarios,
we show that this approach can gain up to 17% performance, on average 7%, by effectively
avoiding idle resources. We demonstrate that a work-conserving strategy without
migration is no suitable alternative.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling
with task migration for a heterogeneous compute node in the data center. In: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE). EDA Consortium / IEEE; 2016:912-917.'
apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center.
Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 912–917.
bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center},
booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim
and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco},
year={2016}, pages={912–917} }'
chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco
Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous
Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation
& Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium
/ IEEE, 2016.
ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center,”
in Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2016, pp. 912–917.
mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for
a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design,
Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium
/ IEEE, 2016, pp. 912–17.
short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE), EDA Consortium / IEEE, 2016, pp. 912–917.'
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:27:00Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:41:55Z
date_updated: 2018-03-21T12:41:55Z
file_id: '1541'
file_name: 168-07459438.pdf
file_size: 261356
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:41:55Z
has_accepted_license: '1'
language:
- iso: eng
page: 912-917
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Performance-centric scheduling with task migration for a heterogeneous compute
node in the data center
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '171'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application
partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop
on Reconfigurable Computing (WRC). ; 2016.'
apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities
for deferring application partitioning and accelerator synthesis to runtime (extended
abstract). Workshop on Reconfigurable Computing (WRC).
bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for
deferring application partitioning and accelerator synthesis to runtime (extended
abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter,
Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016}
}'
chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl.
“Opportunities for Deferring Application Partitioning and Accelerator Synthesis
to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC),
2016.
ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring
application partitioning and accelerator synthesis to runtime (extended abstract),”
2016.
mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning
and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable
Computing (WRC), 2016.
short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable
Computing (WRC), 2016.'
date_created: 2017-10-17T12:41:25Z
date_updated: 2023-09-26T13:27:21Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:39:46Z
date_updated: 2018-03-21T12:39:46Z
file_id: '1538'
file_name: 171-plessl16_fpl_wrc.pdf
file_size: 54421
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:39:46Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Workshop on Reconfigurable Computing (WRC)
quality_controlled: '1'
status: public
title: Opportunities for deferring application partitioning and accelerator synthesis
to runtime (extended abstract)
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '296'
abstract:
- lang: eng
text: FPGAs are known to permit huge gains in performance and efficiency for suitable
applications but still require reduced design efforts and shorter development
cycles for wider adoption. In this work, we compare the resulting performance
of two design concepts that in different ways promise such increased productivity.
As common starting point, we employ a kernel-centric design approach, where computational
hotspots in an application are identified and individually accelerated on FPGA.
By means of a complex stereo matching application, we evaluate two fundamentally
different design philosophies and approaches for implementing the required kernels
on FPGAs. In the first implementation approach, we designed individually specialized
data flow kernels in a spatial programming language for a Maxeler FPGA platform;
in the alternative design approach, we target a vector coprocessor with large
vector lengths, which is implemented as a form of programmable overlay on the
application FPGAs of a Convey HC-1. We assess both approaches in terms of overall
system performance, raw kernel performance, and performance relative to invested
resources. After compensating for the effects of the underlying hardware platforms,
the specialized dataflow kernels on the Maxeler platform are around 3x faster
than kernels executing on the Convey vector coprocessor. In our concrete scenario,
due to trade-offs between reconfiguration overheads and exposed parallelism, the
advantage of specialized dataflow kernels is reduced to around 2.5x.
article_number: '859425'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels
and a Reusable Overlay in a Stereo-Matching Case Study. International Journal
of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International
Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425
bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015},
DOI={10.1155/2015/859425}, number={859425},
journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi},
author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015}
}'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs
between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”
International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized
Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International
Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015,
doi: 10.1155/2015/859425.'
mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and
a Reusable Overlay in a Stereo-Matching Case Study.” International Journal
of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable
Computing (IJRC) 2015 (2015).
date_created: 2017-10-17T12:41:49Z
date_updated: 2023-09-26T13:29:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2015/859425
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:47:56Z
date_updated: 2018-03-20T07:47:56Z
file_id: '1444'
file_name: 296-859425.pdf
file_size: 2993898
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:47:56Z
has_accepted_license: '1'
intvolume: ' 2015'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: International Journal of Reconfigurable Computing (IJRC)
publisher: Hindawi
quality_controlled: '1'
status: public
title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a
Stereo-Matching Case Study
type: journal_article
user_id: '15278'
volume: 2015
year: '2015'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '528'
abstract:
- lang: eng
text: Cold-boot attacks exploit the fact that DRAM contents are not immediately
lost when a PC is powered off. Instead the contents decay rather slowly, in particular
if the DRAM chips are cooled to low temperatures. This effect opens an attack
vector on cryptographic applications that keep decrypted keys in DRAM. An attacker
with access to the target computer can reboot it or remove the RAM modules and
quickly copy the RAM contents to non-volatile memory. By exploiting the known
cryptographic structure of the cipher and layout of the key data in memory, in
our application an AES key schedule with redundancy, the resulting memory image
can be searched for sections that could correspond to decayed cryptographic keys;
then, the attacker can attempt to reconstruct the original key. However, the runtime
of these algorithms grows rapidly with increasing memory image size, error rate
and complexity of the bit error model, which limits the practicability of the
approach.In this work, we study how the algorithm for key search can be accelerated
with custom computing machines. We present an FPGA-based architecture on a Maxeler
dataflow computing system that outperforms a software implementation up to 205x,
which significantly improves the practicability of cold-attacks against AES.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot
Attacks against AES. In: Proceedings of the International Conference on Field-Programmable
Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394'
apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated
Key Search for Cold-Boot Attacks against AES. Proceedings of the International
Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394
bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated
Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge,
Christoph and Plessl, Christian}, year={2013}, pages={386–389} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl.
“FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT), 386–89.
IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.
ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search
for Cold-Boot Attacks against AES,” in Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.'
mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks
against AES.” Proceedings of the International Conference on Field-Programmable
Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.'
date_created: 2017-10-17T12:42:35Z
date_updated: 2023-09-26T13:37:35Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2013.6718394
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:36:08Z
date_updated: 2018-03-15T10:36:08Z
file_id: '1294'
file_name: 528-plessl13_fpt.pdf
file_size: 822680
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:36:08Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 386-389
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '13'
name: SFB 901 - Subproject C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '591'
abstract:
- lang: eng
text: One major obstacle for a wide spread FPGA usage in general-purpose computing
is the development tool flow that requires much higher effort than for pure software
solutions. Convey Computer promises a solution to this problem for their HC-1
platform, where the FPGAs are configured to run as a vector processor and the software
source code can be annotated with pragmas that guide an automated vectorization
process. We investigate this approach for a stereo matching algorithm that has
abundant parallelism and a number of different computational patterns. We note
that for this case study the automated vectorization in its current state doesn’t
hold its productivity promise. However, we also show that using the Vector Personality
can yield a significant speedups compared to CPU implementations in two of three
investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations,
but can come with much reduced development effort.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
citation:
ama: 'Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware
efficiency for ease of use? In: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773'
apa: Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization
- Trading hardware efficiency for ease of use? Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773
bibtex: '@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization
- Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian
and Schmitz, Henning}, year={2012}, pages={1–8} }'
chicago: Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization
- Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012.
https://doi.org/10.1109/ReConFig.2012.6416773.
ieee: 'T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading
hardware efficiency for ease of use?,” in Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8,
doi: 10.1109/ReConFig.2012.6416773.'
mla: Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency
for Ease of Use?” Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.
short: 'T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.'
date_created: 2017-10-17T12:42:47Z
date_updated: 2023-09-26T13:41:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2012.6416773
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T08:33:18Z
date_updated: 2018-03-15T08:33:18Z
file_id: '1257'
file_name: 591-ReConFig2012Kenter_Schmitz_Plessl.pdf
file_size: 371235
relation: main_file
success: 1
file_date_updated: 2018-03-15T08:33:18Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Pragma based parallelization - Trading hardware efficiency for ease of use?
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '567'
abstract:
- lang: eng
text: Heterogeneous machines are gaining momentum in the High Performance Computing
field, due to the theoretical speedups and power consumption. In practice, while
some applications meet the performance expectations, heterogeneous architectures
still require a tremendous effort from the application developers. This work presents
a code generation method to port codes into heterogeneous platforms, based on
transformations of the control flow into function calls. The results show that
the cost of the function-call mechanism is affordable for the tested HPC kernels.
The complete toolchain, based on the LLVM compiler infrastructure, is fully automated
once the sequential specification is provided.
author:
- first_name: Pablo
full_name: Barrio, Pablo
last_name: Barrio
- first_name: Carlos
full_name: Carreras, Carlos
last_name: Carreras
- first_name: Roberto
full_name: Sierra, Roberto
last_name: Sierra
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs
into function calls: Code generation for heterogeneous architectures. In: Proceedings
of the International Conference on High Performance Computing and Simulation (HPCS).
IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973'
apa: 'Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012).
Turning control flow graphs into function calls: Code generation for heterogeneous
architectures. Proceedings of the International Conference on High Performance
Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973'
bibtex: '@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning
control flow graphs into function calls: Code generation for heterogeneous architectures},
DOI={10.1109/HPCSim.2012.6266973},
booktitle={Proceedings of the International Conference on High Performance Computing
and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras,
Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012},
pages={559–565} }'
chicago: 'Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian
Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for
Heterogeneous Architectures.” In Proceedings of the International Conference
on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.'
ieee: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control
flow graphs into function calls: Code generation for heterogeneous architectures,”
in Proceedings of the International Conference on High Performance Computing
and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.'
mla: 'Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code
Generation for Heterogeneous Architectures.” Proceedings of the International
Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012,
pp. 559–65, doi:10.1109/HPCSim.2012.6266973.'
short: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings
of the International Conference on High Performance Computing and Simulation (HPCS),
IEEE, 2012, pp. 559–565.'
date_created: 2017-10-17T12:42:42Z
date_updated: 2023-09-26T13:42:54Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/HPCSim.2012.6266973
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:20:24Z
date_updated: 2018-03-15T10:20:24Z
file_id: '1275'
file_name: 567-ba-ca-12a.pdf
file_size: 288508
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:20:24Z
has_accepted_license: '1'
language:
- iso: eng
page: 559-565
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the International Conference on High Performance Computing
and Simulation (HPCS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Turning control flow graphs into function calls: Code generation for heterogeneous
architectures'
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2191'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for
CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference.
; 2011.'
apa: Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation
and Partitioning for CPU-Accelerator Architectures. In Intel European Research
and Innovation Conference.
bibtex: '@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation
and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European
Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian
and Platzner, Marco and Kauschke, Michael}, year={2011} }'
chicago: Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke.
“Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European
Research and Innovation Conference, 2011.
ieee: T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning
for CPU-Accelerator Architectures,” in Intel European Research and Innovation
Conference, 2011.
mla: Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.”
Intel European Research and Innovation Conference, 2011.
short: 'T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research
and Innovation Conference, 2011.'
date_created: 2018-04-03T14:34:57Z
date_updated: 2022-01-06T06:55:19Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- funding-intel
publication: Intel European Research and Innovation Conference
status: public
title: Estimation and Partitioning for CPU-Accelerator Architectures
type: conference
user_id: '24135'
year: '2011'
...
---
_id: '2200'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework
for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int.
Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance
Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.
Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY,
USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures}, DOI={10.1145/1950413.1950448},
booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM},
author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke,
Michael}, year={2011}, pages={177–180} }'
chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA),
177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.'
ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc.
Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:
10.1145/1950413.1950448.'
mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration
of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate
Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on
Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.'
date_created: 2018-04-03T15:08:13Z
date_updated: 2023-09-26T13:45:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/1950413.1950448
keyword:
- design space exploration
- LLVM
- partitioning
- performance
- estimation
- funding-intel
language:
- iso: eng
page: 177-180
place: New York, NY, USA
publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)
publication_identifier:
isbn:
- 978-1-4503-0554-9
publisher: ACM
quality_controlled: '1'
status: public
title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2228'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA). ; 2010.'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance
Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
& S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping
(WARP), International Symposium on Computer Architecture (ISCA).
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
Workshop on Architectural Research Prototyping (WARP), International Symposium
on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
Sandra}, year={2010} }'
chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
In Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra
Larrabee, 2010.
ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on
Architectural Research Prototyping (WARP), International Symposium on Computer
Architecture (ISCA), 2010.
mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP),
International Symposium on Computer Architecture (ISCA), edited by Omar Hammami
and Sandra Larrabee, 2010.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
(Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
full_name: Hammami, Omar
last_name: Hammami
- first_name: Sandra
full_name: Larrabee, Sandra
last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2365'
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sven
full_name: Döhre, Sven
last_name: Döhre
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Ulf
full_name: Lorenz, Ulf
last_name: Lorenz
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Andre
full_name: Send, Andre
last_name: Send
- first_name: Alexander
full_name: Warkentin, Alexander
last_name: Warkentin
citation:
ama: 'Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2008:245-251.'
apa: 'Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T.,
… Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
(pp. 245–251). CSREA Press.'
bibtex: '@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008,
title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter,
Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander},
year={2008}, pages={245–251} }'
chicago: 'Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz,
Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating
GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 245–51. CSREA Press, 2008.'
ieee: 'M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2008, pp. 245–251.'
mla: 'Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2008, pp. 245–51.'
short: 'M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A.
Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:34:35Z
date_updated: 2022-01-06T06:55:58Z
department:
- _id: '27'
- _id: '78'
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-064-7
publisher: CSREA Press
status: public
title: 'The GOmputer: Accelerating GO with FPGAs'
type: conference
user_id: '24135'
year: '2008'
...