---
_id: '65101'
abstract:
- lang: eng
text: Various methods to measure the dynamic behavior of particles require the calculation
of autocorrelation functions. For this purpose, fast multi-tau correlators have
been developed in dedicated hardware, in software, and on FPGAs. However, for
methods such as X-ray Photon Correlation Spectroscopy (XPCS), which requires to
calculate the autocorrelation function independently for hundreds of thousands
to millions of pixels from high-resolution detectors, current approaches rely
on offline processing after data acquisition. Moreover, the internal pipeline
state of so many independent correlators is far too large to keep it on-chip.
In this work, we propose a design approach on FPGAs, where pipeline contexts are
stored in off-chip HBM memory. Each compute unit iteratively loads the state for
a single pixel, processes a short time series for this pixel, and afterwards writes
back the context in a dataflow pipeline. We have implemented the required compute
kernels with Vitis HLS and analyze resulting designs on an Alveo U280 card. The
design achieves the expected performance and for the first time provides sufficient
throughput for current high-end detectors used in XPCS.
author:
- first_name: Abdul Rehman
full_name: Tareen, Abdul Rehman
id: '76938'
last_name: Tareen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Tareen AR, Plessl C, Kenter T. Fast Multi-Tau Correlators on FPGA with Context
Switching From and to High- Bandwidth Memory. In: 2025 International Conference
on Field Programmable Technology (ICFPT). IEEE; 2026. doi:10.1109/icfpt67023.2025.00027'
apa: Tareen, A. R., Plessl, C., & Kenter, T. (2026). Fast Multi-Tau Correlators
on FPGA with Context Switching From and to High- Bandwidth Memory. 2025 International
Conference on Field Programmable Technology (ICFPT). https://doi.org/10.1109/icfpt67023.2025.00027
bibtex: '@inproceedings{Tareen_Plessl_Kenter_2026, title={Fast Multi-Tau Correlators
on FPGA with Context Switching From and to High- Bandwidth Memory}, DOI={10.1109/icfpt67023.2025.00027},
booktitle={2025 International Conference on Field Programmable Technology (ICFPT)},
publisher={IEEE}, author={Tareen, Abdul Rehman and Plessl, Christian and Kenter,
Tobias}, year={2026} }'
chicago: Tareen, Abdul Rehman, Christian Plessl, and Tobias Kenter. “Fast Multi-Tau
Correlators on FPGA with Context Switching From and to High- Bandwidth Memory.”
In 2025 International Conference on Field Programmable Technology (ICFPT).
IEEE, 2026. https://doi.org/10.1109/icfpt67023.2025.00027.
ieee: 'A. R. Tareen, C. Plessl, and T. Kenter, “Fast Multi-Tau Correlators on FPGA
with Context Switching From and to High- Bandwidth Memory,” 2026, doi: 10.1109/icfpt67023.2025.00027.'
mla: Tareen, Abdul Rehman, et al. “Fast Multi-Tau Correlators on FPGA with Context
Switching From and to High- Bandwidth Memory.” 2025 International Conference
on Field Programmable Technology (ICFPT), IEEE, 2026, doi:10.1109/icfpt67023.2025.00027.
short: 'A.R. Tareen, C. Plessl, T. Kenter, in: 2025 International Conference on
Field Programmable Technology (ICFPT), IEEE, 2026.'
date_created: 2026-03-24T09:02:22Z
date_updated: 2026-03-24T09:04:31Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/icfpt67023.2025.00027
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2025 International Conference on Field Programmable Technology (ICFPT)
publication_status: published
publisher: IEEE
status: public
title: Fast Multi-Tau Correlators on FPGA with Context Switching From and to High-
Bandwidth Memory
type: conference
user_id: '3145'
year: '2026'
...
---
_id: '62064'
abstract:
- lang: eng
text: SYCL is an open standard for targeting heterogeneous hardware from C++. In
this work, we evaluate a SYCL implementation for a discontinuous Galerkin discretization
of the 2D shallow water equations targeting CPUs, GPUs, and also FPGAs. The discretization
uses polynomial orders zero to two on unstructured triangular meshes. Separating
memory accesses from the numerical code allow us to optimize data accesses for
the target architecture. A performance analysis shows good portability across
x86 and ARM CPUs, GPUs from different vendors, and even two variants of Intel
Stratix 10 FPGAs. Measuring the energy to solution shows that GPUs yield an up
to 10x higher energy efficiency in terms of degrees of freedom per joule compared
to CPUs. With custom designed caches, FPGAs offer a meaningful complement to the
other architectures with particularly good computational performance on smaller
meshes. FPGAs with High Bandwidth Memory are less affected by bandwidth issues
and have similar energy efficiency as latest generation CPUs.
article_number: '772'
author:
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Analyzing performance
portability for a SYCL implementation of the 2D shallow water equations. The
Journal of Supercomputing. 2025;81(6). doi:10.1007/s11227-025-07063-7
apa: Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., & Aizinger,
V. (2025). Analyzing performance portability for a SYCL implementation of the
2D shallow water equations. The Journal of Supercomputing, 81(6),
Article 772. https://doi.org/10.1007/s11227-025-07063-7
bibtex: '@article{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2025, title={Analyzing
performance portability for a SYCL implementation of the 2D shallow water equations},
volume={81}, DOI={10.1007/s11227-025-07063-7},
number={6772}, journal={The Journal of Supercomputing}, publisher={Springer Science
and Business Media LLC}, author={Büttner, Markus and Alt, Christoph and Kenter,
Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym}, year={2025}
}'
chicago: Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian
Plessl, and Vadym Aizinger. “Analyzing Performance Portability for a SYCL Implementation
of the 2D Shallow Water Equations.” The Journal of Supercomputing 81, no.
6 (2025). https://doi.org/10.1007/s11227-025-07063-7.
ieee: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Analyzing
performance portability for a SYCL implementation of the 2D shallow water equations,”
The Journal of Supercomputing, vol. 81, no. 6, Art. no. 772, 2025, doi:
10.1007/s11227-025-07063-7.'
mla: Büttner, Markus, et al. “Analyzing Performance Portability for a SYCL Implementation
of the 2D Shallow Water Equations.” The Journal of Supercomputing, vol.
81, no. 6, 772, Springer Science and Business Media LLC, 2025, doi:10.1007/s11227-025-07063-7.
short: M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, The Journal
of Supercomputing 81 (2025).
date_created: 2025-11-04T09:37:50Z
date_updated: 2025-11-04T09:48:10Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/s11227-025-07063-7
intvolume: ' 81'
issue: '6'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
publication: The Journal of Supercomputing
publication_identifier:
issn:
- 1573-0484
publication_status: published
publisher: Springer Science and Business Media LLC
quality_controlled: '1'
status: public
title: Analyzing performance portability for a SYCL implementation of the 2D shallow
water equations
type: journal_article
user_id: '3145'
volume: 81
year: '2025'
...
---
_id: '62066'
abstract:
- lang: eng
text: In the context of high-performance computing (HPC) for distributed workloads,
individual field-programmable gate arrays (FPGAs) need efficient ways to exchange
data, which requires network infrastructure and software abstractions. Dedicated
multi-FPGA clusters provide inter-FPGA networks for direct device to device communication.
The oneAPI high-level synthesis toolchain offers I/O pipes to allow user kernels
to interact with the networking ports of the FPGA board. In this work, we evaluate
using oneAPI I/O pipes for direct FPGA-to-FPGA communication by scaling a SYCL
implementation of a Jacobi solver on up to 25 FPGAs in the Noctua 2 cluster. We
see good results in weak and strong scaling experiments.
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Alt C, Plessl C, Kenter T. Evaluating oneAPI I/O Pipes in a Case Study of
Scaling a SYCL Jacobi Solver to multiple FPGAs. In: Proceedings of the 13th
International Workshop on OpenCL and SYCL. IWOCL ’25. Association for Computing
Machinery; 2025. doi:10.1145/3731125.3731131'
apa: Alt, C., Plessl, C., & Kenter, T. (2025). Evaluating oneAPI I/O Pipes in
a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs. Proceedings
of the 13th International Workshop on OpenCL and SYCL. https://doi.org/10.1145/3731125.3731131
bibtex: '@inproceedings{Alt_Plessl_Kenter_2025, place={New York, NY, USA}, series={IWOCL
’25}, title={Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi
Solver to multiple FPGAs}, DOI={10.1145/3731125.3731131},
booktitle={Proceedings of the 13th International Workshop on OpenCL and SYCL},
publisher={Association for Computing Machinery}, author={Alt, Christoph and Plessl,
Christian and Kenter, Tobias}, year={2025}, collection={IWOCL ’25} }'
chicago: 'Alt, Christoph, Christian Plessl, and Tobias Kenter. “Evaluating OneAPI
I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to Multiple FPGAs.”
In Proceedings of the 13th International Workshop on OpenCL and SYCL. IWOCL
’25. New York, NY, USA: Association for Computing Machinery, 2025. https://doi.org/10.1145/3731125.3731131.'
ieee: 'C. Alt, C. Plessl, and T. Kenter, “Evaluating oneAPI I/O Pipes in a Case
Study of Scaling a SYCL Jacobi Solver to multiple FPGAs,” 2025, doi: 10.1145/3731125.3731131.'
mla: Alt, Christoph, et al. “Evaluating OneAPI I/O Pipes in a Case Study of Scaling
a SYCL Jacobi Solver to Multiple FPGAs.” Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, 2025, doi:10.1145/3731125.3731131.
short: 'C. Alt, C. Plessl, T. Kenter, in: Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, New York, NY,
USA, 2025.'
date_created: 2025-11-04T09:45:23Z
date_updated: 2025-11-04T09:47:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3731125.3731131
keyword:
- Multi-FPGA
- High-level Synthesis
- oneAPI
- FPGA
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 13th International Workshop on OpenCL and SYCL
publication_identifier:
isbn:
- '9798400713606'
publisher: Association for Computing Machinery
quality_controlled: '1'
series_title: IWOCL ’25
status: public
title: Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver
to multiple FPGAs
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '62065'
author:
- first_name: Shivam
full_name: Sundriyal, Shivam
last_name: Sundriyal
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Sundriyal S, Büttner M, Alt C, Kenter T, Aizinger V. Adaptive Spectral Block
Floating Point for Discontinuous Galerkin Methods. In: 2025 IEEE High Performance
Extreme Computing Conference (HPEC). IEEE; 2025. doi:10.1109/hpec67600.2025.11196195'
apa: Sundriyal, S., Büttner, M., Alt, C., Kenter, T., & Aizinger, V. (2025).
Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods. 2025
IEEE High Performance Extreme Computing Conference (HPEC). https://doi.org/10.1109/hpec67600.2025.11196195
bibtex: '@inproceedings{Sundriyal_Büttner_Alt_Kenter_Aizinger_2025, title={Adaptive
Spectral Block Floating Point for Discontinuous Galerkin Methods}, DOI={10.1109/hpec67600.2025.11196195},
booktitle={2025 IEEE High Performance Extreme Computing Conference (HPEC)}, publisher={IEEE},
author={Sundriyal, Shivam and Büttner, Markus and Alt, Christoph and Kenter, Tobias
and Aizinger, Vadym}, year={2025} }'
chicago: Sundriyal, Shivam, Markus Büttner, Christoph Alt, Tobias Kenter, and Vadym
Aizinger. “Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods.”
In 2025 IEEE High Performance Extreme Computing Conference (HPEC). IEEE,
2025. https://doi.org/10.1109/hpec67600.2025.11196195.
ieee: 'S. Sundriyal, M. Büttner, C. Alt, T. Kenter, and V. Aizinger, “Adaptive Spectral
Block Floating Point for Discontinuous Galerkin Methods,” 2025, doi: 10.1109/hpec67600.2025.11196195.'
mla: Sundriyal, Shivam, et al. “Adaptive Spectral Block Floating Point for Discontinuous
Galerkin Methods.” 2025 IEEE High Performance Extreme Computing Conference
(HPEC), IEEE, 2025, doi:10.1109/hpec67600.2025.11196195.
short: 'S. Sundriyal, M. Büttner, C. Alt, T. Kenter, V. Aizinger, in: 2025 IEEE
High Performance Extreme Computing Conference (HPEC), IEEE, 2025.'
date_created: 2025-11-04T09:43:18Z
date_updated: 2025-11-04T09:48:46Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/hpec67600.2025.11196195
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2025 IEEE High Performance Extreme Computing Conference (HPEC)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '65102'
abstract:
- lang: eng
text: 'Efficient graph processing is essential for a wide range of applications.
Scalability and memory access patterns are still a challenge, especially with
the Breadth-First Search algorithm. This work focuses on leveraging HPC systems
with multiple GPUs available in a single node with peer-to-peer functionality
of the Intel oneAPI implementation of SYCL. We propose three GPU-based load-balancing
methods: work-group localisation for efficient data access, even workload distribution
for higher GPU occupancy, and a hybrid strided-access approach for heuristic balancing.
These methods ensure performance, portability, and productivity with a unified
codebase. Our proposed methodologies outperform state-of-the-art single-GPU implementations
based on CUDA on synthetic RMAT graphs. We analysed BFS performance across NVIDIA
A100, Intel Max 1550, and AMD MI300X GPUs, achieving a peak performance of 153.27
GTEPS on an RMAT25-64 graph using 8 GPUs on the NVIDIA A100. Furthermore, our
work demonstrates the capability to handle RMAT graphs up to scale 29, achieving
superior performance on synthetic graphs and competitive results on real-world
datasets.'
author:
- first_name: Kaan
full_name: Olgu, Kaan
last_name: Olgu
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Jose
full_name: Nunez-Yanez, Jose
last_name: Nunez-Yanez
- first_name: Simon
full_name: McIntosh-Smith, Simon
last_name: McIntosh-Smith
- first_name: Tom
full_name: Deakin, Tom
last_name: Deakin
citation:
ama: 'Olgu K, Kenter T, Nunez-Yanez J, McIntosh-Smith S, Deakin T. Towards Efficient
Load Balancing BFS on GPUs: One Code for AMD, Intel & Nvidia. In: Proceedings
of the SC ’25 Workshops of the International Conference for High Performance Computing,
Networking, Storage and Analysis. ACM; 2025. doi:10.1145/3731599.3767570'
apa: 'Olgu, K., Kenter, T., Nunez-Yanez, J., McIntosh-Smith, S., & Deakin, T.
(2025). Towards Efficient Load Balancing BFS on GPUs: One Code for AMD, Intel
& Nvidia. Proceedings of the SC ’25 Workshops of the International Conference
for High Performance Computing, Networking, Storage and Analysis. https://doi.org/10.1145/3731599.3767570'
bibtex: '@inproceedings{Olgu_Kenter_Nunez-Yanez_McIntosh-Smith_Deakin_2025, title={Towards
Efficient Load Balancing BFS on GPUs: One Code for AMD, Intel & Nvidia}, DOI={10.1145/3731599.3767570}, booktitle={Proceedings
of the SC ’25 Workshops of the International Conference for High Performance Computing,
Networking, Storage and Analysis}, publisher={ACM}, author={Olgu, Kaan and Kenter,
Tobias and Nunez-Yanez, Jose and McIntosh-Smith, Simon and Deakin, Tom}, year={2025}
}'
chicago: 'Olgu, Kaan, Tobias Kenter, Jose Nunez-Yanez, Simon McIntosh-Smith, and
Tom Deakin. “Towards Efficient Load Balancing BFS on GPUs: One Code for AMD, Intel
& Nvidia.” In Proceedings of the SC ’25 Workshops of the International
Conference for High Performance Computing, Networking, Storage and Analysis.
ACM, 2025. https://doi.org/10.1145/3731599.3767570.'
ieee: 'K. Olgu, T. Kenter, J. Nunez-Yanez, S. McIntosh-Smith, and T. Deakin, “Towards
Efficient Load Balancing BFS on GPUs: One Code for AMD, Intel & Nvidia,” 2025,
doi: 10.1145/3731599.3767570.'
mla: 'Olgu, Kaan, et al. “Towards Efficient Load Balancing BFS on GPUs: One Code
for AMD, Intel & Nvidia.” Proceedings of the SC ’25 Workshops of the International
Conference for High Performance Computing, Networking, Storage and Analysis,
ACM, 2025, doi:10.1145/3731599.3767570.'
short: 'K. Olgu, T. Kenter, J. Nunez-Yanez, S. McIntosh-Smith, T. Deakin, in: Proceedings
of the SC ’25 Workshops of the International Conference for High Performance Computing,
Networking, Storage and Analysis, ACM, 2025.'
date_created: 2026-03-24T09:05:22Z
date_updated: 2026-03-24T09:06:33Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3731599.3767570
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the SC '25 Workshops of the International Conference for
High Performance Computing, Networking, Storage and Analysis
publication_status: published
publisher: ACM
status: public
title: 'Towards Efficient Load Balancing BFS on GPUs: One Code for AMD, Intel & Nvidia'
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '62981'
abstract:
- lang: eng
text: "Otus is a high-performance computing cluster that was launched in 2025 and
is operated by the Paderborn Center for Parallel Computing (PC2) at Paderborn
University in Germany. The system is part of the National High Performance Computing
(NHR) initiative. Otus complements the previous supercomputer Noctua 2, offering
approximately twice the computing power while retaining the three node types that
were characteristic of Noctua 2: 1) CPU compute nodes with different memory capacities,
2) high-end GPU nodes, and 3) HPC-grade FPGA nodes. On the Top500 list, which
ranks the 500 most powerful supercomputers in the world, Otus is in position 164
with the CPU partition and in position 255 with the GPU partition (June 2025).
On the Green500 list, ranking the 500 most energy-efficient supercomputers in
the world, Otus is in position 5 with the GPU partition (June 2025).\r\n\r\n\r\nThis
article provides a comprehensive overview of the system in terms of its hardware,
software, system integration, and its overall integration into the data center
building to ensure energy-efficient operation. The article aims to provide unique
insights for scientists using the system and for other centers operating HPC clusters.
The article will be continuously updated to reflect the latest system setup and
measurements. "
author:
- first_name: Sadaf
full_name: Ehtesabi, Sadaf
id: '116116'
last_name: Ehtesabi
- first_name: Manoar
full_name: Hossain, Manoar
id: '114619'
last_name: Hossain
orcid: https://orcid.org/0000-0002-0737-7981
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Andreas
full_name: Krawinkel, Andreas
id: '15275'
last_name: Krawinkel
- first_name: Lukas
full_name: Ostermann, Lukas
id: '69976'
last_name: Ostermann
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Stefan
full_name: Rohde, Stefan
id: '34009'
last_name: Rohde
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-5397
- first_name: Michael
full_name: Schwarz, Michael
id: '5312'
last_name: Schwarz
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
- first_name: Nils
full_name: Winnwa, Nils
id: '61189'
last_name: Winnwa
- first_name: Alex
full_name: Wiens, Alex
id: '23522'
last_name: Wiens
orcid: 0000-0003-1764-9773
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
citation:
ama: Ehtesabi S, Hossain M, Kenter T, et al. Otus Supercomputer. Vol 1. Paderborn
Center for Parallel Computing (PC2); 2025. doi:10.48550/ARXIV.2512.07401
apa: Ehtesabi, S., Hossain, M., Kenter, T., Krawinkel, A., Ostermann, L., Plessl,
C., Riebler, H., Rohde, S., Schade, R., Schwarz, M., Simon, J., Winnwa, N., Wiens,
A., & Wu, X. (2025). Otus Supercomputer (Vol. 1). Paderborn Center
for Parallel Computing (PC2). https://doi.org/10.48550/ARXIV.2512.07401
bibtex: '@book{Ehtesabi_Hossain_Kenter_Krawinkel_Ostermann_Plessl_Riebler_Rohde_Schade_Schwarz_et
al._2025, place={Paderborn}, series={PC2 Technical Report Series}, title={Otus
Supercomputer}, volume={1}, DOI={10.48550/ARXIV.2512.07401},
publisher={Paderborn Center for Parallel Computing (PC2)}, author={Ehtesabi, Sadaf
and Hossain, Manoar and Kenter, Tobias and Krawinkel, Andreas and Ostermann, Lukas
and Plessl, Christian and Riebler, Heinrich and Rohde, Stefan and Schade, Robert
and Schwarz, Michael and et al.}, year={2025}, collection={PC2 Technical Report
Series} }'
chicago: 'Ehtesabi, Sadaf, Manoar Hossain, Tobias Kenter, Andreas Krawinkel, Lukas
Ostermann, Christian Plessl, Heinrich Riebler, et al. Otus Supercomputer.
Vol. 1. PC2 Technical Report Series. Paderborn: Paderborn Center for Parallel
Computing (PC2), 2025. https://doi.org/10.48550/ARXIV.2512.07401.'
ieee: 'S. Ehtesabi et al., Otus Supercomputer, vol. 1. Paderborn:
Paderborn Center for Parallel Computing (PC2), 2025.'
mla: Ehtesabi, Sadaf, et al. Otus Supercomputer. Paderborn Center for Parallel
Computing (PC2), 2025, doi:10.48550/ARXIV.2512.07401.
short: S. Ehtesabi, M. Hossain, T. Kenter, A. Krawinkel, L. Ostermann, C. Plessl,
H. Riebler, S. Rohde, R. Schade, M. Schwarz, J. Simon, N. Winnwa, A. Wiens, X.
Wu, Otus Supercomputer, Paderborn Center for Parallel Computing (PC2), Paderborn,
2025.
date_created: 2025-12-09T09:11:04Z
date_updated: 2026-03-25T11:50:31Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: 10.48550/ARXIV.2512.07401
file:
- access_level: open_access
content_type: application/pdf
creator: deffel
date_created: 2025-12-09T09:19:12Z
date_updated: 2026-03-25T11:50:30Z
file_id: '62982'
file_name: 2512.07401v1.pdf
file_size: 4535595
relation: main_file
file_date_updated: 2026-03-25T11:50:30Z
has_accepted_license: '1'
intvolume: ' 1'
keyword:
- Otus
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
- Noctua 2
- HPC
language:
- iso: eng
oa: '1'
page: '33'
place: Paderborn
publication_status: published
publisher: Paderborn Center for Parallel Computing (PC2)
report_number: PC2TR-2025-1
series_title: PC2 Technical Report Series
status: public
title: Otus Supercomputer
type: report
user_id: '23522'
volume: 1
year: '2025'
...
---
_id: '53474'
abstract:
- lang: eng
text: We present a novel approach to characterize and quantify microheterogeneity
and microphase separation in computer simulations of complex liquid mixtures.
Our post-processing method is based on local density fluctuations of the different
constituents in sampling spheres of varying size. It can be easily applied to
both molecular dynamics (MD) and Monte Carlo (MC) simulations, including periodic
boundary conditions. Multidimensional correlation of the density distributions
yields a clear picture of the domain formation due to the subtle balance of different
interactions. We apply our approach to the example of force field molecular dynamics
simulations of imidazolium-based ionic liquids with different side chain lengths
at different temperatures, namely 1-ethyl-3-methylimidazolium chloride, 1-hexyl-3-methylimidazolium
chloride, and 1-decyl-3-methylimidazolium chloride, which are known to form distinct
liquid domains. We put the results into the context of existing microheterogeneity
analyses and demonstrate the advantages and sensitivity of our novel method. Furthermore,
we show how to estimate the configuration entropy from our analysis, and we investigate
voids in the system. The analysis has been implemented into our program package
TRAVIS and is thus available as free software.
article_number: '322'
author:
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Martin
full_name: Brehm, Martin
id: '100167'
last_name: Brehm
citation:
ama: Lass M, Kenter T, Plessl C, Brehm M. Characterizing Microheterogeneity in Liquid
Mixtures via Local Density Fluctuations. Entropy. 2024;26(4). doi:10.3390/e26040322
apa: Lass, M., Kenter, T., Plessl, C., & Brehm, M. (2024). Characterizing Microheterogeneity
in Liquid Mixtures via Local Density Fluctuations. Entropy, 26(4),
Article 322. https://doi.org/10.3390/e26040322
bibtex: '@article{Lass_Kenter_Plessl_Brehm_2024, title={Characterizing Microheterogeneity
in Liquid Mixtures via Local Density Fluctuations}, volume={26}, DOI={10.3390/e26040322},
number={4322}, journal={Entropy}, publisher={MDPI AG}, author={Lass, Michael and
Kenter, Tobias and Plessl, Christian and Brehm, Martin}, year={2024} }'
chicago: Lass, Michael, Tobias Kenter, Christian Plessl, and Martin Brehm. “Characterizing
Microheterogeneity in Liquid Mixtures via Local Density Fluctuations.” Entropy
26, no. 4 (2024). https://doi.org/10.3390/e26040322.
ieee: 'M. Lass, T. Kenter, C. Plessl, and M. Brehm, “Characterizing Microheterogeneity
in Liquid Mixtures via Local Density Fluctuations,” Entropy, vol. 26, no.
4, Art. no. 322, 2024, doi: 10.3390/e26040322.'
mla: Lass, Michael, et al. “Characterizing Microheterogeneity in Liquid Mixtures
via Local Density Fluctuations.” Entropy, vol. 26, no. 4, 322, MDPI AG,
2024, doi:10.3390/e26040322.
short: M. Lass, T. Kenter, C. Plessl, M. Brehm, Entropy 26 (2024).
date_created: 2024-04-12T18:31:39Z
date_updated: 2024-04-12T18:34:32Z
department:
- _id: '27'
- _id: '518'
- _id: '803'
doi: 10.3390/e26040322
intvolume: ' 26'
issue: '4'
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Entropy
publication_identifier:
issn:
- 1099-4300
publication_status: published
publisher: MDPI AG
status: public
title: Characterizing Microheterogeneity in Liquid Mixtures via Local Density Fluctuations
type: journal_article
user_id: '24135'
volume: 26
year: '2024'
...
---
_id: '53663'
abstract:
- lang: eng
text: 'Noctua 2 is a supercomputer operated at the Paderborn Center for Parallel
Computing (PC2) at Paderborn University in Germany. Noctua 2 was inaugurated in
2022 and is an Atos BullSequana XH2000 system. It consists mainly of three node
types: 1) CPU Compute nodes with AMD EPYC processors in different main memory
configurations, 2) GPU nodes with NVIDIA A100 GPUs, and 3) FPGA nodes with Xilinx
Alveo U280 and Intel Stratix 10 FPGA cards. While CPUs and GPUs are known off-the-shelf
components in HPC systems, the operation of a large number of FPGA cards from
different vendors and a dedicated FPGA-to-FPGA network are unique characteristics
of Noctua 2. This paper describes in detail the overall setup of Noctua 2 and
gives insights into the operation of the cluster from a hardware, software and
facility perspective.'
article_type: original
author:
- first_name: Carsten
full_name: Bauer, Carsten
id: '90082'
last_name: Bauer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Lukas
full_name: Mazur, Lukas
id: '90492'
last_name: Mazur
orcid: ' 0000-0001-6304-7082'
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Holger
full_name: Nitsche, Holger
id: '15272'
last_name: Nitsche
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-5397
- first_name: Michael
full_name: Schwarz, Michael
id: '5312'
last_name: Schwarz
- first_name: Nils
full_name: Winnwa, Nils
id: '61189'
last_name: Winnwa
- first_name: Alex
full_name: Wiens, Alex
id: '23522'
last_name: Wiens
orcid: 0000-0003-1764-9773
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
citation:
ama: Bauer C, Kenter T, Lass M, et al. Noctua 2 Supercomputer. Journal of large-scale
research facilities. 2024;9. doi:10.17815/jlsrf-8-187
apa: Bauer, C., Kenter, T., Lass, M., Mazur, L., Meyer, M., Nitsche, H., Riebler,
H., Schade, R., Schwarz, M., Winnwa, N., Wiens, A., Wu, X., Plessl, C., &
Simon, J. (2024). Noctua 2 Supercomputer. Journal of Large-Scale Research Facilities,
9. https://doi.org/10.17815/jlsrf-8-187
bibtex: '@article{Bauer_Kenter_Lass_Mazur_Meyer_Nitsche_Riebler_Schade_Schwarz_Winnwa_et
al._2024, title={Noctua 2 Supercomputer}, volume={9}, DOI={10.17815/jlsrf-8-187 }, journal={Journal of large-scale research facilities},
author={Bauer, Carsten and Kenter, Tobias and Lass, Michael and Mazur, Lukas and
Meyer, Marius and Nitsche, Holger and Riebler, Heinrich and Schade, Robert and
Schwarz, Michael and Winnwa, Nils and et al.}, year={2024} }'
chicago: Bauer, Carsten, Tobias Kenter, Michael Lass, Lukas Mazur, Marius Meyer,
Holger Nitsche, Heinrich Riebler, et al. “Noctua 2 Supercomputer.” Journal
of Large-Scale Research Facilities 9 (2024). https://doi.org/10.17815/jlsrf-8-187 .
ieee: 'C. Bauer et al., “Noctua 2 Supercomputer,” Journal of large-scale
research facilities, vol. 9, 2024, doi: 10.17815/jlsrf-8-187 .'
mla: Bauer, Carsten, et al. “Noctua 2 Supercomputer.” Journal of Large-Scale
Research Facilities, vol. 9, 2024, doi:10.17815/jlsrf-8-187 .
short: C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler,
R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal
of Large-Scale Research Facilities 9 (2024).
date_created: 2024-04-26T07:39:41Z
date_updated: 2024-04-26T08:44:30Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: '10.17815/jlsrf-8-187 '
file:
- access_level: open_access
content_type: application/pdf
creator: deffel
date_created: 2024-04-26T07:30:20Z
date_updated: 2024-04-26T08:35:17Z
file_id: '53664'
file_name: Noctua2_Supercomputer.pdf
file_size: 3825480
relation: main_file
file_date_updated: 2024-04-26T08:35:17Z
has_accepted_license: '1'
intvolume: ' 9'
keyword:
- Noctua 2
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
language:
- iso: eng
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Journal of large-scale research facilities
publication_status: published
status: public
title: Noctua 2 Supercomputer
type: journal_article
user_id: '8961'
volume: 9
year: '2024'
...
---
_id: '56605'
author:
- first_name: Jan-Oliver
full_name: Opdenhövel, Jan-Oliver
id: '73960'
last_name: Opdenhövel
orcid: 0000-0003-2314-2784
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Opdenhövel J-O, Alt C, Plessl C, Kenter T. StencilStream: A SYCL-based Stencil
Simulation Framework Targeting FPGAs. In: 2024 34th International Conference
on Field-Programmable Logic and Applications (FPL). IEEE; 2024. doi:10.1109/fpl64840.2024.00023'
apa: 'Opdenhövel, J.-O., Alt, C., Plessl, C., & Kenter, T. (2024). StencilStream:
A SYCL-based Stencil Simulation Framework Targeting FPGAs. 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL). https://doi.org/10.1109/fpl64840.2024.00023'
bibtex: '@inproceedings{Opdenhövel_Alt_Plessl_Kenter_2024, title={StencilStream:
A SYCL-based Stencil Simulation Framework Targeting FPGAs}, DOI={10.1109/fpl64840.2024.00023},
booktitle={2024 34th International Conference on Field-Programmable Logic and
Applications (FPL)}, publisher={IEEE}, author={Opdenhövel, Jan-Oliver and Alt,
Christoph and Plessl, Christian and Kenter, Tobias}, year={2024} }'
chicago: 'Opdenhövel, Jan-Oliver, Christoph Alt, Christian Plessl, and Tobias Kenter.
“StencilStream: A SYCL-Based Stencil Simulation Framework Targeting FPGAs.” In
2024 34th International Conference on Field-Programmable Logic and Applications
(FPL). IEEE, 2024. https://doi.org/10.1109/fpl64840.2024.00023.'
ieee: 'J.-O. Opdenhövel, C. Alt, C. Plessl, and T. Kenter, “StencilStream: A SYCL-based
Stencil Simulation Framework Targeting FPGAs,” 2024, doi: 10.1109/fpl64840.2024.00023.'
mla: 'Opdenhövel, Jan-Oliver, et al. “StencilStream: A SYCL-Based Stencil Simulation
Framework Targeting FPGAs.” 2024 34th International Conference on Field-Programmable
Logic and Applications (FPL), IEEE, 2024, doi:10.1109/fpl64840.2024.00023.'
short: 'J.-O. Opdenhövel, C. Alt, C. Plessl, T. Kenter, in: 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024.'
date_created: 2024-10-14T07:49:24Z
date_updated: 2024-10-14T07:56:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/fpl64840.2024.00023
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2024 34th International Conference on Field-Programmable Logic and Applications
(FPL)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs'
type: conference
user_id: '3145'
year: '2024'
...
---
_id: '56607'
author:
- first_name: Abdul Rehman
full_name: Tareen, Abdul Rehman
id: '76938'
last_name: Tareen
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Tareen AR, Meyer M, Plessl C, Kenter T. HiHiSpMV: Sparse Matrix Vector Multiplication
with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. In: 2024
IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing
Machines (FCCM). Vol 35. IEEE; 2024. doi:10.1109/fccm60383.2024.00014'
apa: 'Tareen, A. R., Meyer, M., Plessl, C., & Kenter, T. (2024). HiHiSpMV: Sparse
Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High
Bandwidth Memory. 2024 IEEE 32nd Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM), 35. https://doi.org/10.1109/fccm60383.2024.00014'
bibtex: '@inproceedings{Tareen_Meyer_Plessl_Kenter_2024, title={HiHiSpMV: Sparse
Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High
Bandwidth Memory}, volume={35}, DOI={10.1109/fccm60383.2024.00014},
booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Tareen, Abdul Rehman
and Meyer, Marius and Plessl, Christian and Kenter, Tobias}, year={2024} }'
chicago: 'Tareen, Abdul Rehman, Marius Meyer, Christian Plessl, and Tobias Kenter.
“HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions
on FPGAs with High Bandwidth Memory.” In 2024 IEEE 32nd Annual International
Symposium on Field-Programmable Custom Computing Machines (FCCM), Vol. 35.
IEEE, 2024. https://doi.org/10.1109/fccm60383.2024.00014.'
ieee: 'A. R. Tareen, M. Meyer, C. Plessl, and T. Kenter, “HiHiSpMV: Sparse Matrix
Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth
Memory,” in 2024 IEEE 32nd Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM), 2024, vol. 35, doi: 10.1109/fccm60383.2024.00014.'
mla: 'Tareen, Abdul Rehman, et al. “HiHiSpMV: Sparse Matrix Vector Multiplication
with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.” 2024
IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing
Machines (FCCM), vol. 35, IEEE, 2024, doi:10.1109/fccm60383.2024.00014.'
short: 'A.R. Tareen, M. Meyer, C. Plessl, T. Kenter, in: 2024 IEEE 32nd Annual International
Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2024.'
date_created: 2024-10-14T07:59:08Z
date_updated: 2024-10-14T12:27:55Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/fccm60383.2024.00014
intvolume: ' 35'
language:
- iso: eng
publication: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom
Computing Machines (FCCM)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions
on FPGAs with High Bandwidth Memory'
type: conference
user_id: '3145'
volume: 35
year: '2024'
...
---
_id: '54312'
article_number: '11'
author:
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Enabling Performance
Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL. In:
Proceedings of the Platform for Advanced Scientific Computing Conference (PASC).
ACM; 2024. doi:10.1145/3659914.3659925'
apa: Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., & Aizinger,
V. (2024). Enabling Performance Portability for Shallow Water Equations on CPUs,
GPUs, and FPGAs with SYCL. Proceedings of the Platform for Advanced Scientific
Computing Conference (PASC), Article 11. https://doi.org/10.1145/3659914.3659925
bibtex: '@inproceedings{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2024, title={Enabling
Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with
SYCL}, DOI={10.1145/3659914.3659925},
number={11}, booktitle={Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC)}, publisher={ACM}, author={Büttner, Markus and Alt, Christoph
and Kenter, Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym},
year={2024} }'
chicago: Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian
Plessl, and Vadym Aizinger. “Enabling Performance Portability for Shallow Water
Equations on CPUs, GPUs, and FPGAs with SYCL.” In Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC). ACM, 2024. https://doi.org/10.1145/3659914.3659925.
ieee: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Enabling
Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with
SYCL,” 2024, doi: 10.1145/3659914.3659925.'
mla: Büttner, Markus, et al. “Enabling Performance Portability for Shallow Water
Equations on CPUs, GPUs, and FPGAs with SYCL.” Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC), 11, ACM, 2024, doi:10.1145/3659914.3659925.
short: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, in: Proceedings
of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2024.'
date_created: 2024-05-16T13:24:49Z
date_updated: 2024-11-27T22:50:19Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3659914.3659925
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs,
and FPGAs with SYCL
type: conference
user_id: '16153'
year: '2024'
...
---
_id: '62067'
abstract:
- lang: eng
text: Most FPGA boards in the HPC domain are well-suited for parallel scaling because
of the direct integration of versatile and high-throughput network ports. However,
the utilization of their network capabilities is often challenging and error-prone
because the whole network stack and communication patterns have to be implemented
and managed on the FPGAs. Also, this approach conceptually involves a trade-off
between the performance potential of improved communication and the impact of
resource consumption for communication infrastructure, since the utilized resources
on the FPGAs could otherwise be used for computations. In this work, we investigate
this trade-off, firstly, by using synthetic benchmarks to evaluate the different
configuration options of the communication framework ACCL and their impact on
communication latency and throughput. Finally, we use our findings to implement
a shallow water simulation whose scalability heavily depends on low-latency communication.
With a suitable configuration of ACCL, good scaling behavior can be shown to all
48 FPGAs installed in the system. Overall, the results show that the availability
of inter-FPGA communication frameworks as well as the configurability of framework and
network stack are crucial to achieve the best application performance with low
latency communication.
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Lucian
full_name: Petrica, Lucian
last_name: Petrica
- first_name: Kenneth
full_name: O’Brien, Kenneth
last_name: O’Brien
- first_name: Michaela
full_name: Blott, Michaela
last_name: Blott
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Meyer M, Kenter T, Petrica L, O’Brien K, Blott M, Plessl C. Optimizing Communication
for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. In: Lecture
Notes in Computer Science. Springer Nature Switzerland; 2024. doi:10.1007/978-3-031-69766-1_9'
apa: Meyer, M., Kenter, T., Petrica, L., O’Brien, K., Blott, M., & Plessl, C.
(2024). Optimizing Communication for Latency Sensitive HPC Applications on up
to 48 FPGAs Using ACCL. In Lecture Notes in Computer Science. Springer
Nature Switzerland. https://doi.org/10.1007/978-3-031-69766-1_9
bibtex: '@inbook{Meyer_Kenter_Petrica_O’Brien_Blott_Plessl_2024, place={Cham}, title={Optimizing
Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL},
DOI={10.1007/978-3-031-69766-1_9},
booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
author={Meyer, Marius and Kenter, Tobias and Petrica, Lucian and O’Brien, Kenneth
and Blott, Michaela and Plessl, Christian}, year={2024} }'
chicago: 'Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela
Blott, and Christian Plessl. “Optimizing Communication for Latency Sensitive HPC
Applications on up to 48 FPGAs Using ACCL.” In Lecture Notes in Computer Science.
Cham: Springer Nature Switzerland, 2024. https://doi.org/10.1007/978-3-031-69766-1_9.'
ieee: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, and C. Plessl, “Optimizing
Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL,”
in Lecture Notes in Computer Science, Cham: Springer Nature Switzerland,
2024.'
mla: Meyer, Marius, et al. “Optimizing Communication for Latency Sensitive HPC Applications
on up to 48 FPGAs Using ACCL.” Lecture Notes in Computer Science, Springer
Nature Switzerland, 2024, doi:10.1007/978-3-031-69766-1_9.
short: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, in: Lecture
Notes in Computer Science, Springer Nature Switzerland, Cham, 2024.'
date_created: 2025-11-04T09:50:24Z
date_updated: 2025-11-04T09:51:22Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-69766-1_9
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Cham
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Lecture Notes in Computer Science
publication_identifier:
isbn:
- '9783031697654'
- '9783031697661'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: Optimizing Communication for Latency Sensitive HPC Applications on up to 48
FPGAs Using ACCL
type: book_chapter
user_id: '3145'
year: '2024'
...
---
_id: '56604'
abstract:
- lang: eng
text: This manuscript makes the claim of having computed the 9th Dedekind number,
D(9). This was done by accelerating the core operation of the process with an
efficient FPGA design that outperforms an optimized 64-core CPU reference by 95x.
The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn
University. The resulting value for D(9) is 286386577668298411128469151667598498812366.
This value can be verified in two steps. We have made the data file containing
the 490 M results available, each of which can be verified separately on CPU,
and the whole file sums to our proposed value. The paper explains the mathematical
approach in the first part, before putting the focus on a deep dive into the FPGA
accelerator implementation followed by a performance analysis. The FPGA implementation
was done in Register-Transfer Level using a dual-clock architecture and shows
how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800
FPGAs. The total compute time used was 47,000 FPGA hours.
author:
- first_name: Lennart
full_name: Van Hirtum, Lennart
id: '100210'
last_name: Van Hirtum
- first_name: Patrick
full_name: De Causmaecker, Patrick
last_name: De Causmaecker
- first_name: Jens
full_name: Goemaere, Jens
last_name: Goemaere
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Van Hirtum L, De Causmaecker P, Goemaere J, et al. A Computation of the Ninth
Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable
Technology and Systems. 2024;17(3):1-28. doi:10.1145/3674147
apa: Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H.,
Lass, M., & Plessl, C. (2024). A Computation of the Ninth Dedekind Number
Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and
Systems, 17(3), 1–28. https://doi.org/10.1145/3674147
bibtex: '@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2024,
title={A Computation of the Ninth Dedekind Number Using FPGA Supercomputing},
volume={17}, DOI={10.1145/3674147},
number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems},
publisher={Association for Computing Machinery (ACM)}, author={Van Hirtum, Lennart
and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler,
Heinrich and Lass, Michael and Plessl, Christian}, year={2024}, pages={1–28} }'
chicago: 'Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter,
Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of the Ninth
Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable
Technology and Systems 17, no. 3 (2024): 1–28. https://doi.org/10.1145/3674147.'
ieee: 'L. Van Hirtum et al., “A Computation of the Ninth Dedekind Number
Using FPGA Supercomputing,” ACM Transactions on Reconfigurable Technology and
Systems, vol. 17, no. 3, pp. 1–28, 2024, doi: 10.1145/3674147.'
mla: Van Hirtum, Lennart, et al. “A Computation of the Ninth Dedekind Number Using
FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems,
vol. 17, no. 3, Association for Computing Machinery (ACM), 2024, pp. 1–28, doi:10.1145/3674147.
short: L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M.
Lass, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems 17
(2024) 1–28.
date_created: 2024-10-14T07:38:29Z
date_updated: 2025-11-04T09:53:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3674147
intvolume: ' 17'
issue: '3'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
page: 1-28
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: A Computation of the Ninth Dedekind Number Using FPGA Supercomputing
type: journal_article
user_id: '3145'
volume: 17
year: '2024'
...
---
_id: '53503'
author:
- first_name: Kaan
full_name: Olgu, Kaan
last_name: Olgu
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Jose
full_name: Nunez-Yanez, Jose
last_name: Nunez-Yanez
- first_name: Simon
full_name: Mcintosh-Smith, Simon
last_name: Mcintosh-Smith
citation:
ama: 'Olgu K, Kenter T, Nunez-Yanez J, Mcintosh-Smith S. Optimisation and Evaluation
of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms
to Describing Architectures. In: Proceedings of the 12th International Workshop
on OpenCL and SYCL. ACM; 2024. doi:10.1145/3648115.3648134'
apa: 'Olgu, K., Kenter, T., Nunez-Yanez, J., & Mcintosh-Smith, S. (2024). Optimisation
and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing
Algorithms to Describing Architectures. Proceedings of the 12th International
Workshop on OpenCL and SYCL. https://doi.org/10.1145/3648115.3648134'
bibtex: '@inproceedings{Olgu_Kenter_Nunez-Yanez_Mcintosh-Smith_2024, title={Optimisation
and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing
Algorithms to Describing Architectures}, DOI={10.1145/3648115.3648134},
booktitle={Proceedings of the 12th International Workshop on OpenCL and SYCL},
publisher={ACM}, author={Olgu, Kaan and Kenter, Tobias and Nunez-Yanez, Jose and
Mcintosh-Smith, Simon}, year={2024} }'
chicago: 'Olgu, Kaan, Tobias Kenter, Jose Nunez-Yanez, and Simon Mcintosh-Smith.
“Optimisation and Evaluation of Breadth First Search with OneAPI/SYCL on Intel
FPGAs: From Describing Algorithms to Describing Architectures.” In Proceedings
of the 12th International Workshop on OpenCL and SYCL. ACM, 2024. https://doi.org/10.1145/3648115.3648134.'
ieee: 'K. Olgu, T. Kenter, J. Nunez-Yanez, and S. Mcintosh-Smith, “Optimisation
and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing
Algorithms to Describing Architectures,” 2024, doi: 10.1145/3648115.3648134.'
mla: 'Olgu, Kaan, et al. “Optimisation and Evaluation of Breadth First Search with
OneAPI/SYCL on Intel FPGAs: From Describing Algorithms to Describing Architectures.”
Proceedings of the 12th International Workshop on OpenCL and SYCL, ACM,
2024, doi:10.1145/3648115.3648134.'
short: 'K. Olgu, T. Kenter, J. Nunez-Yanez, S. Mcintosh-Smith, in: Proceedings of
the 12th International Workshop on OpenCL and SYCL, ACM, 2024.'
date_created: 2024-04-15T07:41:21Z
date_updated: 2025-11-04T09:53:59Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3648115.3648134
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the 12th International Workshop on OpenCL and SYCL
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: 'Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel
FPGAs: from Describing Algorithms to Describing Architectures'
type: conference
user_id: '3145'
year: '2024'
...
---
_id: '43439'
abstract:
- lang: eng
text: "This preprint makes the claim of having computed the $9^{th}$ Dedekind\r\nNumber.
This was done by building an efficient FPGA Accelerator for the core\r\noperation
of the process, and parallelizing it on the Noctua 2 Supercluster at\r\nPaderborn
University. The resulting value is\r\n286386577668298411128469151667598498812366.
This value can be verified in two\r\nsteps. We have made the data file containing
the 490M results available, each\r\nof which can be verified separately on CPU,
and the whole file sums to our\r\nproposed value."
author:
- first_name: Lennart
full_name: Van Hirtum, Lennart
last_name: Van Hirtum
- first_name: Patrick
full_name: De Causmaecker, Patrick
last_name: De Causmaecker
- first_name: Jens
full_name: Goemaere, Jens
last_name: Goemaere
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using
FPGA Supercomputing. arXiv:230403039. Published online 2023.
apa: Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H.,
Lass, M., & Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing.
In arXiv:2304.03039.
bibtex: '@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2023,
title={A computation of D(9) using FPGA Supercomputing}, journal={arXiv:2304.03039},
author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and
Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian},
year={2023} }'
chicago: Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter,
Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of D(9) Using
FPGA Supercomputing.” ArXiv:2304.03039, 2023.
ieee: L. Van Hirtum et al., “A computation of D(9) using FPGA Supercomputing,”
arXiv:2304.03039. 2023.
mla: Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.”
ArXiv:2304.03039, 2023.
short: L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M.
Lass, C. Plessl, ArXiv:2304.03039 (2023).
date_created: 2023-04-08T11:05:29Z
date_updated: 2024-01-22T09:56:42Z
department:
- _id: '27'
- _id: '518'
external_id:
arxiv:
- '2304.03039'
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: arXiv:2304.03039
status: public
title: A computation of D(9) using FPGA Supercomputing
type: preprint
user_id: '3145'
year: '2023'
...
---
_id: '46188'
author:
- first_name: Jennifer
full_name: Faj, Jennifer
id: '78722'
last_name: Faj
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Sara
full_name: Faghih-Naini, Sara
last_name: Faghih-Naini
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Faj J, Kenter T, Faghih-Naini S, Plessl C, Aizinger V. Scalable Multi-FPGA
Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.
In: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC). ACM; 2023. doi:10.1145/3592979.3593407'
apa: Faj, J., Kenter, T., Faghih-Naini, S., Plessl, C., & Aizinger, V. (2023).
Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on
Unstructured Meshes. Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC). https://doi.org/10.1145/3592979.3593407
bibtex: '@inproceedings{Faj_Kenter_Faghih-Naini_Plessl_Aizinger_2023, title={Scalable
Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured
Meshes}, DOI={10.1145/3592979.3593407},
booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)}, publisher={ACM}, author={Faj, Jennifer and Kenter, Tobias and Faghih-Naini,
Sara and Plessl, Christian and Aizinger, Vadym}, year={2023} }'
chicago: Faj, Jennifer, Tobias Kenter, Sara Faghih-Naini, Christian Plessl, and
Vadym Aizinger. “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water
Model on Unstructured Meshes.” In Proceedings of the Platform for Advanced
Scientific Computing Conference (PASC). ACM, 2023. https://doi.org/10.1145/3592979.3593407.
ieee: 'J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, and V. Aizinger, “Scalable
Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured
Meshes,” 2023, doi: 10.1145/3592979.3593407.'
mla: Faj, Jennifer, et al. “Scalable Multi-FPGA Design of a Discontinuous Galerkin
Shallow-Water Model on Unstructured Meshes.” Proceedings of the Platform for
Advanced Scientific Computing Conference (PASC), ACM, 2023, doi:10.1145/3592979.3593407.
short: 'J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, V. Aizinger, in: Proceedings
of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2023.'
date_created: 2023-07-28T09:42:14Z
date_updated: 2024-04-17T08:09:39Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3592979.3593407
language:
- iso: eng
main_file_link:
- url: https://dl.acm.org/doi/pdf/10.1145/3592979.3593407
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
related_material:
link:
- description: Open Access available via this link.
relation: other
url: https://www.sighpc.org/for-our-community/acm-open-tocs/pasc23-open-toc
status: public
title: Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model
on Unstructured Meshes
type: conference
user_id: '3145'
year: '2023'
...
---
_id: '46189'
author:
- first_name: Charles
full_name: Prouveur, Charles
last_name: Prouveur
- first_name: Matthieu
full_name: Haefele, Matthieu
last_name: Haefele
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Nils
full_name: Voss, Nils
last_name: Voss
citation:
ama: 'Prouveur C, Haefele M, Kenter T, Voss N. FPGA Acceleration for HPC Supercapacitor
Simulations. In: Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC). ACM; 2023. doi:10.1145/3592979.3593419'
apa: Prouveur, C., Haefele, M., Kenter, T., & Voss, N. (2023). FPGA Acceleration
for HPC Supercapacitor Simulations. Proceedings of the Platform for Advanced
Scientific Computing Conference (PASC). https://doi.org/10.1145/3592979.3593419
bibtex: '@inproceedings{Prouveur_Haefele_Kenter_Voss_2023, title={FPGA Acceleration
for HPC Supercapacitor Simulations}, DOI={10.1145/3592979.3593419},
booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)}, publisher={ACM}, author={Prouveur, Charles and Haefele, Matthieu and
Kenter, Tobias and Voss, Nils}, year={2023} }'
chicago: Prouveur, Charles, Matthieu Haefele, Tobias Kenter, and Nils Voss. “FPGA
Acceleration for HPC Supercapacitor Simulations.” In Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC). ACM, 2023. https://doi.org/10.1145/3592979.3593419.
ieee: 'C. Prouveur, M. Haefele, T. Kenter, and N. Voss, “FPGA Acceleration for HPC
Supercapacitor Simulations,” 2023, doi: 10.1145/3592979.3593419.'
mla: Prouveur, Charles, et al. “FPGA Acceleration for HPC Supercapacitor Simulations.”
Proceedings of the Platform for Advanced Scientific Computing Conference (PASC),
ACM, 2023, doi:10.1145/3592979.3593419.
short: 'C. Prouveur, M. Haefele, T. Kenter, N. Voss, in: Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC), ACM, 2023.'
date_created: 2023-07-28T09:46:25Z
date_updated: 2024-04-17T08:10:51Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3592979.3593419
language:
- iso: eng
main_file_link:
- url: https://dl.acm.org/doi/pdf/10.1145/3592979.3593419
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
related_material:
link:
- description: Open Access available via this link.
relation: other
url: ' https://www.sighpc.org/for-our-community/acm-open-tocs/pasc23-open-toc '
status: public
title: FPGA Acceleration for HPC Supercapacitor Simulations
type: conference
user_id: '3145'
year: '2023'
...
---
_id: '45893'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Hansmeier T, Kenter T, Meyer M, Riebler H, Platzner M, Plessl C. Compute Centers
I: Heterogeneous Execution Environments. In: Haake C-J, Meyer auf der Heide F,
Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly Computing -- Individualized
IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf
Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:165-182. doi:10.5281/zenodo.8068642'
apa: 'Hansmeier, T., Kenter, T., Meyer, M., Riebler, H., Platzner, M., & Plessl,
C. (2023). Compute Centers I: Heterogeneous Execution Environments. In C.-J. Haake,
F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, & H. Wehrheim (Eds.), On-The-Fly
Computing -- Individualized IT-services in dynamic markets (Vol. 412, pp.
165–182). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.5281/zenodo.8068642'
bibtex: '@inbook{Hansmeier_Kenter_Meyer_Riebler_Platzner_Plessl_2023, place={Paderborn},
series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Compute Centers
I: Heterogeneous Execution Environments}, volume={412}, DOI={10.5281/zenodo.8068642},
booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets},
publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Hansmeier,
Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco
and Plessl, Christian}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm
and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023},
pages={165–182}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts}
}'
chicago: 'Hansmeier, Tim, Tobias Kenter, Marius Meyer, Heinrich Riebler, Marco Platzner,
and Christian Plessl. “Compute Centers I: Heterogeneous Execution Environments.”
In On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets,
edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning
Wachsmuth, and Heike Wehrheim, 412:165–82. Verlagsschriftenreihe Des Heinz Nixdorf
Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. https://doi.org/10.5281/zenodo.8068642.'
ieee: 'T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, and C. Plessl,
“Compute Centers I: Heterogeneous Execution Environments,” in On-The-Fly Computing
-- Individualized IT-services in dynamic markets, vol. 412, C.-J. Haake, F.
Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn:
Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–182.'
mla: 'Hansmeier, Tim, et al. “Compute Centers I: Heterogeneous Execution Environments.”
On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets,
edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität
Paderborn, 2023, pp. 165–82, doi:10.5281/zenodo.8068642.'
short: 'T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in:
C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.),
On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf
Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.'
date_created: 2023-07-07T08:15:45Z
date_updated: 2024-05-02T10:33:00Z
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doi: 10.5281/zenodo.8068642
editor:
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full_name: Haake, Claus-Jochen
last_name: Haake
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
last_name: Meyer auf der Heide
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
- first_name: Henning
full_name: Wachsmuth, Henning
last_name: Wachsmuth
- first_name: Heike
full_name: Wehrheim, Heike
last_name: Wehrheim
file:
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creator: florida
date_created: 2023-07-07T08:15:35Z
date_updated: 2023-07-07T11:17:33Z
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file_size: 2288788
relation: main_file
file_date_updated: 2023-07-07T11:17:33Z
has_accepted_license: '1'
intvolume: ' 412'
language:
- iso: eng
oa: '1'
page: 165-182
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
grant_number: '160364472'
name: 'SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen
(Subproject C2)'
publication: On-The-Fly Computing -- Individualized IT-services in dynamic markets
publisher: Heinz Nixdorf Institut, Universität Paderborn
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts
status: public
title: 'Compute Centers I: Heterogeneous Execution Environments'
type: book_chapter
user_id: '398'
volume: 412
year: '2023'
...
---
_id: '38041'
abstract:
- lang: eng
text: "While FPGA accelerator boards and their respective high-level design
tools are maturing, there is still a lack of multi-FPGA applications, libraries,
and not least, benchmarks and reference implementations towards sustained HPC
usage of these devices. As in the early days of GPUs in HPC, for workloads that
can reasonably be decoupled into loosely coupled working sets, multi-accelerator
support can be achieved by using standard communication interfaces like MPI on
the host side. However, for performance and productivity, some applications can
profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities
here when extending the dataflow characteristics to their communication interfaces.\r\n
\ In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA
support and three missing benchmarks that particularly characterize or stress
inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented
for current boards with Intel and Xilinx FPGAs, we established a baseline for
multi-FPGA performance. Additionally, for the communication-centric benchmarks,
we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched
inter-FPGA network that is currently only available for one of the boards. The
evaluation with parallel execution on up to 26 FPGA boards makes use of one of
the largest academic FPGA installations."
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Meyer M, Kenter T, Plessl C. Multi-FPGA Designs and Scaling of HPC Challenge
Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions
on Reconfigurable Technology and Systems. Published online 2023. doi:10.1145/3576200
apa: Meyer, M., Kenter, T., & Plessl, C. (2023). Multi-FPGA Designs and Scaling
of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.
ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/3576200
bibtex: '@article{Meyer_Kenter_Plessl_2023, title={Multi-FPGA Designs and Scaling
of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks},
DOI={10.1145/3576200}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, publisher={Association
for Computing Machinery (ACM)}, author={Meyer, Marius and Kenter, Tobias and Plessl,
Christian}, year={2023} }'
chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Multi-FPGA Designs
and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA
Networks.” ACM Transactions on Reconfigurable Technology and Systems, 2023.
https://doi.org/10.1145/3576200.
ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Multi-FPGA Designs and Scaling of HPC
Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks,” ACM
Transactions on Reconfigurable Technology and Systems, 2023, doi: 10.1145/3576200.'
mla: Meyer, Marius, et al. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks
via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable
Technology and Systems, Association for Computing Machinery (ACM), 2023, doi:10.1145/3576200.
short: M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology
and Systems (2023).
date_created: 2023-01-23T08:40:42Z
date_updated: 2023-07-28T08:02:05Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3576200
keyword:
- General Computer Science
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://dl.acm.org/doi/10.1145/3576200
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901'
- _id: '14'
grant_number: '160364472'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched
Inter-FPGA Networks
type: journal_article
user_id: '24135'
year: '2023'
...
---
_id: '43228'
abstract:
- lang: eng
text: "The computation of electron repulsion integrals (ERIs) over Gaussian-type
orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic
simulations. In practical simulations, several trillions of ERIs may have to be\r\ncomputed
for every time step.\r\nIn this work, we investigate FPGAs as accelerators for
the ERI computation. We use template parameters, here within the Intel oneAPI
tool flow, to create customized designs for 256 different ERI quartet classes,
based on their orbitals. To maximize data reuse, all intermediates are buffered
in FPGA on-chip memory with customized layout. The pre-calculation of intermediates
also helps to overcome data dependencies caused by multi-dimensional recurrence\r\nrelations.
The involved loop structures are partially or even fully unrolled for high throughput
of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary
bitwidth integers is integrated in the FPGA kernels. To our\r\nbest knowledge,
this is the first work on ERI computation on FPGAs that supports more than just
the single most basic quartet class. Also, the integration of ERI computation
and compression it a novelty that is not even covered by CPU or GPU libraries
so far.\r\nOur evaluation shows that using 16-bit integer for the ERI compression,
the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \\times 10^9$
ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors
around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately
explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform
similar computations using the widely used libint reference on a two-socket server
with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up
to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x."
author:
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Wu X, Kenter T, Schade R, Kühne T, Plessl C. Computing and Compressing Electron
Repulsion Integrals on FPGAs. In: 2023 IEEE 31st Annual International Symposium
on Field-Programmable Custom Computing Machines (FCCM). ; 2023:162-173. doi:10.1109/FCCM57271.2023.00026'
apa: Wu, X., Kenter, T., Schade, R., Kühne, T., & Plessl, C. (2023). Computing
and Compressing Electron Repulsion Integrals on FPGAs. 2023 IEEE 31st Annual
International Symposium on Field-Programmable Custom Computing Machines (FCCM),
162–173. https://doi.org/10.1109/FCCM57271.2023.00026
bibtex: '@inproceedings{Wu_Kenter_Schade_Kühne_Plessl_2023, title={Computing and
Compressing Electron Repulsion Integrals on FPGAs}, DOI={10.1109/FCCM57271.2023.00026},
booktitle={2023 IEEE 31st Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM)}, author={Wu, Xin and Kenter, Tobias and Schade,
Robert and Kühne, Thomas and Plessl, Christian}, year={2023}, pages={162–173}
}'
chicago: Wu, Xin, Tobias Kenter, Robert Schade, Thomas Kühne, and Christian Plessl.
“Computing and Compressing Electron Repulsion Integrals on FPGAs.” In 2023
IEEE 31st Annual International Symposium on Field-Programmable Custom Computing
Machines (FCCM), 162–73, 2023. https://doi.org/10.1109/FCCM57271.2023.00026.
ieee: 'X. Wu, T. Kenter, R. Schade, T. Kühne, and C. Plessl, “Computing and Compressing
Electron Repulsion Integrals on FPGAs,” in 2023 IEEE 31st Annual International
Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp.
162–173, doi: 10.1109/FCCM57271.2023.00026.'
mla: Wu, Xin, et al. “Computing and Compressing Electron Repulsion Integrals on
FPGAs.” 2023 IEEE 31st Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM), 2023, pp. 162–73, doi:10.1109/FCCM57271.2023.00026.
short: 'X. Wu, T. Kenter, R. Schade, T. Kühne, C. Plessl, in: 2023 IEEE 31st Annual
International Symposium on Field-Programmable Custom Computing Machines (FCCM),
2023, pp. 162–173.'
date_created: 2023-03-30T11:15:40Z
date_updated: 2023-08-02T15:05:42Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/FCCM57271.2023.00026
external_id:
arxiv:
- '2303.13632'
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/10171537
page: 162-173
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom
Computing Machines (FCCM)
quality_controlled: '1'
status: public
title: Computing and Compressing Electron Repulsion Integrals on FPGAs
type: conference
user_id: '75963'
year: '2023'
...