@inproceedings{24290,
  abstract     = {{The recent rapid development of silicon photonics technology has spurred the process of on-chip 
integration of all kinds of opto-electronic components. One of the most common components of such type 
is the opto-electrical receiver. The monolithic implementation of the receiver could potentially have lower 
power consumption, higher sensitivity and bandwidth due to very short diode to amplifier connection 
length, which has very low parasitic capacitance and series resistance. The SiGe photodiode itself is also 
very compact, thus lowering the junction capacitance and improving its bandwidth. Among the different optical communication systems, coherent transmission lately received a lot of 
attention due to the rising requirements of the optical link capacity, and it was shown that this particular 
approach could benefit greatly from the monolithic integration, since the major component required for the 
demodulation on the receiver side – 90° optical hybrid – could be implemented fully passive and directly 
on the same chip as the receiver itself, together with digital post-processing circuitry. Despite the initial 
complexity of the modulation scheme, advanced silicon photonics components like this optical hybrid 
could make coherent transmission attractive even for short-range optical links. I would like to present the actual designs, implementation and measurement results of 90° fully passive 
optical hybrids, implemented in the IHP SG25PIC (passive photonics IC) technology. One of the designs 
is based on 4x4 multimode interferometer (MMI). The other one is based on two separate 2x2 MMIs with 
additional delay element. The final designs didn’t require any additional tuning after fabrication and have 
shown sufficient precision and performance for a coherent system design. The results of this work were 
later used for the design of monolithic coherent receiver.}},
  author       = {{Gudyriev, Sergiy and Scheytt, Christoph}},
  booktitle    = {{Kleinheubacher Tagung 2015}},
  pages        = {{18}},
  title        = {{{Silicon photonics 90° optical hybrid design for coherent receivers}}},
  year         = {{2015}},
}

@inproceedings{24300,
  author       = {{Wessel, Jan and Schmalz, Klaus and Cahill, Brian and Scheytt, Christoph}},
  booktitle    = {{Elektrotechnisches Kolloquium}},
  title        = {{{Design of an Electrical Interferometer at 120 GHz for Contactless Permittivity Characterization}}},
  year         = {{2014}},
}

@inproceedings{24308,
  abstract     = {{A 115 GHz slow wave transmission line intended for phase detection based integrated biosensors is presented. The structure was fabricated in a 130 nm SiGe process. It achieved the targeted overall phase shift of 1° at 115 GHz. Moreover, the phase can be adjusted by 16 switches using Heterojunction Bipolar (HBT) transistors leading to a phase resolution of 0.125°. The change in input and output matching over all configurations of the switches is not higher than 0.8 dB and the transmission S 21 varies with less than 0.7 dB. To the authors knowledge, it is the first switchable slow wave structure using microstrip transmission lines along with a bipolar switch circuitry. Moreover, the presented structure provides a very powerful solution for real-time digital read-outs in integrated biosensors, without need of additional signal processing steps.}},
  author       = {{Wessel, Jan and Schmalz, Klaus and Scheytt, Christoph and Meliani, Chafik}},
  booktitle    = {{Microwave Symposium (IMS), 2014 IEEE MTT-S International}},
  pages        = {{1 -- 3}},
  publisher    = {{IEEE}},
  title        = {{{ Switchable slow wave transmission line in 130 nm SiGe technology at 115 GHz for phase detection based biosensors}}},
  doi          = {{10.1109/MWSYM.2014.6848446}},
  year         = {{2014}},
}

@inproceedings{24303,
  abstract     = {{A calibration technique as well as measurement results for a 7 GHz Biosensor are presented. It is shown that the applied sensor structure can be calibrated by adjusting the phase of a sensing element's transmission S21. This is realized by slowing down the wave traveling a microstrip line serving as a reference in the differential sensor structure. The dielectric properties along with certain physical boundaries of an obstacle covering parts of the microstrip line evoke that effect. Measurements with an ethanol serious along with simulation results showed that sensitivity can be increased substantially with this calibration technique. A change of the real part of the sample's permittivity of 48 leads to a 18 MHz frequency shift.}},
  author       = {{Wessel, Jan and Schmalz, Klaus and Scheytt, Christoph and Meliani, Chafik and Cahill, Brian}},
  booktitle    = {{European Microwave Conference (EuMC)}},
  pages        = {{699 -- 702}},
  publisher    = {{IEEE}},
  title        = {{{A 7 GHz biosensor for permittivity change with enhanced sensitivity through phase compensation}}},
  doi          = {{10.1109/EuMC.2014.6986530}},
  volume       = {{44th}},
  year         = {{2014}},
}

@inproceedings{24307,
  abstract     = {{There is a continuous increase of bandwidth-demanding services such as ultra HDTV, 3D TV, etc. which will require data rates up to 100-400 Gb/s for short range wireless communication. This paper introduces a novel mixed-mode design where both analog and digital domain design is considered, which helps in the reduction of power consumption. Parallel Sequence Spread Spectrum (PSSS) is used for physical layer (PHY) baseband technology, which considerably alleviates both transmitter and receiver design.}},
  author       = {{Kraemer, Rolf and Wolf, Andreas and Scheytt, Christoph and Kallfass, Ingmar and KrishneGowda, Karthik}},
  booktitle    = {{2014 IEEE 15th Annual IEEE Wireless and Microwave Technology Conference (WAMICON)}},
  publisher    = {{IEEE}},
  title        = {{{Wireless 100 Gb/s: PHY layer Overview and Challenges in THz freqency band}}},
  doi          = {{10.1109/WAMICON.2014.6857743}},
  year         = {{2014}},
}

@article{24302,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, Christoph}},
  journal      = {{Design and Verification Conference (DVCON EUROPE)}},
  location     = {{München, Germany}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{24304,
  author       = {{Scheytt, Christoph}},
  booktitle    = {{Analog 2014,14. Fachtagung der Gesellschaft für Mikroelektronik, Mikrosystemtechnik und Feinwerktechnik des VDE und VDI}},
  title        = {{{System-on-Chip Design für Funkfrequenzen oberhalb von 100 GHz-Herausforderungen und potenzielle Anwendungen}}},
  year         = {{2014}},
}

@article{24306,
  author       = {{Elkhouly, Mohamed and Mao, Yanfei and Meliani, Chafik and Scheytt, Christoph and Ellinger, Frank}},
  journal      = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
  number       = {{9}},
  title        = {{{A -Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology}}},
  volume       = {{49}},
  year         = {{2014}},
}

@inproceedings{24301,
  author       = {{Scheytt, Christoph}},
  booktitle    = {{Fakultätskolloquium der Fakultät für Elektrotechnik und Informationstechnik}},
  title        = {{{mm-Wellen- und Electronic-Photonic System-on-Chip Design}}},
  year         = {{2014}},
}

@article{24310,
  abstract     = {{A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.}},
  author       = {{Awny, Ahmed and Möller, Lothar and Junio, Josef and Scheytt, Christoph and Thiede, Andreas}},
  issn         = {{1558-173X}},
  journal      = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
  number       = {{No.2}},
  pages        = {{452--470}},
  title        = {{{Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer}}},
  doi          = {{10.1109/JSSC.2013.2285385}},
  volume       = {{Vol.49}},
  year         = {{2014}},
}

@inproceedings{34585,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{34583,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@article{25117,
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, J. Christoph}},
  journal      = {{Design and Verification Conference (DVCON EUROPE)}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{24356,
  abstract     = {{A fully integrated six-port receiver front-end at 120 GHz center frequency including a low-noise-amplifier, a passive six-port network, a VCO, and four direct converters is presented in this publication. The overall architecture of the designed six-port receiver is analyzed and fundamental theory of the receiver given. The design of the six-port building blocks is described and measurement results are presented. All circuits have been fabricated in a 0.13μm 300-GHz f T SiGe BiCMOS technology. The fully integrated receiver consumes 85.9 rnA from a 3.3-V supply and occupies an area of 1.03mm 2 . The receiver includes a VCO with a center frequency of 117.15 GHz, a tuning range of 2.7 GHz, and a phase noise of -86 dBc/Hz at 1 MHz offset. The LNA shows a gain of 12 dB, a 3-dB bandwidth of 30 GHz at a power consumption of 9.2 rnA. The six-port core has a conversion gain of 3.6 dB, a P 1dB of -12 dBm, and a power consumption of 28 rnA. The overall receiver shows a conversion gain of 2.4 dB at 120 GHz and P 1dB of -17 dBm.}},
  author       = {{Laemmle, Benjamin and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph and Weigel, Robert and Koelpin, Alexander and Kissinger, Dietmar}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  title        = {{{A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology}}},
  doi          = {{10.1109/SiRF.2013.6489455}},
  year         = {{2013}},
}

@inproceedings{24355,
  abstract     = {{Impulse-radio ultra-wideband systems (IR-UWB) provide short-range wireless communication and precise localization simultaneously. Especially non-coherent IR-UWB reduces the system complexity which enables the design of low-power receivers. This paper presents an integrating digitizer which integrates rectified baseband pulses of an IR-UWB signal and provides the digitized data to the digital baseband of the receiver. The integrator is composed of two time-interleaved (TI) operational amplifiers with capacitive feedback. With this structure, the integrator can be periodically reset without introducing a dead time between two integration periods. The analog-to-digital conversion is performed by a 6 bit 62.4 MS/s successive approximation register analog-to-digital converter (SAR ADC). The integrating digitizer chip is realized in a 250 nm SiGe:C BiCMOS technology from IHP.}},
  author       = {{Digel, Johannes and Masini, Michelangelo and Grözing, Markus and Berroth, Manfred and Fischer, Gunter and Olonbayar, Sonom and Gustat, Hans and Scheytt, Christoph}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  pages        = {{93--95}},
  title        = {{{Integrator and digitizer for a non-coherent IR-UWB receiver}}},
  doi          = {{10.1109/SiRF.2013.6489443}},
  year         = {{2013}},
}

@inproceedings{24353,
  abstract     = {{This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test (BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits and a digital interface. This chipset has been tested in a low-cost package, where the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art integration level and receiver linearity, and DC power consumption.}},
  author       = {{Sun, Yaoming and Marinkovic, Miroslav and Fischer, Gunter and Winkler, Wolfgang and Debski, Wojciech and Beer, Stefan and Zwick, Thomas and Girma, Mekdes Gebresilassie and Hasch, Jürgen and Scheytt, Christoph}},
  booktitle    = {{Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International}},
  pages        = {{148--149}},
  title        = {{{A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization}}},
  doi          = {{10.1109/ISSCC.2013.6487676}},
  year         = {{2013}},
}

@inproceedings{24357,
  abstract     = {{Complex integrated 122 and 245 GHz SiGe BiCMOS transceiver ICs as well as an efficient broadband on-chip antenna are presented. The ICs target radar and sensing applications for the ISM bands at 122 and 245 GHz. Due to high level of integration and basic mm-wave self-testing production as well as test cost are dramatically reduced. Furthermore a compact and efficient on-chip antenna allows for chip-on-board mounting without RF interfaces.}},
  author       = {{Scheytt, Christoph and Sun, Yaoming and Schmalz, Klaus and Mao, Yanfei and Wang, Ruoyu and Debski, Wojciech and Winkler, Wolfgang}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  pages        = {{246--248}},
  title        = {{{Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors}}},
  doi          = {{10.1109/SiRF.2013.6489494}},
  year         = {{2013}},
}

@inproceedings{24354,
  abstract     = {{In this paper, a 6-bit true modular programmable frequency divider with division ratios ranging from 64 to 127 is reported. It is composed of a divider chain of 6 divide-by-2/3 cells, and ECL stages that are introduced as synchronization circuits for programming inputs. The synchronization circuits have CMOS input for compatibility with programming circuits. The stand-alone divider chain is functional up to an input clock frequency of 49 GHz. The combination of the divider chain with synchronization circuits is functional up to 44 GHz. The 6 stage divider draws 34 mA current from a 2.7 V supply. The synchronization circuits draw 30 mA from a 3 V supply. The circuit is fabricated in a 0.13 μm SiGe BiCMOS technology, and is well suited for millimeter-wave phase-locked loop (PLL) circuits which require fine frequency resolution.}},
  author       = {{Ergintav, Arzu and Sun, Yaoming and Scheytt, Christoph and Gürbüz, Yasar}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  title        = {{{49 GHz 6-bit programmable divider in SiGe BiCMOS}}},
  doi          = {{10.1109/SiRF.2013.6489451}},
  year         = {{2013}},
}

@inproceedings{24361,
  abstract     = {{Two subharmonic receivers for 245 GHz spectroscopy sensor applications in the 245 GHz ISM band have been proposed. One receiver consists of an 2nd APDP (antiparallel diode pair) passive SHM (subharmonic mixer), a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA (power amplifier). The other consists of a single-ended four-stage CB (common base) LNA, an 2 nd APDP passive SHM, an IF amplifier, a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA. The receivers are fabricated in a SiGe:C BiCMOS technology with f T /f max =300/500 GHz. The measured conversion gain are -17 dB rsp. 10.6 dB at 245 GHz with 3-dB bandwidths of 13 GHz rsp. 14 GHz, and the single-side band noise figure are 17 dB rsp. 20 dB; the two receivers dissipates a power of 213 mW and 312 mW, respectively.}},
  author       = {{Mao, Yanfei and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph}},
  booktitle    = {{2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium}},
  title        = {{{245 GHz subharmonic receivers in SiGe}}},
  doi          = {{10.1109/RFIC.2013.6569533}},
  year         = {{2013}},
}

@inproceedings{24358,
  abstract     = {{A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with f T /f max of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V.}},
  author       = {{Elkhouly, Mohamed and Mao, Yanfei and Meliani, Chafik and Ellinger, Frank and Scheytt, Christoph}},
  booktitle    = {{2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,}},
  title        = {{{A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology}}},
  doi          = {{10.1109/RFIC.2013.6569589}},
  year         = {{2013}},
}