[{"_id":"65748","publisher":"Springer Nature Switzerland","language":[{"iso":"eng"}],"doi":"10.1007/978-3-032-01986-8_28","user_id":"13256","conference":{"start_date":"2026-05-01","end_date":"2026-05-01"},"publication_identifier":{"issn":["0342-4111","1556-1534"],"isbn":["9783032019851","9783032019868"]},"author":[{"first_name":"Meysam","last_name":"Bahmanian","full_name":"Bahmanian, Meysam","id":"69233"},{"id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt"}],"title":"Frequency Synthesis Based on MLLs","year":"2026","status":"public","date_updated":"2026-06-02T09:34:54Z","publication_status":"published","place":"Cham","date_created":"2026-06-01T12:16:46Z","department":[{"_id":"58"},{"_id":"623"}],"type":"book_chapter","citation":{"ama":"Bahmanian M, Scheytt JC. Frequency Synthesis Based on MLLs. In: <i>Springer Series in Optical Sciences</i>. Springer Nature Switzerland; 2026. doi:<a href=\"https://doi.org/10.1007/978-3-032-01986-8_28\">10.1007/978-3-032-01986-8_28</a>","bibtex":"@inbook{Bahmanian_Scheytt_2026, place={Cham}, title={Frequency Synthesis Based on MLLs}, DOI={<a href=\"https://doi.org/10.1007/978-3-032-01986-8_28\">10.1007/978-3-032-01986-8_28</a>}, booktitle={Springer Series in Optical Sciences}, publisher={Springer Nature Switzerland}, author={Bahmanian, Meysam and Scheytt, J. Christoph}, year={2026} }","mla":"Bahmanian, Meysam, and J. Christoph Scheytt. “Frequency Synthesis Based on MLLs.” <i>Springer Series in Optical Sciences</i>, Springer Nature Switzerland, 2026, doi:<a href=\"https://doi.org/10.1007/978-3-032-01986-8_28\">10.1007/978-3-032-01986-8_28</a>.","chicago":"Bahmanian, Meysam, and J. Christoph Scheytt. “Frequency Synthesis Based on MLLs.” In <i>Springer Series in Optical Sciences</i>. Cham: Springer Nature Switzerland, 2026. <a href=\"https://doi.org/10.1007/978-3-032-01986-8_28\">https://doi.org/10.1007/978-3-032-01986-8_28</a>.","short":"M. Bahmanian, J.C. Scheytt, in: Springer Series in Optical Sciences, Springer Nature Switzerland, Cham, 2026.","apa":"Bahmanian, M., &#38; Scheytt, J. C. (2026). Frequency Synthesis Based on MLLs. In <i>Springer Series in Optical Sciences</i>. Springer Nature Switzerland. <a href=\"https://doi.org/10.1007/978-3-032-01986-8_28\">https://doi.org/10.1007/978-3-032-01986-8_28</a>","ieee":"M. Bahmanian and J. C. Scheytt, “Frequency Synthesis Based on MLLs,” in <i>Springer Series in Optical Sciences</i>, Cham: Springer Nature Switzerland, 2026."},"publication":"Springer Series in Optical Sciences","abstract":[{"lang":"eng","text":"<jats:title>Abstract</jats:title>\r\n                  <jats:p>In this chapter, the precision of optical clocks based on mode-locked laser (MLL) is compared with more conventional types of clock sources. It is shown that the phase noise of the optical pulse train from the MLL can be better than other types of clock sources by orders of magnitude. Then, an abstract representation of frequency synthesizer is demonstrated. Different techniques for RF generation using MLL are shown, and their pros and cons are discussed. Finally, a comparison of all these techniques is made with respect to their phase noise and capability to generate RF signal with different frequencies for different applications.</jats:p>"}]},{"type":"conference","department":[{"_id":"58"}],"date_created":"2026-05-08T17:18:10Z","abstract":[{"lang":"eng","text":"Resilient systems require monitoring and prediction of environmental and intrinsic conditions, as well as the ability to adapt to environmental hazards while optimizing the trade-off among performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. We introduce the migration of TETRISC to the open-source Rocket Chip SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient, scalable architectures configurable for multicore and lockstep modes."}],"publication":"29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)","citation":{"mla":"Hannemann, Kai Arne, et al. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>, 2026.","bibtex":"@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_Scheytt_2026, title={TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture}, booktitle={29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li and Scheytt, J. Christoph}, year={2026} }","ama":"Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L, Scheytt JC. TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture. In: <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>. ; 2026.","ieee":"K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, and J. C. Scheytt, “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture,” presented at the 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg, 2026.","apa":"Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., Lu, L., &#38; Scheytt, J. C. (2026). TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture. <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>. 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg.","chicago":"Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, Li Lu, and J. Christoph Scheytt. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” In <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>, 2026.","short":"K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, J.C. Scheytt, in: 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026."},"user_id":"63972","language":[{"iso":"eng"}],"_id":"65595","date_updated":"2026-07-16T11:05:58Z","title":"TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture","status":"public","year":"2026","author":[{"id":"63972","full_name":"Hannemann, Kai Arne","first_name":"Kai Arne","last_name":"Hannemann"},{"id":"74648","full_name":"Luchterhandt, Lars","first_name":"Lars","last_name":"Luchterhandt"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"full_name":"Ulbricht, Markus","first_name":"Markus","last_name":"Ulbricht"},{"last_name":"Lu","first_name":"Li","full_name":"Lu, Li"},{"full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt","id":"37144"}],"conference":{"name":"29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)","start_date":"2026-03-17","location":"Würzburg","end_date":"2026-03-18"}},{"language":[{"iso":"eng"}],"_id":"58227","user_id":"67349","author":[{"first_name":"Jan","last_name":"Brockmeier","full_name":"Brockmeier, Jan","id":"67349"},{"last_name":"Kruse","first_name":"Stephan","full_name":"Kruse, Stephan","id":"38254"},{"full_name":"Scheytt, J. Christoph","first_name":"J. Christoph","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144"}],"conference":{"end_date":"2025-03-17","start_date":"2025-03-17","name":"German Microwave Conference 2025","location":"Dresden"},"year":"2025","status":"public","title":"A Mach-Zehnder-Modulator based FMCW Lidar Emulator in C-Band","date_updated":"2025-01-17T06:17:50Z","date_created":"2025-01-17T06:17:44Z","place":"Dresden","department":[{"_id":"58"}],"type":"conference","citation":{"ieee":"J. Brockmeier, S. Kruse, and J. C. Scheytt, “A Mach-Zehnder-Modulator based FMCW Lidar Emulator in C-Band,” presented at the German Microwave Conference 2025, Dresden, 2025.","mla":"Brockmeier, Jan, et al. “A Mach-Zehnder-Modulator Based FMCW Lidar Emulator in C-Band.” <i>German Microwave Conference 2025</i>, 2025.","apa":"Brockmeier, J., Kruse, S., &#38; Scheytt, J. C. (2025). A Mach-Zehnder-Modulator based FMCW Lidar Emulator in C-Band. <i>German Microwave Conference 2025</i>. German Microwave Conference 2025, Dresden.","bibtex":"@inproceedings{Brockmeier_Kruse_Scheytt_2025, place={Dresden}, title={A Mach-Zehnder-Modulator based FMCW Lidar Emulator in C-Band}, booktitle={German Microwave Conference 2025}, author={Brockmeier, Jan and Kruse, Stephan and Scheytt, J. Christoph}, year={2025} }","chicago":"Brockmeier, Jan, Stephan Kruse, and J. Christoph Scheytt. “A Mach-Zehnder-Modulator Based FMCW Lidar Emulator in C-Band.” In <i>German Microwave Conference 2025</i>. Dresden, 2025.","short":"J. Brockmeier, S. Kruse, J.C. Scheytt, in: German Microwave Conference 2025, Dresden, 2025.","ama":"Brockmeier J, Kruse S, Scheytt JC. A Mach-Zehnder-Modulator based FMCW Lidar Emulator in C-Band. In: <i>German Microwave Conference 2025</i>. ; 2025."},"publication":"German Microwave Conference 2025","project":[{"name":"LiRaS: LiDAR Radar Kombisystem","_id":"1339"}]},{"date_created":"2025-11-10T08:31:47Z","department":[{"_id":"58"}],"type":"journal_article","citation":{"apa":"Sadiye, B., Iftekhar, M., Müller, W., &#38; Scheytt, J. C. (2025). 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>","ieee":"B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025, doi: <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","short":"B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).","chicago":"Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>.","mla":"Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","ama":"Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. Published online 2025. doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>","bibtex":"@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }"},"publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","project":[{"name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing","_id":"325"}],"_id":"62148","publisher":"IEEE","language":[{"iso":"eng"}],"doi":"10.1109/TVLSI.2025.3625787","user_id":"93634","publication_identifier":{"issn":["1063-8210"]},"author":[{"id":"93634","first_name":"Babak","last_name":"Sadiye","full_name":"Sadiye, Babak"},{"id":"47944","full_name":"Iftekhar, Mohammed","first_name":"Mohammed","last_name":"Iftekhar"},{"last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243"},{"full_name":"Scheytt, J. Christoph","first_name":"J. Christoph","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144"}],"status":"public","year":"2025","title":"60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design","date_updated":"2025-11-10T08:38:07Z","publication_status":"published"},{"date_updated":"2025-11-20T10:34:13Z","title":"A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology","status":"public","year":"2025","conference":{"location":"Riga, Latvia","name":"IEEE Nordic Circuits and Systems Conference (NORCAS)","start_date":"2025-10-28","end_date":"2025-10-29"},"author":[{"id":"47944","full_name":"Iftekhar, Mohammed","first_name":"Mohammed","last_name":"Iftekhar"},{"id":"93634","first_name":"Babak","last_name":"Sadiye","full_name":"Sadiye, Babak"},{"id":"16243","last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang"},{"full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt","id":"37144"}],"doi":"10.1109/NorCAS66540.2025.11231203","user_id":"47944","_id":"62126","language":[{"iso":"eng"}],"project":[{"_id":"325","name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing"}],"publication":"IEEE Nordic Circuits and Systems Conference (NORCAS)","citation":{"bibtex":"@inproceedings{Iftekhar_Sadiye_Müller_Scheytt_2025, title={A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>}, booktitle={IEEE Nordic Circuits and Systems Conference (NORCAS)}, author={Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","ama":"Iftekhar M, Sadiye B, Müller W, Scheytt JC. A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. In: <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. ; 2025. doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>","mla":"Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025, doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","chicago":"Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>.","short":"M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits and Systems Conference (NORCAS), 2025.","ieee":"M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia, 2025, doi: <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","apa":"Iftekhar, M., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2025). A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>"},"type":"conference","department":[{"_id":"58"}],"date_created":"2025-11-07T10:41:45Z"},{"publication":"2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","citation":{"ieee":"M. Weizel, H. G. Malavalli Nagaraju, and J. C. Scheytt, “A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS,” Phoenix, Arizona, USA, 2025, doi: <a href=\"https://doi.org/10.1109/bcicts63111.2025.11211462\">10.1109/bcicts63111.2025.11211462</a>.","apa":"Weizel, M., Malavalli Nagaraju, H. G., &#38; Scheytt, J. C. (2025). A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS. <i>2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. <a href=\"https://doi.org/10.1109/bcicts63111.2025.11211462\">https://doi.org/10.1109/bcicts63111.2025.11211462</a>","chicago":"Weizel, Maxim, Harshan Gowda Malavalli Nagaraju, and J. Christoph Scheytt. “A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS.” In <i>2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/bcicts63111.2025.11211462\">https://doi.org/10.1109/bcicts63111.2025.11211462</a>.","short":"M. Weizel, H.G. Malavalli Nagaraju, J.C. Scheytt, in: 2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), IEEE, 2025.","mla":"Weizel, Maxim, et al. “A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS.” <i>2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/bcicts63111.2025.11211462\">10.1109/bcicts63111.2025.11211462</a>.","bibtex":"@inproceedings{Weizel_Malavalli Nagaraju_Scheytt_2025, title={A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS}, DOI={<a href=\"https://doi.org/10.1109/bcicts63111.2025.11211462\">10.1109/bcicts63111.2025.11211462</a>}, booktitle={2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}, publisher={IEEE}, author={Weizel, Maxim and Malavalli Nagaraju, Harshan Gowda and Scheytt, J. Christoph}, year={2025} }","ama":"Weizel M, Malavalli Nagaraju HG, Scheytt JC. A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS. In: <i>2025 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/bcicts63111.2025.11211462\">10.1109/bcicts63111.2025.11211462</a>"},"project":[{"name":"SPP 2111; TP: Ultrabreitbandiger Photonisch-Elektronischer Analog-Digital-Wandler (PACE) - Phase 2","_id":"303"},{"_id":"298","name":"FOR 2863: Metrologie für die THz Kommunikation (Meteracom)"},{"_id":"308","name":"FOR 2863:  Metrologie für die THz Kommunikation, TP: Ultrabreitbandige Abtastung"},{"_id":"313","name":"FOR 2863:  Metrologie für die THz Kommunikation, TP C3: Skalierbares THz Transceiver Impairment Modell"}],"date_created":"2025-11-20T11:59:10Z","type":"conference","department":[{"_id":"58"}],"status":"public","year":"2025","title":"A 128 GS/s 2x Time-Interleaved Track and Hold Amplifier in 130nm SiGe BiCMOS","conference":{"location":"Phoenix, Arizona, USA"},"author":[{"full_name":"Weizel, Maxim","orcid":"0000-0003-2699-9839","first_name":"Maxim","last_name":"Weizel","id":"44271"},{"first_name":"Harshan Gowda","last_name":"Malavalli Nagaraju","full_name":"Malavalli Nagaraju, Harshan Gowda","id":"84233"},{"orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt","full_name":"Scheytt, J. Christoph","id":"37144"}],"date_updated":"2025-11-20T12:02:26Z","publication_status":"published","_id":"62270","language":[{"iso":"eng"}],"publisher":"IEEE","doi":"10.1109/bcicts63111.2025.11211462","user_id":"44271"},{"_id":"58856","language":[{"iso":"eng"}],"publisher":"VDE Verlag","user_id":"16243","author":[{"id":"63972","full_name":"Hannemann, Kai Arne","first_name":"Kai Arne","last_name":"Hannemann"},{"full_name":"Bütün, Hüseyin Berke","last_name":"Bütün","first_name":"Hüseyin Berke"},{"last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243"},{"full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt","id":"37144"}],"publication_identifier":{"isbn":["978-3-8007-6515-7"]},"year":"2025","status":"public","title":"Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study","date_updated":"2025-11-20T12:46:44Z","place":"Warnemünde","date_created":"2025-02-26T14:33:18Z","department":[{"_id":"58"}],"type":"conference","citation":{"apa":"Hannemann, K. A., Bütün, H. B., Müller, W., &#38; Scheytt, J. C. (2025). Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study. <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>.","ieee":"K. A. Hannemann, H. B. Bütün, W. Müller, and J. C. Scheytt, “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study,” 2025.","short":"K.A. Hannemann, H.B. Bütün, W. Müller, J.C. Scheytt, in: MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, VDE Verlag, Warnemünde, 2025.","chicago":"Hannemann, Kai Arne, Hüseyin Berke Bütün, Wolfgang Müller, and J. Christoph Scheytt. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” In <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>. Warnemünde: VDE Verlag, 2025.","mla":"Hannemann, Kai Arne, et al. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>, VDE Verlag, 2025.","ama":"Hannemann KA, Bütün HB, Müller W, Scheytt JC. Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study. In: <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>. VDE Verlag; 2025.","bibtex":"@inproceedings{Hannemann_Bütün_Müller_Scheytt_2025, place={Warnemünde}, title={Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study}, booktitle={MBMV 2025 - 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen}, publisher={VDE Verlag}, author={Hannemann, Kai Arne and Bütün, Hüseyin Berke and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }"},"publication":"MBMV 2025 - 28. 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In: <i>2025 55th European Microwave Conference (EuMC)</i>. ; 2025:127-130. doi:<a href=\"https://doi.org/10.23919/EuMC65286.2025.11235121\">10.23919/EuMC65286.2025.11235121</a>","bibtex":"@inproceedings{Kruse_Diri_Mager_Kress_Scheytt_2025, title={Electrooptical Integration of an Electronic Photonic Integrated Circuit Into Plastic Substrates Using Mid-Technology}, DOI={<a href=\"https://doi.org/10.23919/EuMC65286.2025.11235121\">10.23919/EuMC65286.2025.11235121</a>}, booktitle={2025 55th European Microwave Conference (EuMC)}, author={Kruse, Stephan and Diri, Jabil and Mager, Thomas and Kress, Christian and Scheytt, J. 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In: <i>2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/ICECS66544.2025.11270577\">10.1109/ICECS66544.2025.11270577</a>","bibtex":"@inproceedings{Weizel_Gudyriev_Zazzi_Müller_Schwabe_Witzens_Scheytt_2025, title={High Voltage (5Vpp) Driver Monolithically Integrated with Thermally Tunable Optical Ring Resonators in a Silicon Photonics Technology}, DOI={<a href=\"https://doi.org/10.1109/ICECS66544.2025.11270577\">10.1109/ICECS66544.2025.11270577</a>}, booktitle={2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)}, publisher={IEEE}, author={Weizel, Maxim and Gudyriev, Sergiy and Zazzi, Andrea and Müller, Juliana and Schwabe, Tobias and Witzens, Jeremy and Scheytt, J. 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Noise Folding in Optoelectronic PLLs for Ultralow Phase Noise: Modeling and Suppression With Experimental Validation. <i>IEEE Transactions on Microwave Theory and Techniques</i>. <a href=\"https://doi.org/10.1109/TMTT.2025.3615413\">https://doi.org/10.1109/TMTT.2025.3615413</a>","mla":"Surendranath Shroff, Vijayalakshmi, et al. “Noise Folding in Optoelectronic PLLs for Ultralow Phase Noise: Modeling and Suppression With Experimental Validation.” <i>IEEE Transactions on Microwave Theory and Techniques</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/TMTT.2025.3615413\">10.1109/TMTT.2025.3615413</a>.","ieee":"V. Surendranath Shroff, M. Bahmanian, and J. C. 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Christoph Scheytt. “Noise Folding in Optoelectronic PLLs for Ultralow Phase Noise: Modeling and Suppression With Experimental Validation.” <i>IEEE Transactions on Microwave Theory and Techniques</i>, 2025. <a href=\"https://doi.org/10.1109/TMTT.2025.3615413\">https://doi.org/10.1109/TMTT.2025.3615413</a>.","bibtex":"@article{Surendranath Shroff_Bahmanian_Scheytt_2025, title={Noise Folding in Optoelectronic PLLs for Ultralow Phase Noise: Modeling and Suppression With Experimental Validation}, DOI={<a href=\"https://doi.org/10.1109/TMTT.2025.3615413\">10.1109/TMTT.2025.3615413</a>}, journal={IEEE Transactions on Microwave Theory and Techniques}, publisher={IEEE}, author={Surendranath Shroff, Vijayalakshmi and Bahmanian, Meysam and Scheytt, J. Christoph}, year={2025} }"},"publication":"IEEE Transactions on Microwave Theory and Techniques"},{"date_created":"2025-01-17T06:28:06Z","type":"conference","department":[{"_id":"58"}],"citation":{"ieee":"S. Kruse, J. Brockmeier, T. Schwabe, and J. C. Scheytt, “A Visible Light FMCW Lidar System Based on LEDs,” presented at the German Microwave Conference, Dresden, 2025.","apa":"Kruse, S., Brockmeier, J., Schwabe, T., &#38; Scheytt, J. C. (2025). <i>A Visible Light FMCW Lidar System Based on LEDs</i>. German Microwave Conference, Dresden.","short":"S. Kruse, J. Brockmeier, T. Schwabe, J.C. Scheytt, in: 2025.","chicago":"Kruse, Stephan, Jan Brockmeier, Tobias Schwabe, and J. Christoph Scheytt. “A Visible Light FMCW Lidar System Based on LEDs,” 2025.","mla":"Kruse, Stephan, et al. <i>A Visible Light FMCW Lidar System Based on LEDs</i>. 2025.","bibtex":"@inproceedings{Kruse_Brockmeier_Schwabe_Scheytt_2025, title={A Visible Light FMCW Lidar System Based on LEDs}, author={Kruse, Stephan and Brockmeier, Jan and Schwabe, Tobias and Scheytt, J. Christoph}, year={2025} }","ama":"Kruse S, Brockmeier J, Schwabe T, Scheytt JC. A Visible Light FMCW Lidar System Based on LEDs. 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Christoph}, year={2025} }","ama":"Kruse S, Surendranath Shroff V, Bahmanian M, Brockmeier J, Scheytt JC. An Ultra Low Phase Noise Frequency Synthesizer with Optical Output for 77 GHz Photonic Radar. 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High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology .","bibtex":"@inproceedings{Kress_Schwabe_Mihaylov_Scheytt, title={High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology }, author={Kress, Christian and Schwabe, Tobias and Mihaylov, Martin Miroslavov and Scheytt, J. Christoph} }","mla":"Kress, Christian, et al. <i>High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology </i>.","short":"C. Kress, T. Schwabe, M.M. Mihaylov, J.C. Scheytt, in: n.d.","chicago":"Kress, Christian, Tobias Schwabe, Martin Miroslavov Mihaylov, and J. Christoph Scheytt. “High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology ,” n.d.","apa":"Kress, C., Schwabe, T., Mihaylov, M. M., &#38; Scheytt, J. C. (n.d.). <i>High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology </i>. CLEO: Conference on Lasers and Electro-Optics, Long Beach, CA, USA.","ieee":"C. Kress, T. Schwabe, M. M. Mihaylov, and J. C. Scheytt, “High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology ,” presented at the CLEO: Conference on Lasers and Electro-Optics, Long Beach, CA, USA."},"user_id":"13256","_id":"59896","language":[{"iso":"eng"}],"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/11190539","open_access":"1"}],"date_updated":"2026-03-31T09:06:49Z","publication_status":"accepted","conference":{"end_date":"2025-05-09","name":"CLEO: Conference on Lasers and Electro-Optics","start_date":"2025-05-04","location":"Long Beach, CA, USA"},"author":[{"orcid":"0000-0002-4403-2237","first_name":"Christian","last_name":"Kress","full_name":"Kress, Christian","id":"13256"},{"id":"39217","last_name":"Schwabe","first_name":"Tobias","full_name":"Schwabe, Tobias"},{"first_name":"Martin Miroslavov","last_name":"Mihaylov","full_name":"Mihaylov, Martin Miroslavov","id":"42449"},{"id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt"}],"year":"2025","status":"public","title":"High-Speed Mach-Zehnder Modulator with Linear Segmented On-Chip Drivers in Photonic 45nm SOI-CMOS Technology "},{"date_updated":"2026-04-29T14:27:08Z","publication_status":"accepted","year":"2025","status":"public","title":"Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source","conference":{"start_date":"2025-05-03","name":"PhotonIcs and Electromagnetics Research Symposium (PIERS)","location":"Abu Dhabi","end_date":"2025-05-09"},"author":[{"full_name":"Kress, Christian","first_name":"Christian","last_name":"Kress","orcid":"0000-0002-4403-2237","id":"13256"},{"id":"42449","last_name":"Mihaylov","first_name":"Martin Miroslavov","full_name":"Mihaylov, Martin Miroslavov"},{"full_name":"Schwabe, Tobias","last_name":"Schwabe","first_name":"Tobias","id":"39217"},{"id":"26263","last_name":"Silberhorn","first_name":"Christine","full_name":"Silberhorn, Christine"},{"id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph","last_name":"Scheytt"}],"doi":"10.1109/PIERS-Spring66516.2025.11276835","user_id":"13256","publisher":"PhotonIcs and Electromagnetics Research Symposium (PIERS)","_id":"59895","language":[{"iso":"eng"}],"abstract":[{"text":"The generation of optically broadband Nyquist pulse sequences using an integrated Mach-Zehnder modulator (MZM) in a thin-film lithium-niobate (TFLN) platform with repetition rates of 5 to 32 GHz and optical bandwidths of up to 160 GHz is demonstrated. Nyquist pulse sequences with high optical bandwidth can be used as synchronization and control signals in quantum sources based on photon pair generation.","lang":"eng"}],"project":[{"_id":"302","name":"PONyDAC: SPP 2111 - PONyDAC II - Präziser Optischer Nyquist-Puls-Synthesizer DAC"},{"name":"TRR 142 - C11: TRR 142 - Kompakte Photonenpaar-Quelle mit ultraschnellen Modulatoren auf Basis von CMOS und LNOI (C11*)","_id":"175"}],"publication":"PIERS Proceedings ","citation":{"short":"C. Kress, M.M. Mihaylov, T. Schwabe, C. Silberhorn, J.C. Scheytt, in: PIERS Proceedings , PhotonIcs and Electromagnetics Research Symposium (PIERS), n.d.","chicago":"Kress, Christian, Martin Miroslavov Mihaylov, Tobias Schwabe, Christine Silberhorn, and J. Christoph Scheytt. “Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source.” In <i>PIERS Proceedings </i>. PhotonIcs and Electromagnetics Research Symposium (PIERS), n.d. <a href=\"https://doi.org/10.1109/PIERS-Spring66516.2025.11276835\">https://doi.org/10.1109/PIERS-Spring66516.2025.11276835</a>.","ieee":"C. Kress, M. M. Mihaylov, T. Schwabe, C. Silberhorn, and J. C. Scheytt, “Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source,” presented at the PhotonIcs and Electromagnetics Research Symposium (PIERS), Abu Dhabi, doi: <a href=\"https://doi.org/10.1109/PIERS-Spring66516.2025.11276835\">10.1109/PIERS-Spring66516.2025.11276835</a>.","apa":"Kress, C., Mihaylov, M. M., Schwabe, T., Silberhorn, C., &#38; Scheytt, J. C. (n.d.). Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source. <i>PIERS Proceedings </i>. PhotonIcs and Electromagnetics Research Symposium (PIERS), Abu Dhabi. <a href=\"https://doi.org/10.1109/PIERS-Spring66516.2025.11276835\">https://doi.org/10.1109/PIERS-Spring66516.2025.11276835</a>","bibtex":"@inproceedings{Kress_Mihaylov_Schwabe_Silberhorn_Scheytt, title={Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source}, DOI={<a href=\"https://doi.org/10.1109/PIERS-Spring66516.2025.11276835\">10.1109/PIERS-Spring66516.2025.11276835</a>}, booktitle={PIERS Proceedings }, publisher={PhotonIcs and Electromagnetics Research Symposium (PIERS)}, author={Kress, Christian and Mihaylov, Martin Miroslavov and Schwabe, Tobias and Silberhorn, Christine and Scheytt, J. Christoph} }","ama":"Kress C, Mihaylov MM, Schwabe T, Silberhorn C, Scheytt JC. Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source. In: <i>PIERS Proceedings </i>. PhotonIcs and Electromagnetics Research Symposium (PIERS). doi:<a href=\"https://doi.org/10.1109/PIERS-Spring66516.2025.11276835\">10.1109/PIERS-Spring66516.2025.11276835</a>","mla":"Kress, Christian, et al. “Broadband Nyquist Pulse Generation on TFLN Platform for Integrated Quantum Source.” <i>PIERS Proceedings </i>, PhotonIcs and Electromagnetics Research Symposium (PIERS), doi:<a href=\"https://doi.org/10.1109/PIERS-Spring66516.2025.11276835\">10.1109/PIERS-Spring66516.2025.11276835</a>."},"type":"conference","department":[{"_id":"58"},{"_id":"623"}],"date_created":"2025-05-14T09:59:50Z"},{"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication":"OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits","citation":{"mla":"Luchterhandt, Lars, et al. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>, 2025.","ama":"Luchterhandt L, Govindasamy V, Wang Y, Dömer R, Müller W, Scheytt JC. Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells. In: <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>. ; 2025.","bibtex":"@inproceedings{Luchterhandt_Govindasamy_Wang_Dömer_Müller_Scheytt_2025, place={Lyon, France}, title={Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells}, booktitle={OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","apa":"Luchterhandt, L., Govindasamy, V., Wang, Y., Dömer, R., Müller, W., &#38; Scheytt, J. C. (2025). Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells. <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>.","ieee":"L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, and J. C. 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Scheytt, in: OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits, Lyon, France, 2025."},"type":"conference","department":[{"_id":"58"}],"place":"Lyon, France","date_created":"2025-02-26T14:40:23Z","date_updated":"2026-07-16T14:58:16Z","year":"2025","status":"public","title":"Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells","author":[{"full_name":"Luchterhandt, Lars","last_name":"Luchterhandt","first_name":"Lars","id":"74648"},{"full_name":"Govindasamy, Vivek","last_name":"Govindasamy","first_name":"Vivek"},{"first_name":"Yutong","last_name":"Wang","full_name":"Wang, Yutong"},{"last_name":"Dömer","first_name":"Rainer","full_name":"Dömer, Rainer"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"id":"37144","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","first_name":"J. Christoph","full_name":"Scheytt, J. Christoph"}],"user_id":"16243","_id":"58861","language":[{"iso":"eng"}]},{"date_created":"2026-07-16T15:15:02Z","department":[{"_id":"58"}],"type":"conference","citation":{"mla":"Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>.","ama":"Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Müller W, Dömer R. A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>","bibtex":"@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={<a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>}, booktitle={2025 Forum on Specification &#38;amp;amp; Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025} }","apa":"Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Müller, W., &#38; Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">https://doi.org/10.1109/fdl68117.2025.11165408</a>","ieee":"L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">10.1109/fdl68117.2025.11165408</a>.","chicago":"Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/fdl68117.2025.11165408\">https://doi.org/10.1109/fdl68117.2025.11165408</a>.","short":"L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, R. Dömer, in: 2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL), IEEE, 2025."},"publication":"2025 Forum on Specification &amp;amp; Design Languages (FDL)","_id":"66520","publisher":"IEEE","language":[{"iso":"eng"}],"user_id":"16243","doi":"10.1109/fdl68117.2025.11165408","author":[{"id":"74648","full_name":"Luchterhandt, Lars","first_name":"Lars","last_name":"Luchterhandt"},{"full_name":"Govindasamy, Vivek","first_name":"Vivek","last_name":"Govindasamy"},{"first_name":"Yutong","last_name":"Wang","full_name":"Wang, Yutong"},{"full_name":"Scheytt, Christoph","orcid":"0000-0002-5950-6618 ","first_name":"Christoph","last_name":"Scheytt","id":"37144"},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"}],"title":"A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids","status":"public","year":"2025","publication_status":"published","date_updated":"2026-07-16T15:17:01Z"}]