@misc{587, author = {{Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}}, publisher = {{Awareness Magazine}}, title = {{{Programming models for reconfigurable heterogeneous multi-cores}}}, year = {{2012}}, } @inproceedings{10636, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}}, title = {{{Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array}}}, year = {{2012}}, } @article{10685, author = {{Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}}, journal = {{International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}}, number = {{4}}, pages = {{17--31}}, publisher = {{IGI Global}}, title = {{{Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}}}, doi = {{10.4018/jaras.2012100102}}, volume = {{3}}, year = {{2012}}, } @misc{10723, author = {{Platzner, Marco and Boschmann, Alexander and Kaufmann, Paul}}, pages = {{6--11}}, title = {{{Wieder natürlich gehen und greifen}}}, year = {{2012}}, } @misc{13462, author = {{Lewis, Peter and Platzner, Marco and Yao, Xin}}, publisher = {{Awareness Magazine}}, title = {{{An outlook for self-awareness in computing systems}}}, year = {{2012}}, } @article{2108, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, issn = {{0141-9331}}, journal = {{Microprocessors and Microsystems}}, keywords = {{funding-altera}}, number = {{2}}, pages = {{110--126}}, title = {{{IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}}}, doi = {{10.1016/j.micpro.2011.04.002}}, volume = {{36}}, year = {{2012}}, } @inproceedings{609, abstract = {{Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}}, pages = {{8--9}}, title = {{{Hardware/Software Platform for Self-aware Compute Nodes}}}, year = {{2012}}, } @inproceedings{2191, author = {{Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}}, booktitle = {{Intel European Research and Innovation Conference}}, keywords = {{funding-intel}}, title = {{{Estimation and Partitioning for CPU-Accelerator Architectures}}}, year = {{2011}}, } @inbook{2202, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}}, editor = {{Khalgui, Mohamed and Hanisch, Hans-Michael}}, isbn = {{978-1-60960-086-0}}, publisher = {{IGI Global}}, title = {{{Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}}}, doi = {{10.4018/978-1-60960-086-0}}, year = {{2011}}, } @inproceedings{2204, author = {{Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}}, booktitle = {{Proc. European Conf. on Parallel Processing (Euro-Par)}}, publisher = {{Springer}}, title = {{{Parallel Monte-Carlo Tree Search for HPC Systems}}}, doi = {{10.1007/978-3-642-23397-5_36}}, volume = {{6853}}, year = {{2011}}, } @inproceedings{666, abstract = {{Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach.}}, author = {{Drzevitzky, Stephanie and Platzner, Marco}}, booktitle = {{Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, pages = {{58--65}}, title = {{{Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach}}}, doi = {{10.1109/ReCoSoC.2011.5981499}}, year = {{2011}}, } @inproceedings{10637, author = {{Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT)}}, title = {{{Accurate gait phase detection using surface electromyographic signals and support vector machines}}}, year = {{2011}}, } @inproceedings{10638, author = {{Boschmann, Alexander and Platzner, Marco and Robrecht, Michael and Hahn, Martin and Winkler, Michael}}, booktitle = {{Proc. MyoElectric Controls Symposium (MEC)}}, title = {{{Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems}}}, year = {{2011}}, } @inbook{10687, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Organic Computing---A Paradigm Shift for Complex Systems}}, editor = {{Müller-Schloer, Christian and Schmeck, Hartmut and Ungerer, Theo}}, pages = {{193--206}}, publisher = {{Springer Basel}}, title = {{{Multi-objective Intrinsic Evolution of Embedded Systems}}}, volume = {{1}}, year = {{2011}}, } @inbook{10737, author = {{Sekanina, Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{125--179}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Evolution of Electronic Circuits}}}, year = {{2011}}, } @inbook{10748, author = {{Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{35--99}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Problem Decomposition in Cartesian Genetic Programming}}}, year = {{2011}}, } @inproceedings{13643, author = {{Agne, Andreas and Platzner, Marco and Lübbers, Enno}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781457714849}}, pages = {{185--188}}, publisher = {{IEEE}}, title = {{{Memory Virtualization for Multithreaded Reconfigurable Hardware}}}, doi = {{10.1109/fpl.2011.42}}, year = {{2011}}, } @inproceedings{2200, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}}, isbn = {{978-1-4503-0554-9}}, keywords = {{design space exploration, LLVM, partitioning, performance, estimation, funding-intel}}, pages = {{177--180}}, publisher = {{ACM}}, title = {{{Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}}}, doi = {{10.1145/1950413.1950448}}, year = {{2011}}, } @article{2201, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, journal = {{Int. Journal of Recon- figurable Computing (IJRC)}}, keywords = {{funding-altera}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}}}, doi = {{10.1155/2011/760954}}, year = {{2011}}, } @inproceedings{2994, author = {{Schäfer, Wilhelm and Trächtler, Ansgar and Birattari, Mauro and Blömer, Johannes and Dorigo, Marco and Engels, Gregor and O'Grady, Rehan and Platzner, Marco and Rammig, Franz and Reif, Wolfgang}}, booktitle = {{Proceedings of the FSE/SDP workshop on Future of software engineering research - FoSER '10}}, isbn = {{9781450304276}}, publisher = {{ACM Press}}, title = {{{Engineering self-coordinating software intensive systems}}}, doi = {{10.1145/1882362.1882428}}, year = {{2010}}, }