@inproceedings{13638, author = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}}, isbn = {{9781424443758}}, publisher = {{IEEE}}, title = {{{An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}}}, doi = {{10.1109/fpt.2009.5377645}}, year = {{2009}}, } @inproceedings{13639, author = {{Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, publisher = {{IEEE}}, title = {{{Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}}}, year = {{2009}}, } @inproceedings{2350, abstract = {{Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. }}, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, isbn = {{978-1-4244-4450-2}}, keywords = {{IMORC, interconnect, performance}}, pages = {{275--278}}, publisher = {{IEEE Computer Society}}, title = {{{IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}}}, doi = {{10.1109/FCCM.2009.25}}, year = {{2009}}, } @inproceedings{2262, abstract = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }}, author = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}}, keywords = {{EvoCache, evolvable hardware, computer architecture}}, pages = {{11--18}}, publisher = {{IEEE Computer Society}}, title = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}}, year = {{2009}}, } @inproceedings{2238, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{978-0-7695-3917-1}}, keywords = {{IMORC, graphics}}, pages = {{119--124}}, publisher = {{IEEE Computer Society}}, title = {{{Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}}}, doi = {{10.1109/ReConFig.2009.32}}, year = {{2009}}, } @inproceedings{2261, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, isbn = {{978-1-4244-3892-1}}, issn = {{1946-1488}}, keywords = {{IMORC, NOC, KNN, accelerator}}, pages = {{338--344}}, publisher = {{IEEE}}, title = {{{An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}}}, year = {{2009}}, } @inproceedings{2365, author = {{Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{The GOmputer: Accelerating GO with FPGAs}}}, year = {{2008}}, } @inproceedings{10653, author = {{Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}}, booktitle = {{IEEE Adaptive Hardware and Systems (AHS)}}, pages = {{32--39}}, publisher = {{IEEE}}, title = {{{Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}}}, year = {{2008}}, } @inproceedings{10656, author = {{Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{IEEE Intl. Conf. on Evolvable Systems (ICES)}}, pages = {{22--33}}, publisher = {{Springer}}, title = {{{A Comparison of Evolvable Hardware Architectures for Classification Tasks}}}, volume = {{5216}}, year = {{2008}}, } @unpublished{10690, author = {{Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}}, title = {{{Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}}}, year = {{2008}}, } @inproceedings{10691, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Genetic and Evolutionary Computation (GECCO)}}, pages = {{1219 -- 1226}}, publisher = {{ACM Press}}, title = {{{Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}}}, year = {{2008}}, } @inproceedings{13629, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}}, publisher = {{IEEE}}, title = {{{Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}}}, year = {{2008}}, } @inproceedings{13630, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}}}, year = {{2008}}, } @inproceedings{13631, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424419609}}, publisher = {{IEEE}}, title = {{{A portable abstraction layer for hardware threads}}}, doi = {{10.1109/fpl.2008.4629901}}, year = {{2008}}, } @inproceedings{2364, author = {{Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{A Hardware Accelerator for k-th Nearest Neighbor Thinning}}}, year = {{2008}}, } @inproceedings{2372, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Many-core and Reconfigurable Supercomputing Conference (MRSC)}}, keywords = {{IMORC, IP core, interconnect}}, title = {{{IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}}}, year = {{2008}}, } @inproceedings{10698, author = {{Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Biologically Inspired Collaborative Computing (BICC)}}, pages = {{213--222}}, publisher = {{Springer}}, title = {{{On Robust Evolution of Digital Hardware}}}, doi = {{10.1007/978-0-387-09655-1_19}}, volume = {{268}}, year = {{2008}}, } @inproceedings{6508, abstract = {{In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.}}, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}}, isbn = {{076952866X}}, keywords = {{integrated circuit design, hardware evolution, evolutionary hardware design, evolutionary optimizers, hash functions, preengineered circuits, Hardware, Circuits, Design optimization, Visualization, Genetic programming, Genetic mutations, Clustering algorithms, Biological cells, Field programmable gate arrays, Routing}}, location = {{Edinburgh, UK}}, pages = {{447--454}}, publisher = {{IEEE}}, title = {{{MOVES: A Modular Framework for Hardware Evolution}}}, doi = {{10.1109/ahs.2007.73}}, year = {{2007}}, } @article{10625, author = {{Bergmann, Neil and Platzner, Marco and Teich, Jürgen}}, journal = {{{EURASIP} Journal on Embedded Systems}}, pages = {{1--2}}, publisher = {{Springer Science+Business Media}}, title = {{{Dynamically Reconfigurable Architectures (editorial)}}}, doi = {{10.1155/2007/28405}}, volume = {{2007}}, year = {{2007}}, } @article{10646, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, keywords = {{reconfigurable architectures, resource allocation, device reconfiguration time, dynamic hardware reconfiguration, dynamically reconfigurable hardware, light-weight runtime system, merge server distribute load, periodic real-time tasks, runtime system overheads, schedulability analysis, scheduling technique, server-based execution, synthesis tool flow}}, number = {{4}}, pages = {{295--302}}, title = {{{Server-based execution of periodic tasks on dynamically reconfigurable hardware}}}, doi = {{10.1049/iet-cdt:20060186}}, volume = {{1}}, year = {{2007}}, }