[{"has_accepted_license":"1","status":"public","user_id":"477","ddc":["040"],"_id":"433","page":"1-6 ","project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"}],"citation":{"short":"T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–6, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">https://doi.org/10.1109/ReConFig.2014.7032514</a>.","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–6.","apa":"Wiersema, T., Bockhorn, A., &#38; Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i> (pp. 1–6). <a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">https://doi.org/10.1109/ReConFig.2014.7032514</a>","bibtex":"@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">10.1109/ReConFig.2014.7032514</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2014}, pages={1–6} }","ama":"Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. ; 2014:1-6. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">10.1109/ReConFig.2014.7032514</a>","mla":"Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032514\">10.1109/ReConFig.2014.7032514</a>."},"file_date_updated":"2018-03-16T11:30:58Z","date_updated":"2022-01-06T07:00:56Z","author":[{"full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema","id":"3118"},{"first_name":"Arne","last_name":"Bockhorn","full_name":"Bockhorn, Arne"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"year":"2014","title":"Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA","doi":"10.1109/ReConFig.2014.7032514","language":[{"iso":"eng"}],"abstract":[{"text":"Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:16Z","file":[{"relation":"main_file","date_updated":"2018-03-16T11:30:58Z","file_name":"433-wiersema14_reconfig_IEEE_approved.pdf","file_size":369333,"access_level":"closed","file_id":"1355","success":1,"content_type":"application/pdf","creator":"florida","date_created":"2018-03-16T11:30:58Z"}]},{"issue":"3","publication":"IEEE Transactions on Computational Intelligence and AI in Games","citation":{"mla":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, vol. 6, no. 3, 2014, pp. 361–74, doi:<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>.","apa":"Schaefers, L., &#38; Platzner, M. (2014). A Novel Technique and its Application to Computer Go. <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, <i>6</i>(3), 361–374. <a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">https://doi.org/10.1109/TCIAIG.2014.2346997</a>","ieee":"L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, vol. 6, no. 3, pp. 361–374, 2014.","ama":"Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. <i>IEEE Transactions on Computational Intelligence and AI in Games</i>. 2014;6(3):361-374. doi:<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>","short":"L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games 6 (2014) 361–374.","chicago":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” <i>IEEE Transactions on Computational Intelligence and AI in Games</i> 6, no. 3 (2014): 361–74. <a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">https://doi.org/10.1109/TCIAIG.2014.2346997</a>.","bibtex":"@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application to Computer Go}, volume={6}, DOI={<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>}, number={3}, journal={IEEE Transactions on Computational Intelligence and AI in Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374} }"},"date_created":"2019-07-10T09:22:43Z","type":"journal_article","department":[{"_id":"78"}],"title":"A Novel Technique and its Application to Computer Go","status":"public","year":"2014","author":[{"last_name":"Schaefers","first_name":"Lars","full_name":"Schaefers, Lars"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T06:50:47Z","intvolume":"         6","page":"361-374","_id":"10602","language":[{"iso":"eng"}],"doi":"10.1109/TCIAIG.2014.2346997","user_id":"3118","volume":6},{"department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:22:44Z","citation":{"ieee":"H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” <i>IEEE Transactions on Computers</i>, vol. 63, no. 12, pp. 2919–2932, 2014.","apa":"Giefers, H., &#38; Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core. <i>IEEE Transactions on Computers</i>, <i>63</i>(12), 2919–2932. <a href=\"https://doi.org/10.1109/TC.2013.174\">https://doi.org/10.1109/TC.2013.174</a>","chicago":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” <i>IEEE Transactions on Computers</i> 63, no. 12 (2014): 2919–32. <a href=\"https://doi.org/10.1109/TC.2013.174\">https://doi.org/10.1109/TC.2013.174</a>.","short":"H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932.","mla":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” <i>IEEE Transactions on Computers</i>, vol. 63, no. 12, 2014, pp. 2919–32, doi:<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>.","bibtex":"@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh Many-Core}, volume={63}, DOI={<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>}, number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner and Platzner, Marco}, year={2014}, pages={2919–2932} }","ama":"Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. <i>IEEE Transactions on Computers</i>. 2014;63(12):2919-2932. doi:<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>"},"issue":"12","publication":"IEEE Transactions on Computers","volume":63,"user_id":"398","doi":"10.1109/TC.2013.174","_id":"10603","language":[{"iso":"eng"}],"page":"2919 - 2932","intvolume":"        63","date_updated":"2022-01-06T06:50:47Z","author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"title":"An FPGA-based Reconfigurable Mesh Many-Core","status":"public","year":"2014"},{"date_updated":"2022-01-06T06:50:48Z","title":"FPGA Redundancy Configurations: An Automated Design Space Exploration","status":"public","year":"2014","author":[{"full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb","last_name":"Anwer"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"}],"doi":"10.1109/IPDPSW.2014.37","user_id":"3118","language":[{"iso":"eng"}],"_id":"10621","series_title":"RAW","publication":"Reconfigurable Architectures Workshop (RAW)","citation":{"chicago":"Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” In <i>Reconfigurable Architectures Workshop (RAW)</i>. RAW, 2014. <a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">https://doi.org/10.1109/IPDPSW.2014.37</a>.","short":"J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014.","apa":"Anwer, J., Platzner, M., &#38; Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In <i>Reconfigurable Architectures Workshop (RAW)</i>. <a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">https://doi.org/10.1109/IPDPSW.2014.37</a>","ieee":"J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An Automated Design Space Exploration,” in <i>Reconfigurable Architectures Workshop (RAW)</i>, 2014.","ama":"Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: <i>Reconfigurable Architectures Workshop (RAW)</i>. RAW. ; 2014. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>","bibtex":"@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy Configurations: An Automated Design Space Exploration}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>}, booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }","mla":"Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” <i>Reconfigurable Architectures Workshop (RAW)</i>, 2014, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>."},"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T09:32:58Z"},{"citation":{"mla":"Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” <i>Proc. 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(EMBC)","citation":{"chicago":"Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.","short":"A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.","apa":"Boschmann, A., &#38; Platzner, M. (2014). Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>.","ieee":"A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity,” in <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.","ama":"Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In: <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>. ; 2014.","bibtex":"@inproceedings{Boschmann_Platzner_2014, title={Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2014} }","mla":"Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014."},"date_created":"2019-07-10T11:02:59Z","type":"conference","department":[{"_id":"78"}],"status":"public","year":"2014","title":"Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity","author":[{"first_name":"Alexander","last_name":"Boschmann","full_name":"Boschmann, Alexander"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"date_updated":"2022-01-06T06:50:49Z","_id":"10633","language":[{"iso":"eng"}],"user_id":"3118"},{"date_updated":"2022-01-06T06:50:49Z","author":[{"first_name":"Nam","last_name":"Ho","full_name":"Ho, Nam"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"status":"public","title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms","year":"2014","user_id":"3118","doi":"10.1109/FPL.2014.6927437","_id":"10674","language":[{"iso":"eng"}],"page":"1-4","project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"citation":{"chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4.","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>."},"publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"78"}],"keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"],"type":"conference","date_created":"2019-07-10T11:18:01Z"},{"citation":{"mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37, doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i> (pp. 31–37). <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>. ; 2014:31-37. doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }"},"publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","department":[{"_id":"78"}],"type":"conference","keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"date_created":"2019-07-10T11:23:00Z","date_updated":"2022-01-06T06:50:49Z","author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","year":"2014","status":"public","user_id":"3118","doi":"10.1109/ICES.2014.7008719","_id":"10677","language":[{"iso":"eng"}],"page":"31-37"},{"publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","citation":{"mla":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, IEEE, 2014, pp. 177–84, doi:<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>.","bibtex":"@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2014}, pages={177–184} }","ama":"Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>. IEEE; 2014:177-184. doi:<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>","ieee":"J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs,” in <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 2014, pp. 177–184.","apa":"Anwer, J., &#38; Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i> (pp. 177–184). IEEE. <a href=\"https://doi.org/10.1109/DFT.2014.6962108\">https://doi.org/10.1109/DFT.2014.6962108</a>","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 177–84. IEEE, 2014. <a href=\"https://doi.org/10.1109/DFT.2014.6962108\">https://doi.org/10.1109/DFT.2014.6962108</a>.","short":"J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184."},"date_created":"2019-07-10T12:07:05Z","type":"conference","department":[{"_id":"78"}],"status":"public","title":"Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs","year":"2014","author":[{"last_name":"Anwer","first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:50:50Z","page":"177-184","language":[{"iso":"eng"}],"_id":"10764","publisher":"IEEE","doi":"10.1109/DFT.2014.6962108","user_id":"398"},{"department":[{"_id":"78"}],"type":"conference","date_created":"2019-09-09T09:09:31Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"citation":{"mla":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” <i>2014 IEEE Conference on Computational Intelligence and Games</i>, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/CIG.2014.6932863\">10.1109/CIG.2014.6932863</a>.","bibtex":"@inproceedings{Graf_Platzner_2014, title={Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go}, DOI={<a href=\"https://doi.org/10.1109/CIG.2014.6932863\">10.1109/CIG.2014.6932863</a>}, booktitle={2014 IEEE Conference on Computational Intelligence and Games}, author={Graf, Tobias and Platzner, Marco}, year={2014}, pages={1–8} }","ama":"Graf T, Platzner M. Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In: <i>2014 IEEE Conference on Computational Intelligence and Games</i>. ; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/CIG.2014.6932863\">10.1109/CIG.2014.6932863</a>","ieee":"T. Graf and M. Platzner, “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go,” in <i>2014 IEEE Conference on Computational Intelligence and Games</i>, 2014, pp. 1–8.","apa":"Graf, T., &#38; Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In <i>2014 IEEE Conference on Computational Intelligence and Games</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/CIG.2014.6932863\">https://doi.org/10.1109/CIG.2014.6932863</a>","chicago":"Graf, Tobias, and Marco Platzner. “Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go.” In <i>2014 IEEE Conference on Computational Intelligence and Games</i>, 1–8, 2014. <a href=\"https://doi.org/10.1109/CIG.2014.6932863\">https://doi.org/10.1109/CIG.2014.6932863</a>.","short":"T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8."},"publication":"2014 IEEE Conference on Computational Intelligence and Games","user_id":"40778","doi":"10.1109/CIG.2014.6932863","_id":"13154","language":[{"iso":"eng"}],"page":"1-8","date_updated":"2022-01-06T06:51:29Z","author":[{"full_name":"Graf, Tobias","last_name":"Graf","first_name":"Tobias"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"year":"2014","status":"public","title":"Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go"},{"quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"file_date_updated":"2018-03-20T07:29:58Z","citation":{"mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","apa":"Platzner, M., &#38; Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, &#38; T. Kaerlein (Eds.), <i>Logiken strukturbildender Prozesse: Automatismen</i> (pp. 123–144). Wilhelm Fink.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in <i>Logiken strukturbildender Prozesse: Automatismen</i>, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. <i>Logiken strukturbildender Prozesse: Automatismen</i>. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }"},"place":"Paderborn","has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","editor":[{"full_name":"Künsemöller, Jörn","last_name":"Künsemöller","first_name":"Jörn"},{"full_name":"Eke, Norber Otto","first_name":"Norber Otto","last_name":"Eke"},{"full_name":"Foit, Lioba","last_name":"Foit","first_name":"Lioba"},{"full_name":"Kaerlein, Timo","first_name":"Timo","last_name":"Kaerlein"}],"page":"123-144","_id":"335","publisher":"Wilhelm Fink","abstract":[{"text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.","lang":"eng"}],"publication":"Logiken strukturbildender Prozesse: Automatismen","type":"book_chapter","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"file":[{"content_type":"application/pdf","success":1,"file_id":"1424","file_size":2848154,"access_level":"closed","file_name":"335-2014_plessl_automatismen.pdf","date_updated":"2018-03-20T07:29:58Z","relation":"main_file","date_created":"2018-03-20T07:29:58Z","creator":"florida"}],"date_created":"2017-10-17T12:41:57Z","date_updated":"2023-09-26T13:32:49Z","publication_status":"published","year":"2014","title":"Verschiebungen an der Grenze zwischen Hardware und Software","author":[{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl"}],"publication_identifier":{"isbn":["978-3-7705-5730-1"]},"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","language":[{"iso":"ger"}]},{"language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2013.12.001","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Hendrik","last_name":"Hangmann","full_name":"Hangmann, Hendrik"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","year":"2014","intvolume":"        38","date_updated":"2023-09-26T13:33:06Z","date_created":"2017-10-17T12:42:02Z","file":[{"file_size":1499996,"access_level":"closed","file_name":"363-plessl13_micpro.pdf","date_updated":"2018-03-20T07:20:31Z","relation":"main_file","success":1,"content_type":"application/pdf","file_id":"1408","creator":"florida","date_created":"2018-03-20T07:20:31Z"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","issue":"8, Part B","publication":"Microprocessors and Microsystems","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.","lang":"eng"}],"publisher":"Elsevier","_id":"363","page":"911-919","volume":38,"ddc":["040"],"user_id":"15278","status":"public","has_accepted_license":"1","citation":{"short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>."},"file_date_updated":"2018-03-20T07:20:31Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"quality_controlled":"1"},{"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"quality_controlled":"1","citation":{"mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014)."},"file_date_updated":"2018-03-20T07:19:19Z","has_accepted_license":"1","status":"public","volume":7,"ddc":["040"],"user_id":"15278","publisher":"ACM","_id":"365","abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","issue":"2","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"type":"journal_article","date_created":"2017-10-17T12:42:03Z","file":[{"relation":"main_file","date_updated":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf","access_level":"closed","file_size":916052,"file_id":"1406","success":1,"content_type":"application/pdf","creator":"florida","date_created":"2018-03-20T07:19:19Z"}],"intvolume":"         7","date_updated":"2023-09-26T13:33:31Z","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lösch, Achim","last_name":"Lösch","first_name":"Achim","id":"43646"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"year":"2014","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","doi":"10.1145/2617596","language":[{"iso":"eng"}],"article_number":"13"},{"file":[{"content_type":"application/pdf","success":1,"file_id":"1426","file_size":1877185,"access_level":"closed","file_name":"328-plessl14_micro_01.pdf","date_updated":"2018-03-20T07:31:40Z","relation":"main_file","date_created":"2018-03-20T07:31:40Z","creator":"florida"}],"date_created":"2017-10-17T12:41:55Z","type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"IEEE Micro","issue":"1","abstract":[{"text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/MM.2013.110","year":"2014","title":"ReconOS - An Operating System Approach for Reconfigurable Computing","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"full_name":"Keller, Ariane","last_name":"Keller","first_name":"Ariane"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"first_name":"Bernhard","last_name":"Plattner","full_name":"Plattner, Bernhard"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"}],"date_updated":"2023-09-26T13:32:31Z","intvolume":"        34","file_date_updated":"2018-03-20T07:31:40Z","citation":{"short":"A. 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Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","ama":"Agne A, Happe M, Keller A, et al. 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