[{"author":[{"first_name":"Stephanie","last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie"},{"full_name":"Kastens, Uwe","last_name":"Kastens","first_name":"Uwe"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-07-10T09:22:56Z","volume":2010,"publisher":"Hindawi Publishing Corporation","date_updated":"2022-01-06T06:50:47Z","doi":"10.1155/2010/180242","title":"Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification","citation":{"bibtex":"@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={<a href=\"https://doi.org/10.1155/2010/180242\">10.1155/2010/180242</a>}, journal={International Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010} }","short":"S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable Computing 2010 (2010).","mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” <i>International Journal of Reconfigurable Computing</i>, vol. 2010, Hindawi Publishing Corporation, 2010, doi:<a href=\"https://doi.org/10.1155/2010/180242\">10.1155/2010/180242</a>.","apa":"Drzevitzky, S., Kastens, U., &#38; Platzner, M. (2010). Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. <i>International Journal of Reconfigurable Computing</i>, <i>2010</i>. <a href=\"https://doi.org/10.1155/2010/180242\">https://doi.org/10.1155/2010/180242</a>","ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification,” <i>International Journal of Reconfigurable Computing</i>, vol. 2010, 2010.","chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” <i>International Journal of Reconfigurable Computing</i> 2010 (2010). <a href=\"https://doi.org/10.1155/2010/180242\">https://doi.org/10.1155/2010/180242</a>.","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. <i>International Journal of Reconfigurable Computing</i>. 2010;2010. doi:<a href=\"https://doi.org/10.1155/2010/180242\">10.1155/2010/180242</a>"},"intvolume":"      2010","year":"2010","user_id":"3118","department":[{"_id":"78"}],"_id":"10605","language":[{"iso":"eng"}],"type":"journal_article","publication":"International Journal of Reconfigurable Computing","status":"public"},{"page":"6357-6360","citation":{"ieee":"P. Kaufmann, K. Englehart, and M. Platzner, “Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms,” in <i>International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>, 2010, pp. 6357–6360.","chicago":"Kaufmann, Paul, Kevin Englehart, and Marco Platzner. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” In <i>International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>, 6357–60. IEEE, 2010.","ama":"Kaufmann P, Englehart K, Platzner M. Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In: <i>International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>. IEEE; 2010:6357-6360.","apa":"Kaufmann, P., Englehart, K., &#38; Platzner, M. (2010). Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms. In <i>International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i> (pp. 6357–6360). IEEE.","short":"P. Kaufmann, K. Englehart, M. Platzner, in: International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–6360.","mla":"Kaufmann, Paul, et al. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” <i>International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)</i>, IEEE, 2010, pp. 6357–60.","bibtex":"@inproceedings{Kaufmann_Englehart_Platzner_2010, title={Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms}, booktitle={International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)}, publisher={IEEE}, author={Kaufmann, Paul and Englehart, Kevin and Platzner, Marco}, year={2010}, pages={6357–6360} }"},"year":"2010","title":"Fluctuating EMG Signals: Investigating Long-term Effects of Pattern Matching Algorithms","author":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"last_name":"Englehart","full_name":"Englehart, Kevin","first_name":"Kevin"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2019-07-10T11:27:27Z","date_updated":"2022-01-06T06:50:49Z","publisher":"IEEE","status":"public","publication":"International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"3118","_id":"10683"},{"status":"public","publication":"IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)","type":"conference","language":[{"iso":"eng"}],"_id":"10686","department":[{"_id":"78"}],"user_id":"3118","year":"2010","page":"541-548","citation":{"ama":"Kaufmann P, Knieper T, Platzner M. A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In: <i>IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i>. IEEE; 2010:541-548.","chicago":"Kaufmann, Paul, Tobias Knieper, and Marco Platzner. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” In <i>IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i>, 541–48. IEEE, 2010.","ieee":"P. Kaufmann, T. Knieper, and M. Platzner, “A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers,” in <i>IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i>, 2010, pp. 541–548.","apa":"Kaufmann, P., Knieper, T., &#38; Platzner, M. (2010). A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers. In <i>IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i> (pp. 541–548). IEEE.","short":"P. Kaufmann, T. Knieper, M. Platzner, in: IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–548.","bibtex":"@inproceedings{Kaufmann_Knieper_Platzner_2010, title={A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers}, booktitle={IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)}, publisher={IEEE}, author={Kaufmann, Paul and Knieper, Tobias and Platzner, Marco}, year={2010}, pages={541–548} }","mla":"Kaufmann, Paul, et al. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” <i>IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC)</i>, IEEE, 2010, pp. 541–48."},"title":"A Novel Hybrid Evolutionary Strategy and its Periodization with Multi-objective Genetic Optimizers","date_updated":"2022-01-06T06:50:49Z","publisher":"IEEE","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Knieper","full_name":"Knieper, Tobias","first_name":"Tobias"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2019-07-10T11:28:11Z"},{"type":"journal_article","publication":"IET Computers Digital Techniques","status":"public","user_id":"3118","department":[{"_id":"78"}],"_id":"10694","language":[{"iso":"eng"}],"issue":"3","publication_identifier":{"issn":["1751-8601"]},"citation":{"apa":"Kebschull, U., Platzner, M., &#38; Teich, J. (2010). Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). <i>IET Computers Digital Techniques</i>, <i>4</i>(3), 157–158. <a href=\"https://doi.org/10.1049/iet-cdt.2010.9044\">https://doi.org/10.1049/iet-cdt.2010.9044</a>","bibtex":"@article{Kebschull_Platzner_Teich_2010, title={Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}, volume={4}, DOI={<a href=\"https://doi.org/10.1049/iet-cdt.2010.9044\">10.1049/iet-cdt.2010.9044</a>}, number={3}, journal={IET Computers Digital Techniques}, author={Kebschull, Udo and Platzner, Marco and Teich, Jürgen}, year={2010}, pages={157–158} }","mla":"Kebschull, Udo, et al. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” <i>IET Computers Digital Techniques</i>, vol. 4, no. 3, 2010, pp. 157–58, doi:<a href=\"https://doi.org/10.1049/iet-cdt.2010.9044\">10.1049/iet-cdt.2010.9044</a>.","short":"U. Kebschull, M. Platzner, J. Teich, IET Computers Digital Techniques 4 (2010) 157–158.","ama":"Kebschull U, Platzner M, Teich J. Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial). <i>IET Computers Digital Techniques</i>. 2010;4(3):157-158. doi:<a href=\"https://doi.org/10.1049/iet-cdt.2010.9044\">10.1049/iet-cdt.2010.9044</a>","chicago":"Kebschull, Udo, Marco Platzner, and Jürgen Teich. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” <i>IET Computers Digital Techniques</i> 4, no. 3 (2010): 157–58. <a href=\"https://doi.org/10.1049/iet-cdt.2010.9044\">https://doi.org/10.1049/iet-cdt.2010.9044</a>.","ieee":"U. Kebschull, M. Platzner, and J. Teich, “Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial),” <i>IET Computers Digital Techniques</i>, vol. 4, no. 3, pp. 157–158, 2010."},"page":"157-158","intvolume":"         4","year":"2010","date_created":"2019-07-10T11:30:01Z","author":[{"full_name":"Kebschull, Udo","last_name":"Kebschull","first_name":"Udo"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"},{"first_name":"Jürgen","last_name":"Teich","full_name":"Teich, Jürgen"}],"volume":4,"date_updated":"2022-01-06T06:50:49Z","doi":"10.1049/iet-cdt.2010.9044","title":"Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)"},{"author":[{"first_name":"Tobias","full_name":"Knieper, Tobias","last_name":"Knieper"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"last_name":"Glette","full_name":"Glette, Kyrre","first_name":"Kyrre"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"}],"date_created":"2019-07-10T11:38:03Z","volume":6274,"publisher":"Springer","date_updated":"2022-01-06T06:50:49Z","title":"Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture","citation":{"chicago":"Knieper, Tobias, Paul Kaufmann, Kyrre Glette, Marco Platzner, and Jim Torresen. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 6274:250–61. LNCS. Springer, 2010.","ieee":"T. Knieper, P. Kaufmann, K. Glette, M. Platzner, and J. Torresen, “Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture,” in <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 2010, vol. 6274, pp. 250–261.","ama":"Knieper T, Kaufmann P, Glette K, Platzner M, Torresen J. Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In: <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>. Vol 6274. LNCS. Springer; 2010:250-261.","apa":"Knieper, T., Kaufmann, P., Glette, K., Platzner, M., &#38; Torresen, J. (2010). Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i> (Vol. 6274, pp. 250–261). Springer.","short":"T. Knieper, P. Kaufmann, K. Glette, M. Platzner, J. Torresen, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2010, pp. 250–261.","bibtex":"@inproceedings{Knieper_Kaufmann_Glette_Platzner_Torresen_2010, series={LNCS}, title={Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture}, volume={6274}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Knieper, Tobias and Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2010}, pages={250–261}, collection={LNCS} }","mla":"Knieper, Tobias, et al. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, vol. 6274, Springer, 2010, pp. 250–61."},"intvolume":"      6274","page":"250-261","year":"2010","user_id":"3118","series_title":"LNCS","department":[{"_id":"78"}],"_id":"10699","language":[{"iso":"eng"}],"type":"conference","publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","status":"public"},{"author":[{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:41:18Z","date_updated":"2022-01-06T06:50:50Z","publisher":"Springer-Verlag GmbH","doi":"10.1007/978-90-481-3485-4_13","title":"ReconOS: An Operating System for Dynamically Reconfigurable Hardware","citation":{"short":"E. Lübbers, M. Platzner, in: M. Platzner, J. Teich, N. Wehn (Eds.), Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010, pp. 269–290.","bibtex":"@inbook{Lübbers_Platzner_2010, title={ReconOS: An Operating System for Dynamically Reconfigurable Hardware}, DOI={<a href=\"https://doi.org/10.1007/978-90-481-3485-4_13\">10.1007/978-90-481-3485-4_13</a>}, booktitle={Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}, publisher={Springer-Verlag GmbH}, author={Lübbers, Enno and Platzner, Marco}, editor={Platzner, Marco and Teich, Jürgen and Wehn, NorbertEditors}, year={2010}, pages={269–290} }","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>, edited by Marco Platzner et al., Springer-Verlag GmbH, 2010, pp. 269–90, doi:<a href=\"https://doi.org/10.1007/978-90-481-3485-4_13\">10.1007/978-90-481-3485-4_13</a>.","apa":"Lübbers, E., &#38; Platzner, M. (2010). ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In M. Platzner, J. Teich, &#38; N. Wehn (Eds.), <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i> (pp. 269–290). Springer-Verlag GmbH. <a href=\"https://doi.org/10.1007/978-90-481-3485-4_13\">https://doi.org/10.1007/978-90-481-3485-4_13</a>","ama":"Lübbers E, Platzner M. ReconOS: An Operating System for Dynamically Reconfigurable Hardware. In: Platzner M, Teich J, Wehn N, eds. <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH; 2010:269-290. doi:<a href=\"https://doi.org/10.1007/978-90-481-3485-4_13\">10.1007/978-90-481-3485-4_13</a>","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” In <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>, edited by Marco Platzner, Jürgen Teich, and Norbert Wehn, 269–90. Springer-Verlag GmbH, 2010. <a href=\"https://doi.org/10.1007/978-90-481-3485-4_13\">https://doi.org/10.1007/978-90-481-3485-4_13</a>.","ieee":"E. Lübbers and M. Platzner, “ReconOS: An Operating System for Dynamically Reconfigurable Hardware,” in <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>, M. Platzner, J. Teich, and N. Wehn, Eds. Springer-Verlag GmbH, 2010, pp. 269–290."},"page":"269-290","year":"2010","user_id":"3118","department":[{"_id":"78"}],"_id":"10704","language":[{"iso":"eng"}],"type":"book_chapter","publication":"Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications","status":"public","editor":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"full_name":"Teich, Jürgen","last_name":"Teich","first_name":"Jürgen"},{"full_name":"Wehn, Norbert","last_name":"Wehn","first_name":"Norbert"}]},{"title":"Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications","doi":"10.1007/978-90-481-3485-4","date_updated":"2022-01-06T06:50:50Z","publisher":"Springer-Verlag GmbH","date_created":"2019-07-10T12:07:04Z","year":"2010","citation":{"mla":"Platzner, Marco, et al., editors. <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH, 2010, doi:<a href=\"https://doi.org/10.1007/978-90-481-3485-4\">10.1007/978-90-481-3485-4</a>.","bibtex":"@book{Platzner_Teich_Wehn_2010, title={Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications}, DOI={<a href=\"https://doi.org/10.1007/978-90-481-3485-4\">10.1007/978-90-481-3485-4</a>}, publisher={Springer-Verlag GmbH}, year={2010} }","short":"M. Platzner, J. Teich, N. Wehn, eds., Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, Springer-Verlag GmbH, 2010.","apa":"Platzner, M., Teich, J., &#38; Wehn, N. (Eds.). (2010). <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH. <a href=\"https://doi.org/10.1007/978-90-481-3485-4\">https://doi.org/10.1007/978-90-481-3485-4</a>","ama":"Platzner M, Teich J, Wehn N, eds. <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH; 2010. doi:<a href=\"https://doi.org/10.1007/978-90-481-3485-4\">10.1007/978-90-481-3485-4</a>","ieee":"M. Platzner, J. Teich, and N. Wehn, Eds., <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH, 2010.","chicago":"Platzner, Marco, Jürgen Teich, and Norbert Wehn, eds. <i>Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications</i>. Springer-Verlag GmbH, 2010. <a href=\"https://doi.org/10.1007/978-90-481-3485-4\">https://doi.org/10.1007/978-90-481-3485-4</a>."},"publication_identifier":{"isbn":["9048134846"]},"language":[{"iso":"eng"}],"_id":"10763","user_id":"3118","department":[{"_id":"78"}],"editor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"first_name":"Jürgen","full_name":"Teich, Jürgen","last_name":"Teich"},{"last_name":"Wehn","full_name":"Wehn, Norbert","first_name":"Norbert"}],"status":"public","type":"book_editor"},{"_id":"13640","user_id":"398","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)","status":"public","publisher":"IEEE","date_updated":"2022-01-06T06:51:40Z","author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-10-04T22:31:38Z","title":"A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier","year":"2010","citation":{"chicago":"Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” In <i>Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2010.","ieee":"H. Giefers and M. Platzner, “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier,” in <i>Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2010.","ama":"Giefers H, Platzner M. A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In: <i>Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2010.","apa":"Giefers, H., &#38; Platzner, M. (2010). A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. In <i>Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE.","bibtex":"@inproceedings{Giefers_Platzner_2010, title={A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier}, booktitle={Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }","mla":"Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” <i>Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2010.","short":"H. Giefers, M. Platzner, in: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010."}},{"citation":{"mla":"Schäfer, Wilhelm, et al. “Engineering Self-Coordinating Software Intensive Systems.” <i>Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER)</i>, 2010, pp. 321–24.","short":"W. Schäfer, M. Birattari, J. Blömer, M. Dorigo, G. Engels, R. O’Grady, M. Platzner, F.-J. Rammig, W. Reif, A. Trächtler, in: Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.","bibtex":"@inproceedings{Schäfer_Birattari_Blömer_Dorigo_Engels_O’Grady_Platzner_Rammig_Reif_Trächtler_2010, title={Engineering Self-Coordinating Software Intensive Systems}, booktitle={Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER)}, author={Schäfer, Wilhelm and Birattari, Mauro and Blömer, Johannes and Dorigo, Marco and Engels, Gregor and O’Grady, Rehan and Platzner, Marco and Rammig, Franz-Josef and Reif, Wolfgang  and Trächtler, Ansgar}, year={2010}, pages={321–324} }","apa":"Schäfer, W., Birattari, M., Blömer, J., Dorigo, M., Engels, G., O’Grady, R., … Trächtler, A. (2010). Engineering Self-Coordinating Software Intensive Systems. In <i>Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER)</i> (pp. 321–324).","ieee":"W. Schäfer <i>et al.</i>, “Engineering Self-Coordinating Software Intensive Systems,” in <i>Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER)</i>, 2010, pp. 321–324.","chicago":"Schäfer, Wilhelm, Mauro Birattari, Johannes Blömer, Marco Dorigo, Gregor Engels, Rehan O’Grady, Marco Platzner, Franz-Josef Rammig, Wolfgang  Reif, and Ansgar Trächtler. “Engineering Self-Coordinating Software Intensive Systems.” In <i>Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER)</i>, 321–24, 2010.","ama":"Schäfer W, Birattari M, Blömer J, et al. Engineering Self-Coordinating Software Intensive Systems. In: <i>Proceedings of the Foundations of Software Engineering (FSE) and NITR &#38; D/SPD Working Conference on the Future of Software Engineering Research (FoSER)</i>. ; 2010:321-324."},"page":"321-324","year":"2010","author":[{"full_name":"Schäfer, Wilhelm","last_name":"Schäfer","first_name":"Wilhelm"},{"first_name":"Mauro","full_name":"Birattari, Mauro","last_name":"Birattari"},{"first_name":"Johannes","full_name":"Blömer, Johannes","last_name":"Blömer"},{"first_name":"Marco","full_name":"Dorigo, Marco","last_name":"Dorigo"},{"first_name":"Gregor","last_name":"Engels","full_name":"Engels, Gregor"},{"full_name":"O'Grady, Rehan","last_name":"O'Grady","first_name":"Rehan"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"first_name":"Franz-Josef","full_name":"Rammig, Franz-Josef","last_name":"Rammig"},{"first_name":"Wolfgang ","full_name":"Reif, Wolfgang ","last_name":"Reif"},{"full_name":"Trächtler, Ansgar","last_name":"Trächtler","first_name":"Ansgar"}],"date_created":"2019-10-04T22:35:54Z","date_updated":"2022-01-06T06:51:40Z","title":"Engineering Self-Coordinating Software Intensive Systems","type":"conference","publication":"Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER)","status":"public","user_id":"398","department":[{"_id":"78"}],"_id":"13641","language":[{"iso":"eng"}]},{"publication":"Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"398","_id":"13642","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Giefers_Platzner_2010, title={A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics}, booktitle={Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Giefers, Heiner and Platzner, Marco}, year={2010} }","short":"H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.","mla":"Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” <i>Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2010.","apa":"Giefers, H., &#38; Platzner, M. (2010). A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In <i>Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press.","chicago":"Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” In <i>Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.","ieee":"H. Giefers and M. Platzner, “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics,” in <i>Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2010.","ama":"Giefers H, Platzner M. A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. In: <i>Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010."},"year":"2010","author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2019-10-04T22:37:54Z","publisher":"CSREA Press","date_updated":"2022-01-06T06:51:40Z","title":"A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics"},{"author":[{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Ariane","full_name":"Keller, Ariane","last_name":"Keller"},{"full_name":"Plattner, Bernhard","last_name":"Plattner","first_name":"Bernhard"}],"date_created":"2018-04-05T16:27:13Z","publisher":"CSREA Press","date_updated":"2023-09-26T13:48:32Z","title":"Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware","publication_identifier":{"isbn":["1-60132-140-6"]},"quality_controlled":"1","page":"225-231","citation":{"short":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.","bibtex":"@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }","mla":"Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2010, pp. 225–31.","apa":"Lübbers, E., Platzner, M., Plessl, C., Keller, A., &#38; Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 225–231.","chicago":"Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 225–31. CSREA Press, 2010.","ieee":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2010, pp. 225–231.","ama":"Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010:225-231."},"year":"2010","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2223","language":[{"iso":"eng"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference","status":"public"},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2206","language":[{"iso":"eng"}],"type":"conference","publication":"Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)","status":"public","date_created":"2018-04-04T09:36:16Z","author":[{"first_name":"Ariane","last_name":"Keller","full_name":"Keller, Ariane"},{"first_name":"Bernhard","last_name":"Plattner","full_name":"Plattner, Bernhard"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"publisher":"IEEE","date_updated":"2023-09-26T13:51:00Z","doi":"10.1109/GLOCOMW.2010.5700341","title":"Reconfigurable Nodes for Future Networks","publication_identifier":{"isbn":["978-1-4244-8864-3"]},"quality_controlled":"1","citation":{"apa":"Keller, A., Plattner, B., Lübbers, E., Platzner, M., &#38; Plessl, C. (2010). Reconfigurable Nodes for Future Networks. <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 372–376. <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>","mla":"Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, IEEE, 2010, pp. 372–76, doi:<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>.","bibtex":"@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }","short":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.","chicago":"Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian Plessl. “Reconfigurable Nodes for Future Networks.” In <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 372–76. IEEE, 2010. <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>.","ieee":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,” in <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 2010, pp. 372–376, doi: <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>.","ama":"Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>. IEEE; 2010:372-376. doi:<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>"},"page":"372-376","year":"2010"},{"quality_controlled":"1","year":"2010","citation":{"apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &#38; S. Larrabee (Eds.), <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, 2010.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>. ; 2010."},"date_updated":"2023-09-26T13:50:04Z","author":[{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Kauschke, Michael","last_name":"Kauschke","first_name":"Michael"}],"date_created":"2018-04-05T16:43:04Z","title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","type":"conference","publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","editor":[{"first_name":"Omar","last_name":"Hammami","full_name":"Hammami, Omar"},{"full_name":"Larrabee, Sandra","last_name":"Larrabee","first_name":"Sandra"}],"status":"public","_id":"2228","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"user_id":"3118","department":[{"_id":"78"}],"_id":"10639","status":"public","type":"conference","publication":"Proc. Technically Assisted Rehabilitation (TAR)","title":"Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets","date_created":"2019-07-10T11:03:25Z","author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"last_name":"Winkler","full_name":"Winkler, Michael","first_name":"Michael"}],"date_updated":"2022-01-06T06:50:49Z","citation":{"ama":"Boschmann A, Kaufmann P, Platzner M, Winkler M. Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In: <i>Proc. Technically Assisted Rehabilitation (TAR)</i>. ; 2009.","ieee":"A. Boschmann, P. Kaufmann, M. Platzner, and M. Winkler, “Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets,” in <i>Proc. Technically Assisted Rehabilitation (TAR)</i>, 2009.","chicago":"Boschmann, Alexander, Paul Kaufmann, Marco Platzner, and Michael Winkler. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” In <i>Proc. Technically Assisted Rehabilitation (TAR)</i>, 2009.","short":"A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically Assisted Rehabilitation (TAR), 2009.","mla":"Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” <i>Proc. Technically Assisted Rehabilitation (TAR)</i>, 2009.","bibtex":"@inproceedings{Boschmann_Kaufmann_Platzner_Winkler_2009, title={Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets}, booktitle={Proc. Technically Assisted Rehabilitation (TAR)}, author={Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}, year={2009} }","apa":"Boschmann, A., Kaufmann, P., Platzner, M., &#38; Winkler, M. (2009). Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets. In <i>Proc. Technically Assisted Rehabilitation (TAR)</i>."},"year":"2009"},{"doi":"10.1145/1596532.1596540","title":"ReconOS: Multithreaded Programming for Reconfigurable Computers","date_created":"2019-07-10T11:41:17Z","author":[{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"volume":9,"date_updated":"2022-01-06T06:50:50Z","citation":{"ieee":"E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no. 1, pp. 8:1-8:33, 2009.","chicago":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i> 9, no. 1 (2009): 8:1-8:33. <a href=\"https://doi.org/10.1145/1596532.1596540\">https://doi.org/10.1145/1596532.1596540</a>.","ama":"Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>. 2009;9(1):8:1-8:33. doi:<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>","bibtex":"@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming for Reconfigurable Computers}, volume={9}, DOI={<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers, Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }","short":"E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33.","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>.","apa":"Lübbers, E., &#38; Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>, <i>9</i>(1), 8:1-8:33. <a href=\"https://doi.org/10.1145/1596532.1596540\">https://doi.org/10.1145/1596532.1596540</a>"},"intvolume":"         9","page":"8:1-8:33","year":"2009","issue":"1","publication_identifier":{"issn":["1539-9087"]},"language":[{"iso":"eng"}],"keyword":["Reconfigurable computing","multithreading","operating systems"],"user_id":"3118","department":[{"_id":"78"}],"_id":"10703","status":"public","type":"journal_article","publication":"ACM Transactions on Embedded Computing Systems"},{"department":[{"_id":"78"}],"user_id":"398","_id":"13632","language":[{"iso":"eng"}],"publication":"Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)","type":"conference","status":"public","date_created":"2019-10-04T22:13:24Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"publisher":"Springer","date_updated":"2022-01-06T06:51:40Z","title":"A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms","citation":{"apa":"Happe, M., Lübbers, E., &#38; Platzner, M. (2009). A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer.","mla":"Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, Springer, 2009.","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.","bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}, booktitle={Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }","ieee":"M. Happe, E. Lübbers, and M. Platzner, “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms,” in <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>, 2009.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” In <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer, 2009.","ama":"Happe M, Lübbers E, Platzner M. A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. In: <i>Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)</i>. Springer; 2009."},"year":"2009"},{"_id":"13634","department":[{"_id":"78"}],"user_id":"398","language":[{"iso":"eng"}],"publication":"Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)","type":"conference","status":"public","date_updated":"2022-01-06T06:51:40Z","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-10-04T22:16:01Z","title":"Towards Models for Many-Cores: The Case for the Reconfigurable Mesh","year":"2009","citation":{"ieee":"H. Giefers and M. Platzner, “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh,” in <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.","chicago":"Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” In <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.","ama":"Giefers H, Platzner M. Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In: <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>. ; 2009.","apa":"Giefers, H., &#38; Platzner, M. (2009). Towards Models for Many-Cores: The Case for the Reconfigurable Mesh. In <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>.","mla":"Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” <i>Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)</i>, 2009.","short":"H. Giefers, M. Platzner, in: Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}, booktitle={Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }"}},{"citation":{"chicago":"Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” In <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>. IEEE, 2009.","ieee":"H. Giefers and M. Platzner, “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores,” in <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>, 2009.","ama":"Giefers H, Platzner M. ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In: <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>. IEEE; 2009.","apa":"Giefers, H., &#38; Platzner, M. (2009). ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores. In <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>. IEEE.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}, booktitle={Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }","mla":"Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” <i>Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium</i>, IEEE, 2009.","short":"H. Giefers, M. Platzner, in: Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009."},"year":"2009","date_created":"2019-10-04T22:17:57Z","author":[{"full_name":"Giefers, Heiner","last_name":"Giefers","first_name":"Heiner"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"publisher":"IEEE","date_updated":"2022-01-06T06:51:40Z","title":"ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores","type":"conference","publication":"Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium","status":"public","user_id":"398","department":[{"_id":"78"}],"_id":"13635","language":[{"iso":"eng"}]},{"citation":{"ama":"Lübbers E, Platzner M. Cooperative Multithreading in Dynamically Reconfigurable Systems. In: <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE; 2009.","chicago":"Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE, 2009.","ieee":"E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable Systems,” in <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, 2009.","apa":"Lübbers, E., &#38; Platzner, M. (2009). Cooperative Multithreading in Dynamically Reconfigurable Systems. In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE.","bibtex":"@inproceedings{Lübbers_Platzner_2009, title={Cooperative Multithreading in Dynamically Reconfigurable Systems}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2009} }","short":"E. Lübbers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","mla":"Lübbers, Enno, and Marco Platzner. “Cooperative Multithreading in Dynamically Reconfigurable Systems.” <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, IEEE, 2009."},"year":"2009","title":"Cooperative Multithreading in Dynamically Reconfigurable Systems","author":[{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-10-04T22:20:12Z","publisher":"IEEE","date_updated":"2022-01-06T06:51:40Z","status":"public","publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"398","_id":"13636"},{"citation":{"ieee":"H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, 2009.","chicago":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE, 2009.","ama":"Giefers H, Platzner M. Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In: <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE; 2009.","apa":"Giefers, H., &#38; Platzner, M. (2009). Program-driven Fine-grained Power Management for the Reconfigurable Mesh. In <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>. IEEE.","short":"H. Giefers, M. Platzner, in: Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , IEEE, 2009.","bibtex":"@inproceedings{Giefers_Platzner_2009, title={Program-driven Fine-grained Power Management for the Reconfigurable Mesh}, booktitle={Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2009} }","mla":"Giefers, Heiner, and Marco Platzner. “Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh.” <i>Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) </i>, IEEE, 2009."},"year":"2009","title":"Program-driven Fine-grained Power Management for the Reconfigurable Mesh","author":[{"full_name":"Giefers, Heiner","last_name":"Giefers","first_name":"Heiner"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_created":"2019-10-04T22:22:02Z","date_updated":"2022-01-06T06:51:40Z","publisher":"IEEE","status":"public","publication":"Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) ","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"398","_id":"13637"}]