[{"doi":"10.1109/fpt.2009.5377645","title":"An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning","date_created":"2019-10-04T22:22:52Z","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2022-01-06T06:51:40Z","publisher":"IEEE","citation":{"ama":"Happe M, Lübbers E, Platzner M. An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In: <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2009. doi:<a href=\"https://doi.org/10.1109/fpt.2009.5377645\">10.1109/fpt.2009.5377645</a>","ieee":"M. Happe, E. Lübbers, and M. Platzner, “An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning,” in <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>, 2009.","chicago":"Happe, Markus, Enno Lübbers, and Marco Platzner. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” In <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>. IEEE, 2009. <a href=\"https://doi.org/10.1109/fpt.2009.5377645\">https://doi.org/10.1109/fpt.2009.5377645</a>.","apa":"Happe, M., Lübbers, E., &#38; Platzner, M. (2009). An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning. In <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>. IEEE. <a href=\"https://doi.org/10.1109/fpt.2009.5377645\">https://doi.org/10.1109/fpt.2009.5377645</a>","short":"M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT), IEEE, 2009.","mla":"Happe, Markus, et al. “An Adaptive Sequential Monte Carlo Framework with Runtime HW/SW Repartitioning.” <i>Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2009, doi:<a href=\"https://doi.org/10.1109/fpt.2009.5377645\">10.1109/fpt.2009.5377645</a>.","bibtex":"@inproceedings{Happe_Lübbers_Platzner_2009, title={An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}, DOI={<a href=\"https://doi.org/10.1109/fpt.2009.5377645\">10.1109/fpt.2009.5377645</a>}, booktitle={Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2009} }"},"year":"2009","publication_status":"published","publication_identifier":{"isbn":["9781424443758"]},"language":[{"iso":"eng"}],"user_id":"398","department":[{"_id":"78"}],"_id":"13638","status":"public","type":"conference","publication":"Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)"},{"status":"public","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","type":"conference","language":[{"iso":"eng"}],"_id":"13639","department":[{"_id":"78"}],"user_id":"398","year":"2009","citation":{"chicago":"Drzevitzky, Stephanie, Uwe Kastens, and Marco Platzner. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE, 2009.","ieee":"S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009.","ama":"Drzevitzky S, Kastens U, Platzner M. Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2009.","apa":"Drzevitzky, S., Kastens, U., &#38; Platzner, M. (2009). Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE.","mla":"Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2009.","short":"S. Drzevitzky, U. Kastens, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2009.","bibtex":"@inproceedings{Drzevitzky_Kastens_Platzner_2009, title={Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2009} }"},"title":"Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules","date_updated":"2022-01-06T06:51:40Z","publisher":"IEEE","date_created":"2019-10-04T22:25:10Z","author":[{"last_name":"Drzevitzky","full_name":"Drzevitzky, Stephanie","first_name":"Stephanie"},{"last_name":"Kastens","full_name":"Kastens, Uwe","first_name":"Uwe"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}]},{"language":[{"iso":"eng"}],"keyword":["IMORC","interconnect","performance"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2350","status":"public","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"type":"conference","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","doi":"10.1109/FCCM.2009.25","title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","date_created":"2018-04-16T15:05:52Z","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_updated":"2023-09-26T13:51:44Z","publisher":"IEEE Computer Society","citation":{"bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78, doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–278. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278, doi: <a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–78. IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2009:275-278. doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>"},"page":"275-278","year":"2009","quality_controlled":"1","publication_identifier":{"isbn":["978-1-4244-4450-2"]}},{"quality_controlled":"1","citation":{"apa":"Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, IEEE Computer Society, 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>. IEEE Computer Society; 2009:11-18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 2009, pp. 11–18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009."},"page":"11-18","place":"Los Alamitos, CA, USA","year":"2009","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2018-04-06T15:18:24Z","date_updated":"2023-09-26T13:53:11Z","publisher":"IEEE Computer Society","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","type":"conference","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","status":"public","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2262","language":[{"iso":"eng"}],"keyword":["EvoCache","evolvable hardware","computer architecture"]},{"language":[{"iso":"eng"}],"keyword":["IMORC","graphics"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2238","status":"public","type":"conference","publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2009.32","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","date_created":"2018-04-05T17:11:28Z","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"last_name":"Süß","full_name":"Süß, Tim","first_name":"Tim"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_updated":"2023-09-26T13:52:32Z","publisher":"IEEE Computer Society","citation":{"ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124. doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124, doi: <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }"},"page":"119-124","year":"2009","place":"Los Alamitos, CA, USA","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"quality_controlled":"1"},{"date_created":"2018-04-06T15:15:47Z","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"publisher":"IEEE","date_updated":"2023-09-26T13:52:52Z","title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","quality_controlled":"1","publication_identifier":{"issn":["1946-1488"],"isbn":["978-1-4244-3892-1"]},"page":"338-344","citation":{"apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–344.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–44. IEEE, 2009.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2009:338-344."},"year":"2009","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2261","language":[{"iso":"eng"}],"keyword":["IMORC","NOC","KNN","accelerator"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","type":"conference","status":"public"},{"status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference","_id":"2365","department":[{"_id":"27"},{"_id":"78"}],"user_id":"24135","year":"2008","page":"245-251","citation":{"short":"M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","bibtex":"@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }","mla":"Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51.","apa":"Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 245–251). CSREA Press.","chicago":"Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.","ieee":"M. Platzner <i>et al.</i>, “The GOmputer: Accelerating GO with FPGAs,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008, pp. 245–251.","ama":"Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251."},"publication_identifier":{"isbn":["1-60132-064-7"]},"title":"The GOmputer: Accelerating GO with FPGAs","date_updated":"2022-01-06T06:55:58Z","publisher":"CSREA Press","author":[{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"first_name":"Sven","last_name":"Döhre","full_name":"Döhre, Sven"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"full_name":"Lorenz, Ulf","last_name":"Lorenz","first_name":"Ulf"},{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Andre","full_name":"Send, Andre","last_name":"Send"},{"first_name":"Alexander","last_name":"Warkentin","full_name":"Warkentin, Alexander"}],"date_created":"2018-04-17T11:34:35Z"},{"type":"conference","publication":"IEEE Adaptive Hardware and Systems (AHS)","status":"public","_id":"10653","user_id":"3118","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"year":"2008","citation":{"ama":"Glette K, Gruber T, Kaufmann P, Torresen J, Sick B, Platzner M. Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In: <i>IEEE Adaptive Hardware and Systems (AHS)</i>. IEEE; 2008:32-39.","ieee":"K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner, “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control,” in <i>IEEE Adaptive Hardware and Systems (AHS)</i>, 2008, pp. 32–39.","chicago":"Glette, Kyrre, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick, and Marco Platzner. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” In <i>IEEE Adaptive Hardware and Systems (AHS)</i>, 32–39. IEEE, 2008.","apa":"Glette, K., Gruber, T., Kaufmann, P., Torresen, J., Sick, B., &#38; Platzner, M. (2008). Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. In <i>IEEE Adaptive Hardware and Systems (AHS)</i> (pp. 32–39). IEEE.","short":"K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, M. Platzner, in: IEEE Adaptive Hardware and Systems (AHS), IEEE, 2008, pp. 32–39.","bibtex":"@inproceedings{Glette_Gruber_Kaufmann_Torresen_Sick_Platzner_2008, title={Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}, booktitle={IEEE Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}, year={2008}, pages={32–39} }","mla":"Glette, Kyrre, et al. “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control.” <i>IEEE Adaptive Hardware and Systems (AHS)</i>, IEEE, 2008, pp. 32–39."},"page":"32-39","date_updated":"2022-01-06T06:50:49Z","publisher":"IEEE","author":[{"full_name":"Glette, Kyrre","last_name":"Glette","first_name":"Kyrre"},{"last_name":"Gruber","full_name":"Gruber, Thiemo","first_name":"Thiemo"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"full_name":"Torresen, Jim","last_name":"Torresen","first_name":"Jim"},{"last_name":"Sick","full_name":"Sick, Bernhard","first_name":"Bernhard"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-07-10T11:13:13Z","title":"Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control"},{"date_created":"2019-07-10T11:13:31Z","author":[{"full_name":"Glette, Kyrre","last_name":"Glette","first_name":"Kyrre"},{"last_name":"Torresen","full_name":"Torresen, Jim","first_name":"Jim"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"volume":5216,"date_updated":"2022-01-06T06:50:49Z","publisher":"Springer","title":"A Comparison of Evolvable Hardware Architectures for Classification Tasks","citation":{"apa":"Glette, K., Torresen, J., Kaufmann, P., &#38; Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i> (Vol. 5216, pp. 22–33). Springer.","mla":"Glette, Kyrre, et al. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, vol. 5216, Springer, 2008, pp. 22–33.","bibtex":"@inproceedings{Glette_Torresen_Kaufmann_Platzner_2008, series={LNCS}, title={A Comparison of Evolvable Hardware Architectures for Classification Tasks}, volume={5216}, booktitle={IEEE Intl. Conf. on Evolvable Systems (ICES)}, publisher={Springer}, author={Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={22–33}, collection={LNCS} }","short":"K. Glette, J. Torresen, P. Kaufmann, M. Platzner, in: IEEE Intl. Conf. on Evolvable Systems (ICES), Springer, 2008, pp. 22–33.","chicago":"Glette, Kyrre, Jim Torresen, Paul Kaufmann, and Marco Platzner. “A Comparison of Evolvable Hardware Architectures for Classification Tasks.” In <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 5216:22–33. LNCS. Springer, 2008.","ieee":"K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>, 2008, vol. 5216, pp. 22–33.","ama":"Glette K, Torresen J, Kaufmann P, Platzner M. A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: <i>IEEE Intl. Conf. on Evolvable Systems (ICES)</i>. Vol 5216. LNCS. Springer; 2008:22-33."},"page":"22-33","intvolume":"      5216","year":"2008","series_title":"LNCS","user_id":"3118","department":[{"_id":"78"}],"_id":"10656","language":[{"iso":"eng"}],"type":"conference","publication":"IEEE Intl. Conf. on Evolvable Systems (ICES)","status":"public"},{"citation":{"bibtex":"@article{Torresen_Glette_Platzner_Kaufmann_2008, title={Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}, author={Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}, year={2008} }","mla":"Torresen, Jim, et al. <i>Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)</i>. 2008.","short":"J. Torresen, K. Glette, M. Platzner, P. Kaufmann, (2008).","apa":"Torresen, J., Glette, K., Platzner, M., &#38; Kaufmann, P. (2008). Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).","ama":"Torresen J, Glette K, Platzner M, Kaufmann P. Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS). 2008.","ieee":"J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008.","chicago":"Torresen, Jim, Kyrre Glette, Marco Platzner, and Paul Kaufmann. “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS),” 2008."},"year":"2008","date_created":"2019-07-10T11:29:14Z","author":[{"first_name":"Jim","full_name":"Torresen, Jim","last_name":"Torresen"},{"first_name":"Kyrre","last_name":"Glette","full_name":"Glette, Kyrre"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"}],"date_updated":"2022-01-06T06:50:49Z","title":"Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)","type":"preprint","status":"public","department":[{"_id":"78"}],"user_id":"398","_id":"10690","language":[{"iso":"eng"}]},{"type":"conference","publication":"Genetic and Evolutionary Computation (GECCO)","status":"public","_id":"10691","user_id":"3118","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"year":"2008","citation":{"short":"P. Kaufmann, M. Platzner, in: Genetic and Evolutionary Computation (GECCO), ACM Press, 2008, pp. 1219–1226.","bibtex":"@inproceedings{Kaufmann_Platzner_2008, title={Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}, booktitle={Genetic and Evolutionary Computation (GECCO)}, publisher={ACM Press}, author={Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={1219–1226} }","mla":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” <i>Genetic and Evolutionary Computation (GECCO)</i>, ACM Press, 2008, pp. 1219–26.","apa":"Kaufmann, P., &#38; Platzner, M. (2008). Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In <i>Genetic and Evolutionary Computation (GECCO)</i> (pp. 1219–1226). ACM Press.","chicago":"Kaufmann, Paul, and Marco Platzner. “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming.” In <i>Genetic and Evolutionary Computation (GECCO)</i>, 1219–26. ACM Press, 2008.","ieee":"P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in <i>Genetic and Evolutionary Computation (GECCO)</i>, 2008, pp. 1219–1226.","ama":"Kaufmann P, Platzner M. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming. In: <i>Genetic and Evolutionary Computation (GECCO)</i>. ACM Press; 2008:1219-1226."},"page":"1219 - 1226","publisher":"ACM Press","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:29:57Z","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"title":"Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming"},{"author":[{"last_name":"Giefers","full_name":"Giefers, Heiner","first_name":"Heiner"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2019-10-04T22:05:22Z","publisher":"IEEE","date_updated":"2022-01-06T06:51:40Z","title":"Realizing Reconfigurable Mesh Algorithms on Softcore Arrays","citation":{"chicago":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” In <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>. IEEE, 2008.","ieee":"H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>, 2008.","ama":"Giefers H, Platzner M. Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In: <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>. IEEE; 2008.","mla":"Giefers, Heiner, and Marco Platzner. “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays.” <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>, IEEE, 2008.","short":"H. Giefers, M. Platzner, in: Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), IEEE, 2008.","bibtex":"@inproceedings{Giefers_Platzner_2008, title={Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}, booktitle={Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}, publisher={IEEE}, author={Giefers, Heiner and Platzner, Marco}, year={2008} }","apa":"Giefers, H., &#38; Platzner, M. (2008). Realizing Reconfigurable Mesh Algorithms on Softcore Arrays. In <i>Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)</i>. IEEE."},"year":"2008","department":[{"_id":"78"}],"user_id":"398","_id":"13629","language":[{"iso":"eng"}],"publication":"Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)","type":"conference","status":"public"},{"title":"Communication and Synchronization in Multithreaded Reconfigurable Computing Systems","publisher":"CSREA Press","date_updated":"2022-01-06T06:51:40Z","date_created":"2019-10-04T22:07:14Z","author":[{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"year":"2008","citation":{"ieee":"E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008.","chicago":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” In <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press, 2008.","ama":"Lübbers E, Platzner M. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In: <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008.","apa":"Lübbers, E., &#38; Platzner, M. (2008). Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. In <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press.","mla":"Lübbers, Enno, and Marco Platzner. “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems.” <i>Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008.","bibtex":"@inproceedings{Lübbers_Platzner_2008, title={Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}, booktitle={Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","short":"E. Lübbers, M. Platzner, in: Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008."},"language":[{"iso":"eng"}],"_id":"13630","department":[{"_id":"78"}],"user_id":"398","status":"public","publication":"Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference"},{"status":"public","publication":"Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)","type":"conference","language":[{"iso":"eng"}],"_id":"13631","department":[{"_id":"78"}],"user_id":"398","year":"2008","citation":{"bibtex":"@inproceedings{Lübbers_Platzner_2008, title={A portable abstraction layer for hardware threads}, DOI={<a href=\"https://doi.org/10.1109/fpl.2008.4629901\">10.1109/fpl.2008.4629901</a>}, booktitle={Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Lübbers, Enno and Platzner, Marco}, year={2008} }","mla":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2008, doi:<a href=\"https://doi.org/10.1109/fpl.2008.4629901\">10.1109/fpl.2008.4629901</a>.","short":"E. Lübbers, M. Platzner, in: Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2008.","apa":"Lübbers, E., &#38; Platzner, M. (2008). A portable abstraction layer for hardware threads. In <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE. <a href=\"https://doi.org/10.1109/fpl.2008.4629901\">https://doi.org/10.1109/fpl.2008.4629901</a>","chicago":"Lübbers, Enno, and Marco Platzner. “A Portable Abstraction Layer for Hardware Threads.” In <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2008. <a href=\"https://doi.org/10.1109/fpl.2008.4629901\">https://doi.org/10.1109/fpl.2008.4629901</a>.","ieee":"E. Lübbers and M. Platzner, “A portable abstraction layer for hardware threads,” in <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2008.","ama":"Lübbers E, Platzner M. A portable abstraction layer for hardware threads. In: <i>Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2008. doi:<a href=\"https://doi.org/10.1109/fpl.2008.4629901\">10.1109/fpl.2008.4629901</a>"},"publication_identifier":{"isbn":["9781424419609"]},"publication_status":"published","title":"A portable abstraction layer for hardware threads","doi":"10.1109/fpl.2008.4629901","date_updated":"2022-01-06T06:51:40Z","publisher":"IEEE","author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2019-10-04T22:07:43Z"},{"language":[{"iso":"eng"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2364","status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","type":"conference","title":"A Hardware Accelerator for k-th Nearest Neighbor Thinning","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"first_name":"Robert","last_name":"Meiche","full_name":"Meiche, Robert"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2018-04-17T11:33:32Z","date_updated":"2023-09-26T13:54:24Z","publisher":"CSREA Press","page":"245-251","citation":{"ama":"Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251.","ieee":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008, pp. 245–251.","chicago":"Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51.","short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }","apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &#38; Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–251."},"year":"2008","publication_identifier":{"isbn":["1-60132-064-7"]},"quality_controlled":"1"},{"title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","date_created":"2018-04-17T12:05:28Z","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_updated":"2023-09-26T13:55:51Z","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>. ; 2008.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }"},"year":"2008","quality_controlled":"1","language":[{"iso":"eng"}],"keyword":["IMORC","IP core","interconnect"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2372","status":"public","type":"conference","publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)"},{"type":"conference","publication":"Biologically Inspired Collaborative Computing (BICC)","status":"public","user_id":"14972","series_title":"IFIP International Federation for Information Processing","department":[{"_id":"78"}],"_id":"10698","language":[{"iso":"eng"}],"citation":{"mla":"Knieper, Tobias, et al. “On Robust Evolution of Digital Hardware.” <i>Biologically Inspired Collaborative Computing (BICC)</i>, vol. 268, Springer, 2008, pp. 213–22, doi:<a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>.","short":"T. Knieper, B. Defo, P. Kaufmann, M. Platzner, in: Biologically Inspired Collaborative Computing (BICC), Springer, 2008, pp. 213–222.","bibtex":"@inproceedings{Knieper_Defo_Kaufmann_Platzner_2008, series={IFIP International Federation for Information Processing}, title={On Robust Evolution of Digital Hardware}, volume={268}, DOI={<a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>}, booktitle={Biologically Inspired Collaborative Computing (BICC)}, publisher={Springer}, author={Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}, year={2008}, pages={213–222}, collection={IFIP International Federation for Information Processing} }","ama":"Knieper T, Defo B, Kaufmann P, Platzner M. On Robust Evolution of Digital Hardware. In: <i>Biologically Inspired Collaborative Computing (BICC)</i>. Vol 268. IFIP International Federation for Information Processing. Springer; 2008:213-222. doi:<a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>","apa":"Knieper, T., Defo, B., Kaufmann, P., &#38; Platzner, M. (2008). On Robust Evolution of Digital Hardware. <i>Biologically Inspired Collaborative Computing (BICC)</i>, <i>268</i>, 213–222. <a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">https://doi.org/10.1007/978-0-387-09655-1_19</a>","chicago":"Knieper, Tobias, Bertrand Defo, Paul Kaufmann, and Marco Platzner. “On Robust Evolution of Digital Hardware.” In <i>Biologically Inspired Collaborative Computing (BICC)</i>, 268:213–22. IFIP International Federation for Information Processing. Springer, 2008. <a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">https://doi.org/10.1007/978-0-387-09655-1_19</a>.","ieee":"T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in <i>Biologically Inspired Collaborative Computing (BICC)</i>, 2008, vol. 268, pp. 213–222, doi: <a href=\"https://doi.org/10.1007/978-0-387-09655-1_19\">10.1007/978-0-387-09655-1_19</a>."},"page":"213-222","intvolume":"       268","year":"2008","author":[{"first_name":"Tobias","full_name":"Knieper, Tobias","last_name":"Knieper"},{"first_name":"Bertrand","last_name":"Defo","full_name":"Defo, Bertrand"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-07-10T11:38:02Z","volume":268,"date_updated":"2026-02-19T08:35:12Z","publisher":"Springer","doi":"10.1007/978-0-387-09655-1_19","title":"On Robust Evolution of Digital Hardware"},{"publisher":"IEEE","date_updated":"2022-01-06T07:03:08Z","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-01-08T09:52:43Z","title":"MOVES: A Modular Framework for Hardware Evolution","doi":"10.1109/ahs.2007.73","conference":{"location":"Edinburgh, UK","end_date":"2007-08-08","start_date":"2007-08-05","name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)"},"publication_identifier":{"isbn":["076952866X","9780769528663"]},"publication_status":"published","year":"2007","page":"447-454","citation":{"apa":"Kaufmann, P., &#38; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i> (pp. 447–454). Edinburgh, UK: IEEE. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, IEEE, 2007, pp. 447–54, doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }","short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>. IEEE; 2007:447-454. doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, Edinburgh, UK, 2007, pp. 447–454.","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, 447–54. IEEE, 2007. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>."},"_id":"6508","department":[{"_id":"78"}],"user_id":"3118","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"language":[{"iso":"eng"}],"publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","type":"conference","abstract":[{"text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.","lang":"eng"}],"status":"public"},{"year":"2007","page":"1-2","intvolume":"      2007","citation":{"chicago":"Bergmann, Neil, Marco Platzner, and Jürgen Teich. “Dynamically Reconfigurable Architectures (Editorial).” <i>{EURASIP} Journal on Embedded Systems</i> 2007 (2007): 1–2. <a href=\"https://doi.org/10.1155/2007/28405\">https://doi.org/10.1155/2007/28405</a>.","ieee":"N. Bergmann, M. Platzner, and J. Teich, “Dynamically Reconfigurable Architectures (editorial),” <i>{EURASIP} Journal on Embedded Systems</i>, vol. 2007, pp. 1–2, 2007.","ama":"Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). <i>{EURASIP} Journal on Embedded Systems</i>. 2007;2007:1-2. doi:<a href=\"https://doi.org/10.1155/2007/28405\">10.1155/2007/28405</a>","bibtex":"@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={<a href=\"https://doi.org/10.1155/2007/28405\">10.1155/2007/28405</a>}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }","short":"N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems 2007 (2007) 1–2.","mla":"Bergmann, Neil, et al. “Dynamically Reconfigurable Architectures (Editorial).” <i>{EURASIP} Journal on Embedded Systems</i>, vol. 2007, Springer Science+Business Media, 2007, pp. 1–2, doi:<a href=\"https://doi.org/10.1155/2007/28405\">10.1155/2007/28405</a>.","apa":"Bergmann, N., Platzner, M., &#38; Teich, J. (2007). Dynamically Reconfigurable Architectures (editorial). <i>{EURASIP} Journal on Embedded Systems</i>, <i>2007</i>, 1–2. <a href=\"https://doi.org/10.1155/2007/28405\">https://doi.org/10.1155/2007/28405</a>"},"publisher":"Springer Science+Business Media","date_updated":"2022-01-06T06:50:48Z","volume":2007,"author":[{"first_name":"Neil","last_name":"Bergmann","full_name":"Bergmann, Neil"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"first_name":"Jürgen","full_name":"Teich, Jürgen","last_name":"Teich"}],"date_created":"2019-07-10T09:40:11Z","title":"Dynamically Reconfigurable Architectures (editorial)","doi":"10.1155/2007/28405","publication":"{EURASIP} Journal on Embedded Systems","type":"journal_article","status":"public","_id":"10625","department":[{"_id":"78"}],"user_id":"398","language":[{"iso":"eng"}]},{"citation":{"ieee":"K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic tasks on dynamically reconfigurable hardware,” <i>IET Computers Digital Techniques</i>, vol. 1, no. 4, pp. 295–302, 2007.","chicago":"Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i> 1, no. 4 (2007): 295–302. <a href=\"https://doi.org/10.1049/iet-cdt:20060186\">https://doi.org/10.1049/iet-cdt:20060186</a>.","ama":"Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>. 2007;1(4):295-302. doi:<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>","short":"K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1 (2007) 295–302.","mla":"Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i>, vol. 1, no. 4, 2007, pp. 295–302, doi:<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>.","bibtex":"@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={<a href=\"https://doi.org/10.1049/iet-cdt:20060186\">10.1049/iet-cdt:20060186</a>}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }","apa":"Danne, K., Mühlenbernd, R., &#38; Platzner, M. (2007). Server-based execution of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>, <i>1</i>(4), 295–302. <a href=\"https://doi.org/10.1049/iet-cdt:20060186\">https://doi.org/10.1049/iet-cdt:20060186</a>"},"page":"295-302","intvolume":"         1","year":"2007","issue":"4","publication_identifier":{"issn":["1751-8601"]},"doi":"10.1049/iet-cdt:20060186","title":"Server-based execution of periodic tasks on dynamically reconfigurable hardware","author":[{"last_name":"Danne","full_name":"Danne, Klaus","first_name":"Klaus"},{"first_name":"Roland","last_name":"Mühlenbernd","full_name":"Mühlenbernd, Roland"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-07-10T11:10:54Z","volume":1,"date_updated":"2022-01-06T06:50:49Z","status":"public","type":"journal_article","publication":"IET Computers Digital Techniques","language":[{"iso":"eng"}],"keyword":["reconfigurable architectures","resource allocation","device reconfiguration time","dynamic hardware reconfiguration","dynamically reconfigurable hardware","light-weight runtime system","merge server distribute load","periodic real-time tasks","runtime system overheads","schedulability analysis","scheduling technique","server-based execution","synthesis tool flow"],"user_id":"3118","department":[{"_id":"78"}],"_id":"10646"}]