[{"citation":{"mla":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>.","ama":"Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>","bibtex":"@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}, DOI={<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>}, booktitle={2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and Platzner, Marco}, year={2018} }","apa":"Lösch, A., &#38; Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In <i>2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. Milan, Italy: IEEE. <a href=\"https://doi.org/10.1109/asap.2018.8445098\">https://doi.org/10.1109/asap.2018.8445098</a>","ieee":"A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in <i>2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, Milan, Italy, 2018.","short":"A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018.","chicago":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” In <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/asap.2018.8445098\">https://doi.org/10.1109/asap.2018.8445098</a>."},"file_date_updated":"2018-11-14T09:40:42Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"}],"conference":{"end_date":"2018-07-12","location":"Milan, Italy","start_date":"2018-07-10","name":"The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors"},"status":"public","has_accepted_license":"1","_id":"5547","publisher":"IEEE","user_id":"43646","ddc":["040"],"publication":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","date_created":"2018-11-14T09:26:53Z","file":[{"date_created":"2018-11-14T09:40:42Z","creator":"aloesch","success":1,"content_type":"application/pdf","file_id":"5552","file_size":2464949,"access_level":"closed","file_name":"loesch_asap2018.pdf","date_updated":"2018-11-14T09:40:42Z","relation":"main_file"}],"department":[{"_id":"78"}],"type":"conference","publication_identifier":{"isbn":["9781538674796"]},"author":[{"full_name":"Lösch, Achim","last_name":"Lösch","first_name":"Achim","id":"43646"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"title":"A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes","year":"2018","publication_status":"published","date_updated":"2022-01-06T07:01:59Z","language":[{"iso":"eng"}],"doi":"10.1109/asap.2018.8445098"},{"abstract":[{"lang":"eng","text":"Approximate computing has become a very popular design\r\nstrategy that exploits error resilient computations to achieve higher\r\nperformance and energy efficiency. Automated synthesis of approximate\r\ncircuits is performed via functional approximation, in which various\r\nparts of the target circuit are extensively examined with a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy and computational budget (i.e., power). However, as the number\r\nof possible approximate transformations increases, traditional search\r\ntechniques suffer from a combinatorial explosion due to the large\r\nbranching factor. In this work, we present a comprehensive framework\r\nfor automated synthesis of approximate circuits from either structural\r\nor behavioral descriptions. We adapt the Monte Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the large design\r\nspace exploration, which enables a broader range of potential possible\r\napproximations through lightweight random simulations. The proposed\r\nframework is able to recognize the design Pareto set even with low\r\ncomputational budgets. Experimental results highlight the capabilities of\r\nthe proposed synthesis framework by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined quality constraints."}],"publication":"26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","citation":{"bibtex":"@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based Framework for Synthesis of Approximate Circuits}, DOI={<a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">10.1109/VLSI-SoC.2018.8645026</a>}, booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2018}, pages={219–224} }","chicago":"Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” In <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 219–24, 2018. <a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">https://doi.org/10.1109/VLSI-SoC.2018.8645026</a>.","ama":"Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for Synthesis of Approximate Circuits. In: <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>. ; 2018:219-224. doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">10.1109/VLSI-SoC.2018.8645026</a>","short":"M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.","ieee":"M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework for Synthesis of Approximate Circuits,” in <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2018, pp. 219–224.","mla":"Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate Circuits.” <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i>, 2018, pp. 219–24, doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">10.1109/VLSI-SoC.2018.8645026</a>.","apa":"Awais, M., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2018). An MCTS-based Framework for Synthesis of Approximate Circuits. In <i>26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)</i> (pp. 219–224). <a href=\"https://doi.org/10.1109/VLSI-SoC.2018.8645026\">https://doi.org/10.1109/VLSI-SoC.2018.8645026</a>"},"type":"conference","keyword":["Approximate computing","High-level synthesis","Accuracy","Monte-Carlo tree search","Circuit simulation"],"department":[{"_id":"78"}],"date_created":"2019-07-10T09:21:38Z","date_updated":"2022-01-06T06:50:46Z","year":"2018","title":"An MCTS-based Framework for Synthesis of Approximate Circuits","status":"public","author":[{"first_name":"Muhammad","last_name":"Awais","orcid":"https://orcid.org/0000-0003-4148-2969","full_name":"Awais, Muhammad","id":"64665"},{"id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","last_name":"Ghasemzadeh Mohammadi"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"user_id":"64665","doi":"10.1109/VLSI-SoC.2018.8645026","page":"219-224","language":[{"iso":"eng"}],"_id":"10598"},{"citation":{"mla":"Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” <i>IEEE Access</i>, 2018, pp. 14078–92, doi:<a href=\"https://doi.org/10.1109/access.2018.2799852\">10.1109/access.2018.2799852</a>.","bibtex":"@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}, DOI={<a href=\"https://doi.org/10.1109/access.2018.2799852\">10.1109/access.2018.2799852</a>}, journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018}, pages={14078–14092} }","ama":"Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. <i>IEEE Access</i>. 2018:14078-14092. doi:<a href=\"https://doi.org/10.1109/access.2018.2799852\">10.1109/access.2018.2799852</a>","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner, “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints,” <i>IEEE Access</i>, pp. 14078–14092, 2018.","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., &#38; Platzner, M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. <i>IEEE Access</i>, 14078–14092. <a href=\"https://doi.org/10.1109/access.2018.2799852\">https://doi.org/10.1109/access.2018.2799852</a>","short":"I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE Access (2018) 14078–14092.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet, and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints.” <i>IEEE Access</i>, 2018, 14078–92. <a href=\"https://doi.org/10.1109/access.2018.2799852\">https://doi.org/10.1109/access.2018.2799852</a>."},"publication":"IEEE Access","date_created":"2019-08-26T13:33:00Z","department":[{"_id":"78"}],"type":"journal_article","publication_identifier":{"issn":["2169-3536"]},"author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"first_name":"Riadh Ben","last_name":"Abdallah","full_name":"Abdallah, Riadh Ben"},{"first_name":"Mohamed","last_name":"Khalgui","full_name":"Khalgui, Mohamed"},{"first_name":"Zhiwu","last_name":"Li","full_name":"Li, Zhiwu"},{"full_name":"Alnowibet, Khalid","first_name":"Khalid","last_name":"Alnowibet"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"year":"2018","status":"public","title":"R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints","date_updated":"2022-01-06T06:51:27Z","publication_status":"published","language":[{"iso":"eng"}],"_id":"12965","page":"14078-14092","doi":"10.1109/access.2018.2799852","user_id":"398"},{"has_accepted_license":"1","date_updated":"2022-01-06T07:03:08Z","author":[{"id":"43646","last_name":"Lösch","first_name":"Achim","full_name":"Lösch, Achim"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"status":"public","title":"reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements","year":"2017","doi":"10.1109/ASAP.2017.7995272","ddc":["040"],"user_id":"477","language":[{"iso":"eng"}],"_id":"65","project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"abstract":[{"text":"Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.","lang":"eng"}],"citation":{"mla":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017, doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>.","bibtex":"@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }","ama":"Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. ; 2017. doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>","ieee":"A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, 2017.","apa":"Lösch, A., &#38; Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>","short":"A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.","chicago":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>."},"publication":"Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","file_date_updated":"2018-11-14T09:37:55Z","department":[{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:41:04Z","file":[{"date_created":"2018-11-14T09:37:55Z","creator":"aloesch","file_id":"5550","success":1,"content_type":"application/pdf","file_name":"loesch_asap2017.pdf","file_size":467545,"access_level":"closed","relation":"main_file","date_updated":"2018-11-14T09:37:55Z"}]},{"_id":"68","publisher":"ACM","page":"61:1--61:23","ddc":["000"],"user_id":"3118","status":"public","has_accepted_license":"1","citation":{"apa":"Isenberg, T., Platzner, M., Wehrheim, H., &#38; Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. <i>ACM Transactions on Design Automation of Electronic Systems</i>, (4), 61:1--61:23. <a href=\"https://doi.org/10.1145/3054743\">https://doi.org/10.1145/3054743</a>","ieee":"T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4, pp. 61:1--61:23, 2017.","short":"T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23.","chicago":"Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4 (2017): 61:1--61:23. <a href=\"https://doi.org/10.1145/3054743\">https://doi.org/10.1145/3054743</a>.","mla":"Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” <i>ACM Transactions on Design Automation of Electronic Systems</i>, no. 4, ACM, 2017, pp. 61:1--61:23, doi:<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>.","ama":"Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. <i>ACM Transactions on Design Automation of Electronic Systems</i>. 2017;(4):61:1--61:23. doi:<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>","bibtex":"@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={<a href=\"https://doi.org/10.1145/3054743\">10.1145/3054743</a>}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }"},"file_date_updated":"2018-11-02T16:08:17Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"12","name":"SFB 901 - Subprojekt B4"},{"name":"SFB 901 - Project Area B","_id":"3"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"language":[{"iso":"eng"}],"doi":"10.1145/3054743","author":[{"last_name":"Isenberg","first_name":"Tobias","full_name":"Isenberg, Tobias"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"id":"573","full_name":"Wehrheim, Heike","last_name":"Wehrheim","first_name":"Heike"},{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"}],"title":"Proof-Carrying Hardware via Inductive Invariants","year":"2017","date_updated":"2022-01-06T07:03:20Z","date_created":"2017-10-17T12:41:04Z","file":[{"file_id":"5324","content_type":"application/pdf","success":1,"file_name":"a61-isenberg.pdf","access_level":"closed","file_size":806356,"relation":"main_file","date_updated":"2018-11-02T16:08:17Z","date_created":"2018-11-02T16:08:17Z","creator":"ups"}],"department":[{"_id":"77"},{"_id":"78"}],"type":"journal_article","publication":"ACM Transactions on Design Automation of Electronic Systems","issue":"4","abstract":[{"lang":"eng","text":"Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits."}]},{"department":[{"_id":"78"}],"type":"journal_article","date_created":"2019-07-10T09:22:27Z","citation":{"mla":"H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant Papers.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017, doi:<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>.","ama":"H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference – Significant Papers. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. 2017. doi:<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>","bibtex":"@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={<a href=\"https://doi.org/10.1145/2996468\">10.1145/2996468</a>}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }","apa":"H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant Papers. <i>ACM Transactions on Reconfigurable Technology and Systems</i>. <a href=\"https://doi.org/10.1145/2996468\">https://doi.org/10.1145/2996468</a>","ieee":"P. H.W. Leong <i>et al.</i>, “The First 25 Years of the FPL Conference – Significant Papers,” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017.","short":"P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017).","chicago":"H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\\~{a}o M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL Conference – Significant Papers.” <i>ACM Transactions on Reconfigurable Technology and Systems</i>, 2017. <a href=\"https://doi.org/10.1145/2996468\">https://doi.org/10.1145/2996468</a>."},"publication":"ACM Transactions on Reconfigurable Technology and Systems","user_id":"398","doi":"10.1145/2996468","_id":"10600","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:47Z","author":[{"last_name":"H.W. Leong","first_name":"Philip","full_name":"H.W. Leong, Philip"},{"last_name":"Amano","first_name":"Hideharu","full_name":"Amano, Hideharu"},{"last_name":"Anderson","first_name":"Jason","full_name":"Anderson, Jason"},{"last_name":"Bertels","first_name":"Koen","full_name":"Bertels, Koen"},{"first_name":"Jo\\~{a}o","last_name":"M.P. Cardoso","full_name":"M.P. Cardoso, Jo\\~{a}o"},{"full_name":"Diessel, Oliver","last_name":"Diessel","first_name":"Oliver"},{"full_name":"Gogniat, Guy","first_name":"Guy","last_name":"Gogniat"},{"first_name":"Mike","last_name":"Hutton","full_name":"Hutton, Mike"},{"last_name":"Lee","first_name":"JunKyu","full_name":"Lee, JunKyu"},{"last_name":"Luk","first_name":"Wayne","full_name":"Luk, Wayne"},{"first_name":"Patrick","last_name":"Lysaght","full_name":"Lysaght, Patrick"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"},{"full_name":"K. Prasanna, Viktor","first_name":"Viktor","last_name":"K. Prasanna"},{"full_name":"Rissa, Tero","last_name":"Rissa","first_name":"Tero"},{"full_name":"Silvano, Cristina","first_name":"Cristina","last_name":"Silvano"},{"first_name":"Hayden","last_name":"So","full_name":"So, Hayden"},{"full_name":"Wang, Yu","first_name":"Yu","last_name":"Wang"}],"year":"2017","status":"public","title":"The First 25 Years of the FPL Conference – Significant Papers"},{"type":"journal_article","department":[{"_id":"78"}],"date_created":"2019-07-10T09:22:28Z","publication":"IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing","citation":{"ieee":"R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial),” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017.","apa":"F. DeMara, R., Platzner, M., &#38; Ottavi, M. (2017). Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>. <a href=\"https://doi.org/10.1109/TETC.2016.2641599\">https://doi.org/10.1109/TETC.2016.2641599</a>","short":"R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017).","chicago":"F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017. <a href=\"https://doi.org/10.1109/TETC.2016.2641599\">https://doi.org/10.1109/TETC.2016.2641599</a>.","mla":"F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics: From Devices to Architectures (Guest Editorial).” <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>, 2017, doi:<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>.","bibtex":"@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }","ama":"F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial). <i>IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing</i>. 2017. doi:<a href=\"https://doi.org/10.1109/TETC.2016.2641599\">10.1109/TETC.2016.2641599</a>"},"doi":"10.1109/TETC.2016.2641599","user_id":"398","language":[{"iso":"eng"}],"_id":"10601","date_updated":"2022-01-06T06:50:47Z","status":"public","title":"Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)","year":"2017","author":[{"full_name":"F. DeMara, Ronald","last_name":"F. DeMara","first_name":"Ronald"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"full_name":"Ottavi, Marco","last_name":"Ottavi","first_name":"Marco"}]},{"date_created":"2019-07-10T09:23:11Z","department":[{"_id":"78"}],"type":"journal_article","citation":{"ieee":"J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus,” <i>Microprocessors and Microsystems</i>, pp. 160–172, 2017.","apa":"Anwer, J., &#38; Platzner, M. (2017). Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. <i>Microprocessors and Microsystems</i>, 160–172. <a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">https://doi.org/10.1016/j.micpro.2017.06.002</a>","short":"J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” <i>Microprocessors and Microsystems</i>, 2017, 160–72. <a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">https://doi.org/10.1016/j.micpro.2017.06.002</a>.","mla":"Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant FPGA Structures Using Boolean Difference Calculus.” <i>Microprocessors and Microsystems</i>, Elsevier, 2017, pp. 160–72, doi:<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>.","bibtex":"@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }","ama":"Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. <i>Microprocessors and Microsystems</i>. 2017:160-172. doi:<a href=\"https://doi.org/10.1016/j.micpro.2017.06.002\">10.1016/j.micpro.2017.06.002</a>"},"publication":"Microprocessors and Microsystems","_id":"10611","language":[{"iso":"eng"}],"publisher":"Elsevier","page":"160-172","user_id":"3118","doi":"10.1016/j.micpro.2017.06.002","author":[{"last_name":"Anwer","first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"status":"public","year":"2017","title":"Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus","date_updated":"2022-01-06T06:50:47Z"},{"doi":"10.23919/DATE.2017.7927137","user_id":"3118","_id":"10630","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"first_name":"Georg","last_name":"Thombansen","full_name":"Thombansen, Georg"},{"id":"49051","last_name":"Witschen","first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias"},{"last_name":"Wiens","first_name":"Alex","full_name":"Wiens, Alex"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller","year":"2017","status":"public","department":[{"_id":"78"}],"type":"conference","date_created":"2019-07-10T11:02:56Z","citation":{"chicago":"Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens, and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” In <i>Design, Automation and Test in Europe (DATE)</i>, 2017. <a href=\"https://doi.org/10.23919/DATE.2017.7927137\">https://doi.org/10.23919/DATE.2017.7927137</a>.","short":"A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design, Automation and Test in Europe (DATE), 2017.","apa":"Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., &#38; Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In <i>Design, Automation and Test in Europe (DATE)</i>. <a href=\"https://doi.org/10.23919/DATE.2017.7927137\">https://doi.org/10.23919/DATE.2017.7927137</a>","ieee":"A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,” in <i>Design, Automation and Test in Europe (DATE)</i>, 2017.","ama":"Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In: <i>Design, Automation and Test in Europe (DATE)</i>. ; 2017. doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>","bibtex":"@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}, DOI={<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}, year={2017} }","mla":"Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric Prosthesis Controller.” <i>Design, Automation and Test in Europe (DATE)</i>, 2017, doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927137\">10.23919/DATE.2017.7927137</a>."},"publication":"Design, Automation and Test in Europe (DATE)"},{"publication":"Proc. Design, Automation and Test in Europe Conf. (DATE)","citation":{"ieee":"N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor,” in <i>Proc. Design, Automation and Test in Europe Conf. (DATE)</i>, 2017.","apa":"Ho, N., Ashraf, I. I., Kaufmann, P., &#38; Platzner, M. (2017). Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In <i>Proc. Design, Automation and Test in Europe Conf. (DATE)</i>. <a href=\"https://doi.org/10.23919/DATE.2017.7927096\">https://doi.org/10.23919/DATE.2017.7927096</a>","chicago":"Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” In <i>Proc. Design, Automation and Test in Europe Conf. (DATE)</i>, 2017. <a href=\"https://doi.org/10.23919/DATE.2017.7927096\">https://doi.org/10.23919/DATE.2017.7927096</a>.","short":"N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.","mla":"Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for the LEON3 Multi-Core Processor.” <i>Proc. Design, Automation and Test in Europe Conf. (DATE)</i>, 2017, doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927096\">10.23919/DATE.2017.7927096</a>.","bibtex":"@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}, DOI={<a href=\"https://doi.org/10.23919/DATE.2017.7927096\">10.23919/DATE.2017.7927096</a>}, booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017} }","ama":"Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In: <i>Proc. Design, Automation and Test in Europe Conf. (DATE)</i>. ; 2017. doi:<a href=\"https://doi.org/10.23919/DATE.2017.7927096\">10.23919/DATE.2017.7927096</a>"},"date_created":"2019-07-10T11:17:58Z","type":"conference","department":[{"_id":"78"}],"title":"Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor","status":"public","year":"2017","author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"last_name":"Ashraf","first_name":"Ishraq Ibne","full_name":"Ashraf, Ishraq Ibne"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"_id":"10672","user_id":"3118","doi":"10.23919/DATE.2017.7927096"},{"publication":"2017 International Conference on Field Programmable Technology (ICFPT)","citation":{"bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 215–18, 2017. <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>. ; 2017:215-218. doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–218.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i> (pp. 215–218). <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>","mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–18, doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>."},"keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T11:22:59Z","date_updated":"2022-01-06T06:50:49Z","title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","status":"public","year":"2017","author":[{"last_name":"Ho","first_name":"Nam","full_name":"Ho, Nam"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"doi":"10.1109/FPT.2017.8280144","user_id":"398","page":"215-218","_id":"10676","language":[{"iso":"eng"}]},{"_id":"10761","publisher":"IEEE","language":[{"iso":"eng"}],"user_id":"3118","doi":"10.1109/AHS.2017.8046380","title":"Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches","year":"2017","status":"public","author":[{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"full_name":"Ho, Nam","last_name":"Ho","first_name":"Nam"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:07:01Z","type":"conference","department":[{"_id":"78"}],"publication":"Adaptive Hardware and Systems (AHS)","citation":{"ama":"Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In: <i>Adaptive Hardware and Systems (AHS)</i>. IEEE; 2017. doi:<a href=\"https://doi.org/10.1109/AHS.2017.8046380\">10.1109/AHS.2017.8046380</a>","bibtex":"@inproceedings{Kaufmann_Ho_Platzner_2017, title={Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}, DOI={<a href=\"https://doi.org/10.1109/AHS.2017.8046380\">10.1109/AHS.2017.8046380</a>}, booktitle={Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Kaufmann, Paul and Ho, Nam and Platzner, Marco}, year={2017} }","mla":"Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” <i>Adaptive Hardware and Systems (AHS)</i>, IEEE, 2017, doi:<a href=\"https://doi.org/10.1109/AHS.2017.8046380\">10.1109/AHS.2017.8046380</a>.","chicago":"Kaufmann, Paul, Nam Ho, and Marco Platzner. “Evaluation Methodology for Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization of Caches.” In <i>Adaptive Hardware and Systems (AHS)</i>. IEEE, 2017. <a href=\"https://doi.org/10.1109/AHS.2017.8046380\">https://doi.org/10.1109/AHS.2017.8046380</a>.","short":"P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS), IEEE, 2017.","apa":"Kaufmann, P., Ho, N., &#38; Platzner, M. (2017). Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In <i>Adaptive Hardware and Systems (AHS)</i>. IEEE. <a href=\"https://doi.org/10.1109/AHS.2017.8046380\">https://doi.org/10.1109/AHS.2017.8046380</a>","ieee":"P. Kaufmann, N. Ho, and M. Platzner, “Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches,” in <i>Adaptive Hardware and Systems (AHS)</i>, 2017."}},{"page":"1-8","language":[{"iso":"eng"}],"_id":"10780","user_id":"3118","doi":"10.1109/ReCoSoC.2017.8016147","status":"public","title":"Computational self-awareness as design approach for visual sensor nodes","year":"2017","author":[{"full_name":"Guettatfi, Zakarya","first_name":"Zakarya","last_name":"Guettatfi"},{"first_name":"Philipp","last_name":"Hübner","full_name":"Hübner, Philipp"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"}],"date_updated":"2022-01-06T06:50:50Z","date_created":"2019-07-10T12:13:15Z","keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"type":"conference","department":[{"_id":"78"}],"publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","citation":{"bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 1–8, 2017. <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8.","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>.","apa":"Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>"}},{"doi":"10.1007/978-3-319-62569-0_8","user_id":"398","_id":"14893","publisher":"Springer ","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:52:10Z","publication_status":"published","publication_identifier":{"issn":["1865-0929","1865-0937"],"isbn":["9783319625683","9783319625690"]},"author":[{"last_name":"Ghribi","first_name":"Ines","full_name":"Ghribi, Ines"},{"full_name":"Abdallah, Riadh Ben","first_name":"Riadh Ben","last_name":"Abdallah"},{"full_name":"Khalgui, Mohamed","last_name":"Khalgui","first_name":"Mohamed"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"status":"public","title":"I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems","year":"2017","department":[{"_id":"78"}],"type":"conference","place":"Cham","date_created":"2019-11-12T08:33:13Z","citation":{"mla":"Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” <i>Communications in Computer and Information Science</i>, Springer , 2017, doi:<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>.","bibtex":"@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>}, booktitle={Communications in Computer and Information Science}, publisher={Springer }, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}, year={2017} }","ama":"Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In: <i>Communications in Computer and Information Science</i>. Cham: Springer ; 2017. doi:<a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">10.1007/978-3-319-62569-0_8</a>","ieee":"I. Ghribi, R. B. Abdallah, M. Khalgui, and M. Platzner, “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems,” in <i>Communications in Computer and Information Science</i>, 2017.","apa":"Ghribi, I., Abdallah, R. B., Khalgui, M., &#38; Platzner, M. (2017). I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In <i>Communications in Computer and Information Science</i>. Cham: Springer . <a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">https://doi.org/10.1007/978-3-319-62569-0_8</a>","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” In <i>Communications in Computer and Information Science</i>. Cham: Springer , 2017. <a href=\"https://doi.org/10.1007/978-3-319-62569-0_8\">https://doi.org/10.1007/978-3-319-62569-0_8</a>.","short":"I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in Computer and Information Science, Springer , Cham, 2017."},"publication":"Communications in Computer and Information Science"},{"abstract":[{"lang":"eng","text":"Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved."}],"publication":"Computers & Electrical Engineering","type":"journal_article","department":[{"_id":"78"}],"file":[{"date_updated":"2018-03-21T10:36:08Z","relation":"main_file","access_level":"closed","file_size":931048,"file_name":"222-1-s2.0-S0045790616300684-main.pdf","content_type":"application/pdf","success":1,"file_id":"1511","creator":"florida","date_created":"2018-03-21T10:36:08Z"}],"date_created":"2017-10-17T12:41:35Z","date_updated":"2022-01-06T06:55:29Z","year":"2016","title":"An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip","author":[{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"},{"full_name":"Bockhorn, Arne","last_name":"Bockhorn","first_name":"Arne"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"doi":"10.1016/j.compeleceng.2016.04.005","language":[{"iso":"eng"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"3","name":"SFB 901 - Project Area B"}],"file_date_updated":"2018-03-21T10:36:08Z","citation":{"mla":"Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, Elsevier, 2016, pp. 112--122, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>.","ama":"Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>. 2016:112--122. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>","bibtex":"@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">10.1016/j.compeleceng.2016.04.005</a>}, journal={Computers &#38; Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }","apa":"Wiersema, T., Bockhorn, A., &#38; Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. <i>Computers &#38; Electrical Engineering</i>, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>","ieee":"T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” <i>Computers &#38; Electrical Engineering</i>, pp. 112--122, 2016.","short":"T. Wiersema, A. Bockhorn, M. Platzner, Computers &#38; Electrical Engineering (2016) 112--122.","chicago":"Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” <i>Computers &#38; Electrical Engineering</i>, 2016, 112--122. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.005\">https://doi.org/10.1016/j.compeleceng.2016.04.005</a>."},"has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"477","page":"112--122","_id":"222","publisher":"Elsevier"},{"publication_status":"published","date_updated":"2022-01-06T07:02:42Z","publication_identifier":{"isbn":["9781467394062"]},"author":[{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Witschen, Linus","first_name":"Linus","last_name":"Witschen"},{"last_name":"Thombansen","first_name":"Georg","full_name":"Thombansen, Georg"},{"id":"14053","last_name":"Kraus","first_name":"Florian","full_name":"Kraus, Florian"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"title":"FPGA-based acceleration of high density myoelectric signal processing","year":"2016","status":"public","user_id":"14053","doi":"10.1109/reconfig.2015.7393312","_id":"5812","publisher":"IEEE","language":[{"iso":"eng"}],"extern":"1","citation":{"short":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.","ama":"Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based acceleration of high density myoelectric signal processing. In: <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2016. doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>","chicago":"Boschmann, Alexander, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” In <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE, 2016. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>.","bibtex":"@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016, title={FPGA-based acceleration of high density myoelectric signal processing}, DOI={<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>}, booktitle={2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, year={2016} }","mla":"Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric Signal Processing.” <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2016, doi:<a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">10.1109/reconfig.2015.7393312</a>.","apa":"Boschmann, A., Agne, A., Witschen, L., Thombansen, G., Kraus, F., &#38; Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE. <a href=\"https://doi.org/10.1109/reconfig.2015.7393312\">https://doi.org/10.1109/reconfig.2015.7393312</a>","ieee":"A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in <i>2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2016."},"publication":"2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"78"}],"type":"conference","date_created":"2018-11-23T15:00:28Z"},{"date_created":"2019-07-10T09:33:00Z","type":"conference","department":[{"_id":"78"}],"publication":"Euromicro Conference on Digital System Design (DSD)","citation":{"mla":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” <i>Euromicro Conference on Digital System Design (DSD)</i>, 2016, doi:<a href=\"https://doi.org/10.1109/DSD.2016.35\">10.1109/DSD.2016.35</a>.","ama":"Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In: <i>Euromicro Conference on Digital System Design (DSD)</i>. ; 2016. doi:<a href=\"https://doi.org/10.1109/DSD.2016.35\">10.1109/DSD.2016.35</a>","bibtex":"@inproceedings{Anwer_Platzner_2016, title={Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/DSD.2016.35\">10.1109/DSD.2016.35</a>}, booktitle={Euromicro Conference on Digital System Design (DSD)}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2016} }","apa":"Anwer, J., &#38; Platzner, M. (2016). Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In <i>Euromicro Conference on Digital System Design (DSD)</i>. <a href=\"https://doi.org/10.1109/DSD.2016.35\">https://doi.org/10.1109/DSD.2016.35</a>","ieee":"J. Anwer and M. Platzner, “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs,” in <i>Euromicro Conference on Digital System Design (DSD)</i>, 2016.","short":"J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design (DSD), 2016.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs.” In <i>Euromicro Conference on Digital System Design (DSD)</i>, 2016. <a href=\"https://doi.org/10.1109/DSD.2016.35\">https://doi.org/10.1109/DSD.2016.35</a>."},"language":[{"iso":"eng"}],"_id":"10622","doi":"10.1109/DSD.2016.35","user_id":"3118","title":"Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs","year":"2016","status":"public","author":[{"full_name":"Anwer, Jahanzeb","last_name":"Anwer","first_name":"Jahanzeb"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:48Z"},{"date_created":"2019-07-10T11:14:43Z","type":"journal_article","department":[{"_id":"78"}],"publication":"Journal Theoretical Computer Science","citation":{"apa":"Graf, T., &#38; Platzner, M. (2016). Adaptive playouts for online learning of policies during Monte Carlo Tree Search. <i>Journal Theoretical Computer Science</i>, <i>644</i>, 53–62. <a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">https://doi.org/10.1016/j.tcs.2016.06.029</a>","mla":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” <i>Journal Theoretical Computer Science</i>, vol. 644, Elsevier, 2016, pp. 53–62, doi:<a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">10.1016/j.tcs.2016.06.029</a>.","ieee":"T. Graf and M. Platzner, “Adaptive playouts for online learning of policies during Monte Carlo Tree Search,” <i>Journal Theoretical Computer Science</i>, vol. 644, pp. 53–62, 2016.","chicago":"Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of Policies during Monte Carlo Tree Search.” <i>Journal Theoretical Computer Science</i> 644 (2016): 53–62. <a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">https://doi.org/10.1016/j.tcs.2016.06.029</a>.","short":"T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62.","ama":"Graf T, Platzner M. Adaptive playouts for online learning of policies during Monte Carlo Tree Search. <i>Journal Theoretical Computer Science</i>. 2016;644:53-62. doi:<a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">10.1016/j.tcs.2016.06.029</a>","bibtex":"@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={<a href=\"https://doi.org/10.1016/j.tcs.2016.06.029\">10.1016/j.tcs.2016.06.029</a>}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }"},"page":"53-62","publisher":"Elsevier","_id":"10661","language":[{"iso":"eng"}],"doi":"10.1016/j.tcs.2016.06.029","user_id":"3118","volume":644,"title":"Adaptive playouts for online learning of policies during Monte Carlo Tree Search","status":"public","year":"2016","author":[{"full_name":"Graf, Tobias","last_name":"Graf","first_name":"Tobias"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"date_updated":"2022-01-06T06:50:49Z","intvolume":"       644"},{"date_created":"2019-07-10T11:47:25Z","type":"conference","department":[{"_id":"78"}],"publication":"Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on","citation":{"mla":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On</i>, 2016, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">10.1109/ReConFig.2016.7857193</a>.","bibtex":"@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">10.1109/ReConFig.2016.7857193</a>}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8}, collection={ReConFig} }","ama":"Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In: <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On</i>. ReConFig. ; 2016:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">10.1109/ReConFig.2016.7857193</a>","ieee":"S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level,” in <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on</i>, 2016, pp. 1–8.","apa":"Meisner, S., &#38; Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">https://doi.org/10.1109/ReConFig.2016.7857193</a>","chicago":"Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level.” In <i>Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On</i>, 1–8. ReConFig, 2016. <a href=\"https://doi.org/10.1109/ReConFig.2016.7857193\">https://doi.org/10.1109/ReConFig.2016.7857193</a>.","short":"S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8."},"page":"1-8","series_title":"ReConFig","_id":"10712","language":[{"iso":"eng"}],"user_id":"3118","doi":"10.1109/ReConFig.2016.7857193","status":"public","title":"Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level","year":"2016","author":[{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"date_updated":"2022-01-06T06:50:50Z"},{"author":[{"full_name":"Ghribi, Ines","first_name":"Ines","last_name":"Ghribi"},{"full_name":"Ben Abdallah, Riadh","first_name":"Riadh","last_name":"Ben Abdallah"},{"full_name":"Khalgui, Mohamed","first_name":"Mohamed","last_name":"Khalgui"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"year":"2016","title":"RCo-Design: New Visual Environment for Reconfigurable Embedded Systems","status":"public","date_updated":"2022-01-06T06:50:50Z","language":[{"iso":"eng"}],"_id":"10766","user_id":"3118","citation":{"bibtex":"@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016} }","ama":"Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In: <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>. ; 2016.","mla":"Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>, 2016.","chicago":"Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner. “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>, 2016.","short":"I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.","ieee":"I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New Visual Environment for Reconfigurable Embedded Systems,” in <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>, 2016.","apa":"Ghribi, I., Ben Abdallah, R., Khalgui, M., &#38; Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In <i>Proceedings of the 30th European Simulation and Modelling Conference (ESM)</i>."},"publication":"Proceedings of the 30th European Simulation and Modelling Conference (ESM)","date_created":"2019-07-10T12:07:54Z","department":[{"_id":"78"}],"type":"conference"}]