---
_id: '5547'
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on
Heterogeneous Compute Nodes. In: 2018 IEEE 29th International Conference on
Application-Specific Systems, Architectures and Processors (ASAP). IEEE; 2018.
doi:10.1109/asap.2018.8445098'
apa: 'Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP). Milan,
Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098'
bibtex: '@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model
for Task Execution on Heterogeneous Compute Nodes}, DOI={10.1109/asap.2018.8445098},
booktitle={2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and
Platzner, Marco}, year={2018} }'
chicago: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” In 2018 IEEE 29th International
Conference on Application-Specific Systems, Architectures and Processors (ASAP).
IEEE, 2018. https://doi.org/10.1109/asap.2018.8445098.
ieee: A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution
on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference
on Application-specific Systems, Architectures and Processors (ASAP), Milan,
Italy, 2018.
mla: Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task
Execution on Heterogeneous Compute Nodes.” 2018 IEEE 29th International Conference
on Application-Specific Systems, Architectures and Processors (ASAP), IEEE,
2018, doi:10.1109/asap.2018.8445098.
short: 'A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific
Systems, Architectures and Processors (ASAP), IEEE, 2018.'
conference:
end_date: 2018-07-12
location: Milan, Italy
name: The 29th Annual IEEE International Conference on Application-specific Systems,
Architectures and Processors
start_date: 2018-07-10
date_created: 2018-11-14T09:26:53Z
date_updated: 2022-01-06T07:01:59Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/asap.2018.8445098
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:40:42Z
date_updated: 2018-11-14T09:40:42Z
file_id: '5552'
file_name: loesch_asap2018.pdf
file_size: 2464949
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:40:42Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publication: 2018 IEEE 29th International Conference on Application-specific Systems,
Architectures and Processors (ASAP)
publication_identifier:
isbn:
- '9781538674796'
publication_status: published
publisher: IEEE
status: public
title: A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute
Nodes
type: conference
user_id: '43646'
year: '2018'
...
---
_id: '10598'
abstract:
- lang: eng
text: "Approximate computing has become a very popular design\r\nstrategy that exploits
error resilient computations to achieve higher\r\nperformance and energy efficiency.
Automated synthesis of approximate\r\ncircuits is performed via functional approximation,
in which various\r\nparts of the target circuit are extensively examined with
a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy
and computational budget (i.e., power). However, as the number\r\nof possible
approximate transformations increases, traditional search\r\ntechniques suffer
from a combinatorial explosion due to the large\r\nbranching factor. In this work,
we present a comprehensive framework\r\nfor automated synthesis of approximate
circuits from either structural\r\nor behavioral descriptions. We adapt the Monte
Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the
large design\r\nspace exploration, which enables a broader range of potential
possible\r\napproximations through lightweight random simulations. The proposed\r\nframework
is able to recognize the design Pareto set even with low\r\ncomputational budgets.
Experimental results highlight the capabilities of\r\nthe proposed synthesis framework
by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined
quality constraints."
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for
Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026'
apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based
Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based
Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026},
booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner,
Marco}, year={2018}, pages={219–224} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An
MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC), 219–24,
2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework
for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate
Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.'
date_created: 2019-07-10T09:21:38Z
date_updated: 2022-01-06T06:50:46Z
department:
- _id: '78'
doi: 10.1109/VLSI-SoC.2018.8645026
keyword:
- Approximate computing
- High-level synthesis
- Accuracy
- Monte-Carlo tree search
- Circuit simulation
language:
- iso: eng
page: 219-224
publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)
status: public
title: An MCTS-based Framework for Synthesis of Approximate Circuits
type: conference
user_id: '64665'
year: '2018'
...
---
_id: '12965'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh Ben
full_name: Abdallah, Riadh Ben
last_name: Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Zhiwu
full_name: Li, Zhiwu
last_name: Li
- first_name: Khalid
full_name: Alnowibet, Khalid
last_name: Alnowibet
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Abdallah RB, Khalgui M, Li Z, Alnowibet K, Platzner M. R-Codesign:
Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy
Constraints. IEEE Access. 2018:14078-14092. doi:10.1109/access.2018.2799852'
apa: 'Ghribi, I., Abdallah, R. B., Khalgui, M., Li, Z., Alnowibet, K., & Platzner,
M. (2018). R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded
Systems Under Energy Constraints. IEEE Access, 14078–14092. https://doi.org/10.1109/access.2018.2799852'
bibtex: '@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign:
Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy
Constraints}, DOI={10.1109/access.2018.2799852},
journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui,
Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018},
pages={14078–14092} }'
chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, Zhiwu Li, Khalid Alnowibet,
and Marco Platzner. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable
Embedded Systems Under Energy Constraints.” IEEE Access, 2018, 14078–92.
https://doi.org/10.1109/access.2018.2799852.'
ieee: 'I. Ghribi, R. B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, and M. Platzner,
“R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems
Under Energy Constraints,” IEEE Access, pp. 14078–14092, 2018.'
mla: 'Ghribi, Ines, et al. “R-Codesign: Codesign Methodology for Real-Time Reconfigurable
Embedded Systems Under Energy Constraints.” IEEE Access, 2018, pp. 14078–92,
doi:10.1109/access.2018.2799852.'
short: I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE
Access (2018) 14078–14092.
date_created: 2019-08-26T13:33:00Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '78'
doi: 10.1109/access.2018.2799852
language:
- iso: eng
page: 14078-14092
publication: IEEE Access
publication_identifier:
issn:
- 2169-3536
publication_status: published
status: public
title: 'R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems
Under Energy Constraints'
type: journal_article
user_id: '398'
year: '2018'
...
---
_id: '65'
abstract:
- lang: eng
text: Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators
have strongly gained interested in the last years. Applications differ in their
execution characteristics and can therefore benefit from such heterogeneous resources
in terms of performance or energy consumption. While performance optimization
has been the only goal for a long time, nowadays research is more and more focusing
on techniques to minimize energy consumption due to rising electricity costs.This
paper presents reMinMin, a novel static list scheduling approach for optimizing
the total energy consumption for a set of tasks executed on a heterogeneous compute
node. reMinMin bases on a new energy model that differentiates between static
and dynamic energy components and covers effects of accelerator tasks on the host
CPU. The required energy values are retrieved by measurements on the real computing
system. In order to evaluate reMinMin, we compare it with two reference implementations
on three task sets with different degrees of heterogeneity. In our experiments,
MinMin is consistently better than a scheduler optimizing for dynamic energy only,
which requires up to 19.43% more energy, and very close to optimal schedules.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements. In: Proceedings of the 28th Annual IEEE
International Conference on Application-Specific Systems, Architectures and Processors
(ASAP). ; 2017. doi:10.1109/ASAP.2017.7995272'
apa: 'Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements. In Proceedings of the
28th Annual IEEE International Conference on Application-specific Systems, Architectures
and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272'
bibtex: '@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements}, DOI={10.1109/ASAP.2017.7995272},
booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner,
Marco}, year={2017} }'
chicago: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” In Proceedings of the
28th Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017. https://doi.org/10.1109/ASAP.2017.7995272.'
ieee: 'A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling
Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE
International Conference on Application-specific Systems, Architectures and Processors
(ASAP), 2017.'
mla: 'Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric
List Scheduling Approach Based on Real Measurements.” Proceedings of the 28th
Annual IEEE International Conference on Application-Specific Systems, Architectures
and Processors (ASAP), 2017, doi:10.1109/ASAP.2017.7995272.'
short: 'A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International
Conference on Application-Specific Systems, Architectures and Processors (ASAP),
2017.'
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:08Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1109/ASAP.2017.7995272
file:
- access_level: closed
content_type: application/pdf
creator: aloesch
date_created: 2018-11-14T09:37:55Z
date_updated: 2018-11-14T09:37:55Z
file_id: '5550'
file_name: loesch_asap2017.pdf
file_size: 467545
relation: main_file
success: 1
file_date_updated: 2018-11-14T09:37:55Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 28th Annual IEEE International Conference on Application-specific
Systems, Architectures and Processors (ASAP)
status: public
title: 'reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on
Real Measurements'
type: conference
user_id: '477'
year: '2017'
...
---
_id: '68'
abstract:
- lang: eng
text: Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically
reconfigurable hardware systems. The producer of a hardware module spends huge
effort when creating a proof for a safety policy. The proof is then transferred
as a certificate together with the configuration bitstream to the consumer of
the hardware module, who can quickly verify the given proof. Previous work utilized
SAT solvers and resolution traces to set up a PCH technology and corresponding
tool flows. In this article, we present a novel technology for PCH based on inductive
invariants. For sequential circuits, our approach is fundamentally stronger than
the previous SAT-based one since we avoid the limitations of bounded unrolling.
We contrast our technology to existing ones and show that it fits into previously
proposed tool flows. We conduct experiments with four categories of benchmark
circuits and report consumer and producer runtime and peak memory consumption,
as well as the size of the certificates and the distribution of the workload between
producer and consumer. Experiments clearly show that our new induction-based technology
is superior for sequential circuits, whereas the previous SAT-based technology
is the better choice for combinational circuits.
author:
- first_name: Tobias
full_name: Isenberg, Tobias
last_name: Isenberg
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via
Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems.
2017;(4):61:1--61:23. doi:10.1145/3054743
apa: Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying
Hardware via Inductive Invariants. ACM Transactions on Design Automation of
Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743
bibtex: '@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying
Hardware via Inductive Invariants}, DOI={10.1145/3054743},
number={4}, journal={ACM Transactions on Design Automation of Electronic Systems},
publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike
and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }'
chicago: 'Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema.
“Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design
Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.'
ieee: T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware
via Inductive Invariants,” ACM Transactions on Design Automation of Electronic
Systems, no. 4, pp. 61:1--61:23, 2017.
mla: Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.”
ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM,
2017, pp. 61:1--61:23, doi:10.1145/3054743.
short: T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design
Automation of Electronic Systems (2017) 61:1--61:23.
date_created: 2017-10-17T12:41:04Z
date_updated: 2022-01-06T07:03:20Z
ddc:
- '000'
department:
- _id: '77'
- _id: '78'
doi: 10.1145/3054743
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T16:08:17Z
date_updated: 2018-11-02T16:08:17Z
file_id: '5324'
file_name: a61-isenberg.pdf
file_size: 806356
relation: main_file
success: 1
file_date_updated: 2018-11-02T16:08:17Z
has_accepted_license: '1'
issue: '4'
language:
- iso: eng
page: 61:1--61:23
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: ACM Transactions on Design Automation of Electronic Systems
publisher: ACM
status: public
title: Proof-Carrying Hardware via Inductive Invariants
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10600'
author:
- first_name: Philip
full_name: H.W. Leong, Philip
last_name: H.W. Leong
- first_name: Hideharu
full_name: Amano, Hideharu
last_name: Amano
- first_name: Jason
full_name: Anderson, Jason
last_name: Anderson
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
- first_name: Jo\~{a}o
full_name: M.P. Cardoso, Jo\~{a}o
last_name: M.P. Cardoso
- first_name: Oliver
full_name: Diessel, Oliver
last_name: Diessel
- first_name: Guy
full_name: Gogniat, Guy
last_name: Gogniat
- first_name: Mike
full_name: Hutton, Mike
last_name: Hutton
- first_name: JunKyu
full_name: Lee, JunKyu
last_name: Lee
- first_name: Wayne
full_name: Luk, Wayne
last_name: Luk
- first_name: Patrick
full_name: Lysaght, Patrick
last_name: Lysaght
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Viktor
full_name: K. Prasanna, Viktor
last_name: K. Prasanna
- first_name: Tero
full_name: Rissa, Tero
last_name: Rissa
- first_name: Cristina
full_name: Silvano, Cristina
last_name: Silvano
- first_name: Hayden
full_name: So, Hayden
last_name: So
- first_name: Yu
full_name: Wang, Yu
last_name: Wang
citation:
ama: H.W. Leong P, Amano H, Anderson J, et al. The First 25 Years of the FPL Conference
– Significant Papers. ACM Transactions on Reconfigurable Technology and Systems.
2017. doi:10.1145/2996468
apa: H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel,
O., … Wang, Y. (2017). The First 25 Years of the FPL Conference – Significant
Papers. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2996468
bibtex: '@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et
al._2017, title={The First 25 Years of the FPL Conference – Significant Papers},
DOI={10.1145/2996468}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip
and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o
and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk,
Wayne and et al.}, year={2017} }'
chicago: H.W. Leong, Philip, Hideharu Amano, Jason Anderson, Koen Bertels, Jo\~{a}o
M.P. Cardoso, Oliver Diessel, Guy Gogniat, et al. “The First 25 Years of the FPL
Conference – Significant Papers.” ACM Transactions on Reconfigurable Technology
and Systems, 2017. https://doi.org/10.1145/2996468.
ieee: P. H.W. Leong et al., “The First 25 Years of the FPL Conference – Significant
Papers,” ACM Transactions on Reconfigurable Technology and Systems, 2017.
mla: H.W. Leong, Philip, et al. “The First 25 Years of the FPL Conference – Significant
Papers.” ACM Transactions on Reconfigurable Technology and Systems, 2017,
doi:10.1145/2996468.
short: P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel,
G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna,
T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology
and Systems (2017).
date_created: 2019-07-10T09:22:27Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1145/2996468
language:
- iso: eng
publication: ACM Transactions on Reconfigurable Technology and Systems
status: public
title: The First 25 Years of the FPL Conference – Significant Papers
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10601'
author:
- first_name: Ronald
full_name: F. DeMara, Ronald
last_name: F. DeMara
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Marco
full_name: Ottavi, Marco
last_name: Ottavi
citation:
ama: 'F. DeMara R, Platzner M, Ottavi M. Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. 2017.
doi:10.1109/TETC.2016.2641599'
apa: 'F. DeMara, R., Platzner, M., & Ottavi, M. (2017). Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial). IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing. https://doi.org/10.1109/TETC.2016.2641599'
bibtex: '@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable
Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599},
journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco},
year={2017} }'
chicago: 'F. DeMara, Ronald, Marco Platzner, and Marco Ottavi. “Innovation in Reconfigurable
Computing Fabrics: From Devices to Architectures (Guest Editorial).” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.
https://doi.org/10.1109/TETC.2016.2641599.'
ieee: 'R. F. DeMara, M. Platzner, and M. Ottavi, “Innovation in Reconfigurable Computing
Fabrics: from Devices to Architectures (guest editorial),” IEEE Transactions
on Computers and IEEE Transactions on Emerging Topics in Computing, 2017.'
mla: 'F. DeMara, Ronald, et al. “Innovation in Reconfigurable Computing Fabrics:
From Devices to Architectures (Guest Editorial).” IEEE Transactions on Computers
and IEEE Transactions on Emerging Topics in Computing, 2017, doi:10.1109/TETC.2016.2641599.'
short: R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and
IEEE Transactions on Emerging Topics in Computing (2017).
date_created: 2019-07-10T09:22:28Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1109/TETC.2016.2641599
language:
- iso: eng
publication: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics
in Computing
status: public
title: 'Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures
(guest editorial)'
type: journal_article
user_id: '398'
year: '2017'
...
---
_id: '10611'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Anwer J, Platzner M. Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus. Microprocessors and Microsystems. 2017:160-172.
doi:10.1016/j.micpro.2017.06.002
apa: Anwer, J., & Platzner, M. (2017). Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus. Microprocessors and Microsystems,
160–172. https://doi.org/10.1016/j.micpro.2017.06.002
bibtex: '@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant
FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002},
journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer,
Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
2017, 160–72. https://doi.org/10.1016/j.micpro.2017.06.002.
ieee: J. Anwer and M. Platzner, “Evaluating fault-tolerance of redundant FPGA structures
using Boolean difference calculus,” Microprocessors and Microsystems, pp.
160–172, 2017.
mla: Anwer, Jahanzeb, and Marco Platzner. “Evaluating Fault-Tolerance of Redundant
FPGA Structures Using Boolean Difference Calculus.” Microprocessors and Microsystems,
Elsevier, 2017, pp. 160–72, doi:10.1016/j.micpro.2017.06.002.
short: J. Anwer, M. Platzner, Microprocessors and Microsystems (2017) 160–172.
date_created: 2019-07-10T09:23:11Z
date_updated: 2022-01-06T06:50:47Z
department:
- _id: '78'
doi: 10.1016/j.micpro.2017.06.002
language:
- iso: eng
page: 160-172
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: Evaluating fault-tolerance of redundant FPGA structures using Boolean difference
calculus
type: journal_article
user_id: '3118'
year: '2017'
...
---
_id: '10630'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Alex
full_name: Wiens, Alex
last_name: Wiens
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Thombansen G, Witschen LM, Wiens A, Platzner M. A Zynq-based
dynamically reconfigurable high density myoelectric prosthesis controller. In:
Design, Automation and Test in Europe (DATE). ; 2017. doi:10.23919/DATE.2017.7927137'
apa: Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner,
M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137
bibtex: '@inproceedings{Boschmann_Thombansen_Witschen_Wiens_Platzner_2017, title={A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller},
DOI={10.23919/DATE.2017.7927137},
booktitle={Design, Automation and Test in Europe (DATE)}, author={Boschmann, Alexander
and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner,
Marco}, year={2017} }'
chicago: Boschmann, Alexander, Georg Thombansen, Linus Matthias Witschen, Alex Wiens,
and Marco Platzner. “A Zynq-Based Dynamically Reconfigurable High Density Myoelectric
Prosthesis Controller.” In Design, Automation and Test in Europe (DATE),
2017. https://doi.org/10.23919/DATE.2017.7927137.
ieee: A. Boschmann, G. Thombansen, L. M. Witschen, A. Wiens, and M. Platzner, “A
Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller,”
in Design, Automation and Test in Europe (DATE), 2017.
mla: Boschmann, Alexander, et al. “A Zynq-Based Dynamically Reconfigurable High
Density Myoelectric Prosthesis Controller.” Design, Automation and Test in
Europe (DATE), 2017, doi:10.23919/DATE.2017.7927137.
short: 'A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design,
Automation and Test in Europe (DATE), 2017.'
date_created: 2019-07-10T11:02:56Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927137
language:
- iso: eng
publication: Design, Automation and Test in Europe (DATE)
status: public
title: A Zynq-based dynamically reconfigurable high density myoelectric prosthesis
controller
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10672'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Ishraq Ibne
full_name: Ashraf, Ishraq Ibne
last_name: Ashraf
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ashraf II, Kaufmann P, Platzner M. Accurate Private/Shared Classification
of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor.
In: Proc. Design, Automation and Test in Europe Conf. (DATE). ; 2017. doi:10.23919/DATE.2017.7927096'
apa: 'Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE).
https://doi.org/10.23919/DATE.2017.7927096'
bibtex: '@inproceedings{Ho_Ashraf_Kaufmann_Platzner_2017, title={Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor}, DOI={10.23919/DATE.2017.7927096},
booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, author={Ho,
Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}, year={2017}
}'
chicago: 'Ho, Nam, Ishraq Ibne Ashraf, Paul Kaufmann, and Marco Platzner. “Accurate
Private/Shared Classification of Memory Accesses: A Run-Time Analysis System for
the LEON3 Multi-Core Processor.” In Proc. Design, Automation and Test in Europe
Conf. (DATE), 2017. https://doi.org/10.23919/DATE.2017.7927096.'
ieee: 'N. Ho, I. I. Ashraf, P. Kaufmann, and M. Platzner, “Accurate Private/Shared
Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core
Processor,” in Proc. Design, Automation and Test in Europe Conf. (DATE),
2017.'
mla: 'Ho, Nam, et al. “Accurate Private/Shared Classification of Memory Accesses:
A Run-Time Analysis System for the LEON3 Multi-Core Processor.” Proc. Design,
Automation and Test in Europe Conf. (DATE), 2017, doi:10.23919/DATE.2017.7927096.'
short: 'N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation
and Test in Europe Conf. (DATE), 2017.'
date_created: 2019-07-10T11:17:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.23919/DATE.2017.7927096
language:
- iso: eng
publication: Proc. Design, Automation and Test in Europe Conf. (DATE)
status: public
title: 'Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis
System for the LEON3 Multi-core Processor'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10676'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International
Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144'
apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
In 2017 International Conference on Field Programmable Technology (ICFPT)
(pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144'
bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
DOI={10.1109/FPT.2017.8280144},
booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
}'
chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
In 2017 International Conference on Field Programmable Technology (ICFPT),
215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.'
ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International
Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.'
mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference
on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.'
short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
multi-core processor'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '10761'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Ho N, Platzner M. Evaluation Methodology for Complex Non-deterministic
Functions: A Case Study in Metaheuristic Optimization of Caches. In: Adaptive
Hardware and Systems (AHS). IEEE; 2017. doi:10.1109/AHS.2017.8046380'
apa: 'Kaufmann, P., Ho, N., & Platzner, M. (2017). Evaluation Methodology for
Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization
of Caches. In Adaptive Hardware and Systems (AHS). IEEE. https://doi.org/10.1109/AHS.2017.8046380'
bibtex: '@inproceedings{Kaufmann_Ho_Platzner_2017, title={Evaluation Methodology
for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization
of Caches}, DOI={10.1109/AHS.2017.8046380},
booktitle={Adaptive Hardware and Systems (AHS)}, publisher={IEEE}, author={Kaufmann,
Paul and Ho, Nam and Platzner, Marco}, year={2017} }'
chicago: 'Kaufmann, Paul, Nam Ho, and Marco Platzner. “Evaluation Methodology for
Complex Non-Deterministic Functions: A Case Study in Metaheuristic Optimization
of Caches.” In Adaptive Hardware and Systems (AHS). IEEE, 2017. https://doi.org/10.1109/AHS.2017.8046380.'
ieee: 'P. Kaufmann, N. Ho, and M. Platzner, “Evaluation Methodology for Complex
Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches,”
in Adaptive Hardware and Systems (AHS), 2017.'
mla: 'Kaufmann, Paul, et al. “Evaluation Methodology for Complex Non-Deterministic
Functions: A Case Study in Metaheuristic Optimization of Caches.” Adaptive
Hardware and Systems (AHS), IEEE, 2017, doi:10.1109/AHS.2017.8046380.'
short: 'P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS),
IEEE, 2017.'
date_created: 2019-07-10T12:07:01Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/AHS.2017.8046380
language:
- iso: eng
publication: Adaptive Hardware and Systems (AHS)
publisher: IEEE
status: public
title: 'Evaluation Methodology for Complex Non-deterministic Functions: A Case Study
in Metaheuristic Optimization of Caches'
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10780'
author:
- first_name: Zakarya
full_name: Guettatfi, Zakarya
last_name: Guettatfi
- first_name: Philipp
full_name: Hübner, Philipp
last_name: Hübner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Bernhard
full_name: Rinner, Bernhard
last_name: Rinner
citation:
ama: 'Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness
as design approach for visual sensor nodes. In: 12th International Symposium
on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8.
doi:10.1109/ReCoSoC.2017.8016147'
apa: Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational
self-awareness as design approach for visual sensor nodes. In 12th International
Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
(pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147
bibtex: '@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational
self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147},
booktitle={12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and
Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }'
chicago: Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner.
“Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In
12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip
(ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.
ieee: Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness
as design approach for visual sensor nodes,” in 12th International Symposium
on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp.
1–8.
mla: Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach
for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric
Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.
short: 'Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International
Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017,
pp. 1–8.'
date_created: 2019-07-10T12:13:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReCoSoC.2017.8016147
keyword:
- embedded systems
- image sensors
- power aware computing
- wireless sensor networks
- Zynq-based VSN node prototype
- computational self-awareness
- design approach
- platform levels
- power consumption
- visual sensor networks
- visual sensor nodes
- Cameras
- Hardware
- Middleware
- Multicore processing
- Operating systems
- Runtime
- Reconfigurable platforms
- distributed embedded systems
- performance-resource trade-off
- self-awareness
- visual sensor nodes
language:
- iso: eng
page: 1-8
publication: 12th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip (ReCoSoC)
status: public
title: Computational self-awareness as design approach for visual sensor nodes
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '14893'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh Ben
full_name: Abdallah, Riadh Ben
last_name: Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Abdallah RB, Khalgui M, Platzner M. I-Codesign: A Codesign Methodology
for Reconfigurable Embedded Systems. In: Communications in Computer and Information
Science. Cham: Springer ; 2017. doi:10.1007/978-3-319-62569-0_8'
apa: 'Ghribi, I., Abdallah, R. B., Khalgui, M., & Platzner, M. (2017). I-Codesign:
A Codesign Methodology for Reconfigurable Embedded Systems. In Communications
in Computer and Information Science. Cham: Springer . https://doi.org/10.1007/978-3-319-62569-0_8'
bibtex: '@inproceedings{Ghribi_Abdallah_Khalgui_Platzner_2017, place={Cham}, title={I-Codesign:
A Codesign Methodology for Reconfigurable Embedded Systems}, DOI={10.1007/978-3-319-62569-0_8},
booktitle={Communications in Computer and Information Science}, publisher={Springer
}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner,
Marco}, year={2017} }'
chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner.
“I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.” In Communications
in Computer and Information Science. Cham: Springer , 2017. https://doi.org/10.1007/978-3-319-62569-0_8.'
ieee: 'I. Ghribi, R. B. Abdallah, M. Khalgui, and M. Platzner, “I-Codesign: A Codesign
Methodology for Reconfigurable Embedded Systems,” in Communications in Computer
and Information Science, 2017.'
mla: 'Ghribi, Ines, et al. “I-Codesign: A Codesign Methodology for Reconfigurable
Embedded Systems.” Communications in Computer and Information Science,
Springer , 2017, doi:10.1007/978-3-319-62569-0_8.'
short: 'I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in
Computer and Information Science, Springer , Cham, 2017.'
date_created: 2019-11-12T08:33:13Z
date_updated: 2022-01-06T06:52:10Z
department:
- _id: '78'
doi: 10.1007/978-3-319-62569-0_8
language:
- iso: eng
place: Cham
publication: Communications in Computer and Information Science
publication_identifier:
isbn:
- '9783319625683'
- '9783319625690'
issn:
- 1865-0929
- 1865-0937
publication_status: published
publisher: 'Springer '
status: public
title: 'I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '222'
abstract:
- lang: eng
text: Virtual field programmable gate arrays (FPGA) are overlay architectures realized
on top of physical FPGAs. They are proposed to enhance or abstract away from the
physical FPGA for experimenting with novel architectures and design tool flows.
In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into
a complete configurable system-on-chip. Such an embedding is required to fully
harness the potential of virtual FPGAs, in particular to give the virtual circuits
access to main memory and operating system services, and to enable a concurrent
operation of virtualized and non-virtualized circuitry. We discuss our extension
to ZUMA and its embedding into the ReconOS operating system for hardware/software
systems. Furthermore, we present an open source tool flow to synthesize configurations
for the virtual FPGA, along with an analysis of the area and delay overheads involved.
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Arne
full_name: Bockhorn, Arne
last_name: Bockhorn
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for
Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers &
Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005
apa: Wiersema, T., Bockhorn, A., & Platzner, M. (2016). An Architecture and
Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.
Computers & Electrical Engineering, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005
bibtex: '@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design
Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip},
DOI={10.1016/j.compeleceng.2016.04.005},
journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema,
Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122}
}'
chicago: Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and
Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.”
Computers & Electrical Engineering, 2016, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005.
ieee: T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool
Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers
& Electrical Engineering, pp. 112--122, 2016.
mla: Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding
a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical
Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005.
short: T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering
(2016) 112--122.
date_created: 2017-10-17T12:41:35Z
date_updated: 2022-01-06T06:55:29Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1016/j.compeleceng.2016.04.005
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:36:08Z
date_updated: 2018-03-21T10:36:08Z
file_id: '1511'
file_name: 222-1-s2.0-S0045790616300684-main.pdf
file_size: 931048
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:36:08Z
has_accepted_license: '1'
language:
- iso: eng
page: 112--122
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Computers & Electrical Engineering
publisher: Elsevier
status: public
title: An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable
System-on-Chip
type: journal_article
user_id: '477'
year: '2016'
...
---
_id: '5812'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Linus
full_name: Witschen, Linus
last_name: Witschen
- first_name: Georg
full_name: Thombansen, Georg
last_name: Thombansen
- first_name: Florian
full_name: Kraus, Florian
id: '14053'
last_name: Kraus
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Agne A, Witschen L, Thombansen G, Kraus F, Platzner M. FPGA-based
acceleration of high density myoelectric signal processing. In: 2015 International
Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2016. doi:10.1109/reconfig.2015.7393312'
apa: Boschmann, A., Agne, A., Witschen, L., Thombansen, G., Kraus, F., & Platzner,
M. (2016). FPGA-based acceleration of high density myoelectric signal processing.
In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).
IEEE. https://doi.org/10.1109/reconfig.2015.7393312
bibtex: '@inproceedings{Boschmann_Agne_Witschen_Thombansen_Kraus_Platzner_2016,
title={FPGA-based acceleration of high density myoelectric signal processing},
DOI={10.1109/reconfig.2015.7393312},
booktitle={2015 International Conference on ReConFigurable Computing and FPGAs
(ReConFig)}, publisher={IEEE}, author={Boschmann, Alexander and Agne, Andreas
and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco},
year={2016} }'
chicago: Boschmann, Alexander, Andreas Agne, Linus Witschen, Georg Thombansen, Florian
Kraus, and Marco Platzner. “FPGA-Based Acceleration of High Density Myoelectric
Signal Processing.” In 2015 International Conference on ReConFigurable Computing
and FPGAs (ReConFig). IEEE, 2016. https://doi.org/10.1109/reconfig.2015.7393312.
ieee: A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, and M. Platzner,
“FPGA-based acceleration of high density myoelectric signal processing,” in 2015
International Conference on ReConFigurable Computing and FPGAs (ReConFig),
2016.
mla: Boschmann, Alexander, et al. “FPGA-Based Acceleration of High Density Myoelectric
Signal Processing.” 2015 International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2016, doi:10.1109/reconfig.2015.7393312.
short: 'A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner,
in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig),
IEEE, 2016.'
date_created: 2018-11-23T15:00:28Z
date_updated: 2022-01-06T07:02:42Z
department:
- _id: '78'
doi: 10.1109/reconfig.2015.7393312
extern: '1'
language:
- iso: eng
publication: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
isbn:
- '9781467394062'
publication_status: published
publisher: IEEE
status: public
title: FPGA-based acceleration of high density myoelectric signal processing
type: conference
user_id: '14053'
year: '2016'
...
---
_id: '10622'
author:
- first_name: Jahanzeb
full_name: Anwer, Jahanzeb
last_name: Anwer
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Anwer J, Platzner M. Boolean Difference Based Reliability Evaluation of Fault
Tolerant Circuit Structures on FPGAs. In: Euromicro Conference on Digital System
Design (DSD). ; 2016. doi:10.1109/DSD.2016.35'
apa: Anwer, J., & Platzner, M. (2016). Boolean Difference Based Reliability
Evaluation of Fault Tolerant Circuit Structures on FPGAs. In Euromicro Conference
on Digital System Design (DSD). https://doi.org/10.1109/DSD.2016.35
bibtex: '@inproceedings{Anwer_Platzner_2016, title={Boolean Difference Based Reliability
Evaluation of Fault Tolerant Circuit Structures on FPGAs}, DOI={10.1109/DSD.2016.35},
booktitle={Euromicro Conference on Digital System Design (DSD)}, author={Anwer,
Jahanzeb and Platzner, Marco}, year={2016} }'
chicago: Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability
Evaluation of Fault Tolerant Circuit Structures on FPGAs.” In Euromicro Conference
on Digital System Design (DSD), 2016. https://doi.org/10.1109/DSD.2016.35.
ieee: J. Anwer and M. Platzner, “Boolean Difference Based Reliability Evaluation
of Fault Tolerant Circuit Structures on FPGAs,” in Euromicro Conference on
Digital System Design (DSD), 2016.
mla: Anwer, Jahanzeb, and Marco Platzner. “Boolean Difference Based Reliability
Evaluation of Fault Tolerant Circuit Structures on FPGAs.” Euromicro Conference
on Digital System Design (DSD), 2016, doi:10.1109/DSD.2016.35.
short: 'J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design
(DSD), 2016.'
date_created: 2019-07-10T09:33:00Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
doi: 10.1109/DSD.2016.35
language:
- iso: eng
publication: Euromicro Conference on Digital System Design (DSD)
status: public
title: Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures
on FPGAs
type: conference
user_id: '3118'
year: '2016'
...
---
_id: '10661'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Graf T, Platzner M. Adaptive playouts for online learning of policies during
Monte Carlo Tree Search. Journal Theoretical Computer Science. 2016;644:53-62.
doi:10.1016/j.tcs.2016.06.029
apa: Graf, T., & Platzner, M. (2016). Adaptive playouts for online learning
of policies during Monte Carlo Tree Search. Journal Theoretical Computer Science,
644, 53–62. https://doi.org/10.1016/j.tcs.2016.06.029
bibtex: '@article{Graf_Platzner_2016, title={Adaptive playouts for online learning
of policies during Monte Carlo Tree Search}, volume={644}, DOI={10.1016/j.tcs.2016.06.029},
journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf,
Tobias and Platzner, Marco}, year={2016}, pages={53–62} }'
chicago: 'Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning
of Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science
644 (2016): 53–62. https://doi.org/10.1016/j.tcs.2016.06.029.'
ieee: T. Graf and M. Platzner, “Adaptive playouts for online learning of policies
during Monte Carlo Tree Search,” Journal Theoretical Computer Science,
vol. 644, pp. 53–62, 2016.
mla: Graf, Tobias, and Marco Platzner. “Adaptive Playouts for Online Learning of
Policies during Monte Carlo Tree Search.” Journal Theoretical Computer Science,
vol. 644, Elsevier, 2016, pp. 53–62, doi:10.1016/j.tcs.2016.06.029.
short: T. Graf, M. Platzner, Journal Theoretical Computer Science 644 (2016) 53–62.
date_created: 2019-07-10T11:14:43Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1016/j.tcs.2016.06.029
intvolume: ' 644'
language:
- iso: eng
page: 53-62
publication: Journal Theoretical Computer Science
publisher: Elsevier
status: public
title: Adaptive playouts for online learning of policies during Monte Carlo Tree Search
type: journal_article
user_id: '3118'
volume: 644
year: '2016'
...
---
_id: '10712'
author:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Meisner S, Platzner M. Thread Shadowing: On the Effectiveness of Error Detection
at the Hardware Thread Level. In: Reconfigurable Computing and FPGAs (ReConFig),
2016 International Conference On. ReConFig. ; 2016:1-8. doi:10.1109/ReConFig.2016.7857193'
apa: 'Meisner, S., & Platzner, M. (2016). Thread Shadowing: On the Effectiveness
of Error Detection at the Hardware Thread Level. In Reconfigurable Computing
and FPGAs (ReConFig), 2016 International Conference on (pp. 1–8). https://doi.org/10.1109/ReConFig.2016.7857193'
bibtex: '@inproceedings{Meisner_Platzner_2016, series={ReConFig}, title={Thread
Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level},
DOI={10.1109/ReConFig.2016.7857193},
booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference
on}, author={Meisner, Sebastian and Platzner, Marco}, year={2016}, pages={1–8},
collection={ReConFig} }'
chicago: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness
of Error Detection at the Hardware Thread Level.” In Reconfigurable Computing
and FPGAs (ReConFig), 2016 International Conference On, 1–8. ReConFig, 2016.
https://doi.org/10.1109/ReConFig.2016.7857193.'
ieee: 'S. Meisner and M. Platzner, “Thread Shadowing: On the Effectiveness of Error
Detection at the Hardware Thread Level,” in Reconfigurable Computing and FPGAs
(ReConFig), 2016 International Conference on, 2016, pp. 1–8.'
mla: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: On the Effectiveness
of Error Detection at the Hardware Thread Level.” Reconfigurable Computing
and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8, doi:10.1109/ReConFig.2016.7857193.'
short: 'S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig),
2016 International Conference On, 2016, pp. 1–8.'
date_created: 2019-07-10T11:47:25Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReConFig.2016.7857193
language:
- iso: eng
page: 1-8
publication: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference
on
series_title: ReConFig
status: public
title: 'Thread Shadowing: On the Effectiveness of Error Detection at the Hardware
Thread Level'
type: conference
user_id: '3118'
year: '2016'
...
---
_id: '10766'
author:
- first_name: Ines
full_name: Ghribi, Ines
last_name: Ghribi
- first_name: Riadh
full_name: Ben Abdallah, Riadh
last_name: Ben Abdallah
- first_name: Mohamed
full_name: Khalgui, Mohamed
last_name: Khalgui
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ghribi I, Ben Abdallah R, Khalgui M, Platzner M. RCo-Design: New Visual Environment
for Reconfigurable Embedded Systems. In: Proceedings of the 30th European Simulation
and Modelling Conference (ESM). ; 2016.'
apa: 'Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). RCo-Design:
New Visual Environment for Reconfigurable Embedded Systems. In Proceedings
of the 30th European Simulation and Modelling Conference (ESM).'
bibtex: '@inproceedings{Ghribi_Ben Abdallah_Khalgui_Platzner_2016, title={RCo-Design:
New Visual Environment for Reconfigurable Embedded Systems}, booktitle={Proceedings
of the 30th European Simulation and Modelling Conference (ESM)}, author={Ghribi,
Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, year={2016}
}'
chicago: 'Ghribi, Ines, Riadh Ben Abdallah, Mohamed Khalgui, and Marco Platzner.
“RCo-Design: New Visual Environment for Reconfigurable Embedded Systems.” In Proceedings
of the 30th European Simulation and Modelling Conference (ESM), 2016.'
ieee: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, and M. Platzner, “RCo-Design: New
Visual Environment for Reconfigurable Embedded Systems,” in Proceedings of
the 30th European Simulation and Modelling Conference (ESM), 2016.'
mla: 'Ghribi, Ines, et al. “RCo-Design: New Visual Environment for Reconfigurable
Embedded Systems.” Proceedings of the 30th European Simulation and Modelling
Conference (ESM), 2016.'
short: 'I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of
the 30th European Simulation and Modelling Conference (ESM), 2016.'
date_created: 2019-07-10T12:07:54Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publication: Proceedings of the 30th European Simulation and Modelling Conference
(ESM)
status: public
title: 'RCo-Design: New Visual Environment for Reconfigurable Embedded Systems'
type: conference
user_id: '3118'
year: '2016'
...