[{"type":"preprint","abstract":[{"text":"While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17% for LUTs, 66% for DSPs, and 22% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms.","lang":"eng"}],"status":"public","_id":"61152","department":[{"_id":"78"}],"user_id":"55631","language":[{"iso":"eng"}],"publication_status":"submitted","year":"2025","citation":{"chicago":"Umuroglu, Yaman, Christoph Berganski, Felix Jentzsch, Michal Danilowicz, Tomasz Kryjak, Charalampos Bezaitis, Magnus Sjalander, et al. “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators,” n.d.","ieee":"Y. Umuroglu <i>et al.</i>, “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.” .","ama":"Umuroglu Y, Berganski C, Jentzsch F, et al. SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.","mla":"Umuroglu, Yaman, et al. <i>SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators</i>.","short":"Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis, M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, (n.d.).","bibtex":"@article{Umuroglu_Berganski_Jentzsch_Danilowicz_Kryjak_Bezaitis_Sjalander_Colbert_Preusser_Petri-Koenig_et al., title={SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators}, author={Umuroglu, Yaman and Berganski, Christoph and Jentzsch, Felix and Danilowicz, Michal and Kryjak, Tomasz and Bezaitis, Charalampos and Sjalander, Magnus and Colbert, Ian and Preusser, Thomas and Petri-Koenig, Jakoba and et al.} }","apa":"Umuroglu, Y., Berganski, C., Jentzsch, F., Danilowicz, M., Kryjak, T., Bezaitis, C., Sjalander, M., Colbert, I., Preusser, T., Petri-Koenig, J., &#38; Blott, M. (n.d.). <i>SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators</i>."},"date_updated":"2025-09-08T14:13:47Z","date_created":"2025-09-08T14:10:39Z","author":[{"first_name":"Yaman","last_name":"Umuroglu","full_name":"Umuroglu, Yaman"},{"full_name":"Berganski, Christoph","id":"98854","last_name":"Berganski","first_name":"Christoph"},{"orcid":"0000-0003-4987-5708","last_name":"Jentzsch","full_name":"Jentzsch, Felix","id":"55631","first_name":"Felix"},{"full_name":"Danilowicz, Michal","last_name":"Danilowicz","first_name":"Michal"},{"first_name":"Tomasz","full_name":"Kryjak, Tomasz","last_name":"Kryjak"},{"first_name":"Charalampos","last_name":"Bezaitis","full_name":"Bezaitis, Charalampos"},{"first_name":"Magnus","full_name":"Sjalander, Magnus","last_name":"Sjalander"},{"first_name":"Ian","full_name":"Colbert, Ian","last_name":"Colbert"},{"first_name":"Thomas","full_name":"Preusser, Thomas","last_name":"Preusser"},{"full_name":"Petri-Koenig, Jakoba","last_name":"Petri-Koenig","first_name":"Jakoba"},{"first_name":"Michaela","last_name":"Blott","full_name":"Blott, Michaela"}],"title":"SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators"},{"language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"98854","_id":"56481","status":"public","type":"conference","conference":{"start_date":"2024-12-10","name":"International Conference on Field Programmable Technology","location":"Sydney","end_date":"2024-12-12"},"title":"FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers","date_created":"2024-10-10T07:49:13Z","author":[{"first_name":"Christoph","last_name":"Berganski","full_name":"Berganski, Christoph","id":"98854"},{"first_name":"Felix","id":"55631","full_name":"Jentzsch, Felix","last_name":"Jentzsch","orcid":"0000-0003-4987-5708"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"first_name":"Max","last_name":"Kuhmichel","full_name":"Kuhmichel, Max"},{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"}],"date_updated":"2024-10-10T07:52:06Z","citation":{"ama":"Berganski C, Jentzsch F, Platzner M, Kuhmichel M, Giefers H. FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers. In: ; 2024.","ieee":"C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, and H. Giefers, “FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers,” presented at the International Conference on Field Programmable Technology, Sydney, 2024.","chicago":"Berganski, Christoph, Felix Jentzsch, Marco Platzner, Max Kuhmichel, and Heiner Giefers. “FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers,” 2024.","short":"C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, H. Giefers, in: 2024.","bibtex":"@inproceedings{Berganski_Jentzsch_Platzner_Kuhmichel_Giefers_2024, title={FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers}, author={Berganski, Christoph and Jentzsch, Felix and Platzner, Marco and Kuhmichel, Max and Giefers, Heiner}, year={2024} }","mla":"Berganski, Christoph, et al. <i>FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers</i>. 2024.","apa":"Berganski, C., Jentzsch, F., Platzner, M., Kuhmichel, M., &#38; Giefers, H. (2024). <i>FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers</i>. International Conference on Field Programmable Technology, Sydney."},"year":"2024"},{"has_accepted_license":"1","citation":{"chicago":"Boschmann, Alexander, Lennart Clausing, Felix Jentzsch, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip.” In <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:225–36. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. <a href=\"https://doi.org/10.5281/zenodo.8068713\">https://doi.org/10.5281/zenodo.8068713</a>.","ieee":"A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, and M. Platzner, “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip,” in <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i>, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 225–236.","ama":"Boschmann A, Clausing L, Jentzsch F, Ghasemzadeh Mohammadi H, Platzner M. Flexible Industrial Analytics on Reconfigurable Systems-On-Chip. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:225-236. doi:<a href=\"https://doi.org/10.5281/zenodo.8068713\">10.5281/zenodo.8068713</a>","apa":"Boschmann, A., Clausing, L., Jentzsch, F., Ghasemzadeh Mohammadi, H., &#38; Platzner, M. (2023). Flexible Industrial Analytics on Reconfigurable Systems-On-Chip. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, &#38; H. Wehrheim (Eds.), <i>On-The-Fly Computing -- Individualized IT-services in dynamic markets</i> (Vol. 412, pp. 225–236). Heinz Nixdorf Institut, Universität Paderborn. <a href=\"https://doi.org/10.5281/zenodo.8068713\">https://doi.org/10.5281/zenodo.8068713</a>","short":"A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, M. Platzner, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 225–236.","mla":"Boschmann, Alexander, et al. “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip.” <i>On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets</i>, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 225–36, doi:<a href=\"https://doi.org/10.5281/zenodo.8068713\">10.5281/zenodo.8068713</a>.","bibtex":"@inbook{Boschmann_Clausing_Jentzsch_Ghasemzadeh Mohammadi_Platzner_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Flexible Industrial Analytics on Reconfigurable Systems-On-Chip}, volume={412}, DOI={<a href=\"https://doi.org/10.5281/zenodo.8068713\">10.5281/zenodo.8068713</a>}, booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Boschmann, Alexander and Clausing, Lennart and Jentzsch, Felix and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, pages={225–236}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }"},"intvolume":"       412","page":"225-236","place":"Paderborn","author":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"},{"last_name":"Clausing","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","id":"74287","first_name":"Lennart"},{"first_name":"Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch","full_name":"Jentzsch, Felix","id":"55631"},{"first_name":"Hassan","last_name":"Ghasemzadeh Mohammadi","full_name":"Ghasemzadeh Mohammadi, Hassan","id":"61186"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"volume":412,"date_updated":"2024-05-02T10:33:26Z","oa":"1","doi":"10.5281/zenodo.8068713","type":"book_chapter","status":"public","editor":[{"first_name":"Claus-Jochen","full_name":"Haake, Claus-Jochen","last_name":"Haake"},{"first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide"},{"last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Wachsmuth","full_name":"Wachsmuth, Henning","first_name":"Henning"},{"full_name":"Wehrheim, Heike","last_name":"Wehrheim","first_name":"Heike"}],"user_id":"398","series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","department":[{"_id":"7"},{"_id":"78"}],"project":[{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"}],"_id":"45899","file_date_updated":"2023-07-07T11:14:23Z","year":"2023","date_created":"2023-07-07T08:36:58Z","publisher":"Heinz Nixdorf Institut, Universität Paderborn","title":"Flexible Industrial Analytics on Reconfigurable Systems-On-Chip","publication":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","file":[{"file_size":468973,"file_id":"45900","file_name":"T1-Chapter-SFB-Buch-Final.pdf","access_level":"open_access","date_updated":"2023-07-07T11:14:23Z","creator":"florida","date_created":"2023-07-07T08:36:40Z","relation":"main_file","content_type":"application/pdf"}],"language":[{"iso":"eng"}],"ddc":["004"]},{"date_updated":"2024-05-13T13:47:31Z","publisher":"IEEE","date_created":"2024-04-11T16:38:42Z","author":[{"first_name":"Felix","full_name":"Jentzsch, Felix","id":"55631","orcid":"0000-0003-4987-5708","last_name":"Jentzsch"}],"title":"Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML","doi":"10.1109/fpl60245.2023.00066","publication_status":"published","year":"2023","citation":{"apa":"Jentzsch, F. (2023). Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML. <i>2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)</i>. <a href=\"https://doi.org/10.1109/fpl60245.2023.00066\">https://doi.org/10.1109/fpl60245.2023.00066</a>","mla":"Jentzsch, Felix. “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML.” <i>2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/fpl60245.2023.00066\">10.1109/fpl60245.2023.00066</a>.","short":"F. Jentzsch, in: 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2023.","bibtex":"@inproceedings{Jentzsch_2023, title={Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML}, DOI={<a href=\"https://doi.org/10.1109/fpl60245.2023.00066\">10.1109/fpl60245.2023.00066</a>}, booktitle={2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Jentzsch, Felix}, year={2023} }","ama":"Jentzsch F. Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML. In: <i>2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/fpl60245.2023.00066\">10.1109/fpl60245.2023.00066</a>","chicago":"Jentzsch, Felix. “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML.” In <i>2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/fpl60245.2023.00066\">https://doi.org/10.1109/fpl60245.2023.00066</a>.","ieee":"F. Jentzsch, “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML,” 2023, doi: <a href=\"https://doi.org/10.1109/fpl60245.2023.00066\">10.1109/fpl60245.2023.00066</a>."},"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"53435","user_id":"398","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"conference","publication":"2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)","status":"public"},{"type":"journal_article","status":"public","_id":"33990","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"78"}],"user_id":"55631","publication_status":"published","intvolume":"        42","page":"125-133","citation":{"ieee":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,” <i>IEEE Micro</i>, vol. 42, no. 6, pp. 125–133, 2022, doi: <a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>.","chicago":"Jentzsch, Felix, Yaman Umuroglu, Alessandro Pappalardo, Michaela Blott, and Marco Platzner. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” <i>IEEE Micro</i> 42, no. 6 (2022): 125–33. <a href=\"https://doi.org/10.1109/MM.2022.3202091\">https://doi.org/10.1109/MM.2022.3202091</a>.","ama":"Jentzsch F, Umuroglu Y, Pappalardo A, Blott M, Platzner M. RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. <i>IEEE Micro</i>. 2022;42(6):125-133. doi:<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>","apa":"Jentzsch, F., Umuroglu, Y., Pappalardo, A., Blott, M., &#38; Platzner, M. (2022). RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. <i>IEEE Micro</i>, <i>42</i>(6), 125–133. <a href=\"https://doi.org/10.1109/MM.2022.3202091\">https://doi.org/10.1109/MM.2022.3202091</a>","short":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro 42 (2022) 125–133.","mla":"Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” <i>IEEE Micro</i>, vol. 42, no. 6, IEEE, 2022, pp. 125–33, doi:<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>.","bibtex":"@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}, volume={42}, DOI={<a href=\"https://doi.org/10.1109/MM.2022.3202091\">10.1109/MM.2022.3202091</a>}, number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}, year={2022}, pages={125–133} }"},"date_updated":"2023-04-04T15:09:17Z","volume":42,"author":[{"first_name":"Felix","id":"55631","full_name":"Jentzsch, Felix","orcid":"0000-0003-4987-5708","last_name":"Jentzsch"},{"first_name":"Yaman","last_name":"Umuroglu","full_name":"Umuroglu, Yaman"},{"first_name":"Alessandro","last_name":"Pappalardo","full_name":"Pappalardo, Alessandro"},{"first_name":"Michaela","full_name":"Blott, Michaela","last_name":"Blott"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"doi":"10.1109/MM.2022.3202091","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9933377"}],"publication":"IEEE Micro","abstract":[{"text":"Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.","lang":"eng"}],"language":[{"iso":"eng"}],"issue":"6","year":"2022","publisher":"IEEE","date_created":"2022-11-03T14:42:16Z","title":"RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures"},{"year":"2021","citation":{"mla":"Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>, Springer, 2021, doi:<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>.","bibtex":"@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021, title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}, DOI={<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>}, booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil  and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }, year={2021} }","short":"H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare, S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in:  Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.","apa":"Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare, S., Manjunatha, S., Platzner, M., Boschmann, A., &#38; Schollbach, D. (2021). FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>","ama":"Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. In: <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. Springer; 2021. doi:<a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>","ieee":"H. Ghasemzadeh Mohammadi <i>et al.</i>, “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,” 2021, doi: <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>.","chicago":"Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil  Arshad, Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk  Schollbach. “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.” In <i> Machine Learning and Principles and Practice of Knowledge Discovery in Databases</i>. Springer, 2021. <a href=\"https://doi.org/10.1007/978-3-030-93736-2_27\">https://doi.org/10.1007/978-3-030-93736-2_27</a>."},"publisher":"Springer","date_updated":"2023-09-15T15:09:07Z","author":[{"id":"61186","full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan"},{"full_name":"Jentzsch, Felix","id":"55631","orcid":"0000-0003-4987-5708","last_name":"Jentzsch","first_name":"Felix"},{"first_name":"Maurice","last_name":"Kuschel","full_name":"Kuschel, Maurice"},{"last_name":"Arshad","full_name":"Arshad, Rahil ","first_name":"Rahil "},{"first_name":"Sneha","last_name":"Rautmare","full_name":"Rautmare, Sneha"},{"full_name":"Manjunatha, Suraj","last_name":"Manjunatha","first_name":"Suraj"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Alexander","last_name":"Boschmann","full_name":"Boschmann, Alexander"},{"last_name":"Schollbach","full_name":"Schollbach, Dirk ","first_name":"Dirk "}],"date_created":"2022-04-18T10:16:55Z","title":"FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics","doi":"https://doi.org/10.1007/978-3-030-93736-2_27","type":"conference","publication":" Machine Learning and Principles and Practice of Knowledge Discovery in Databases","status":"public","project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"grant_number":"160364472","_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"}],"_id":"30908","user_id":"477","department":[{"_id":"78"}],"language":[{"iso":"eng"}]}]