[{"conference":{"start_date":"14.03.2022","end_date":"15.03.2022"},"title":"The Scale4Edge RISC-V Ecosystem","date_created":"2022-01-13T07:27:46Z","author":[{"first_name":"Wolfgang","full_name":"Ecker, Wolfgang","last_name":"Ecker"},{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"},{"first_name":"Reinhold","full_name":"Heckmann, Reinhold","last_name":"Heckmann"},{"last_name":"Krstic","full_name":"Krstic, Milos","first_name":"Milos"},{"first_name":"Vladimir","last_name":"Herdt","full_name":"Herdt, Vladimir"},{"last_name":"Drechsler","full_name":"Drechsler, Rolf","first_name":"Rolf"},{"first_name":"Gerhard","last_name":"Angst","full_name":"Angst, Gerhard"},{"last_name":"Wimmer","full_name":"Wimmer, Ralf","first_name":"Ralf"},{"full_name":"Mauderer, Andreas","last_name":"Mauderer","first_name":"Andreas"},{"first_name":"Rafael","full_name":"Stahl, Rafael","last_name":"Stahl"},{"first_name":"Karsten","last_name":"Emrich","full_name":"Emrich, Karsten"},{"first_name":"Daniel","last_name":"Mueller-Gritschneder","full_name":"Mueller-Gritschneder, Daniel"},{"last_name":"Becker","full_name":"Becker, Bernd","first_name":"Bernd"},{"first_name":"Philipp","full_name":"Scholl, Philipp","last_name":"Scholl"},{"first_name":"Eyck","last_name":"Jentzsch","full_name":"Jentzsch, Eyck"},{"first_name":"Jan","full_name":"Schlamelcher, Jan","last_name":"Schlamelcher"},{"last_name":"Grüttner","full_name":"Grüttner, Kim","first_name":"Kim"},{"full_name":"Bernardo, Paul Palomero","last_name":"Bernardo","first_name":"Paul Palomero"},{"first_name":"Oliver","last_name":"Brinkmann","full_name":"Brinkmann, Oliver"},{"full_name":"Damian, Mihaela","last_name":"Damian","first_name":"Mihaela"},{"last_name":"Oppermann","full_name":"Oppermann, Julian","first_name":"Julian"},{"first_name":"Andreas","last_name":"Koch","full_name":"Koch, Andreas"},{"last_name":"Bormann","full_name":"Bormann, Jörg","first_name":"Jörg"},{"first_name":"Johannes","full_name":"Partzsch, Johannes","last_name":"Partzsch"},{"last_name":"Mayr","full_name":"Mayr, Christian","first_name":"Christian"},{"first_name":"Wolfgang","last_name":"Kunz","full_name":"Kunz, Wolfgang"}],"date_updated":"2022-01-13T07:30:38Z","citation":{"short":"W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.","bibtex":"@inproceedings{Ecker_Adelt_Müller_Heckmann_Krstic_Herdt_Drechsler_Angst_Wimmer_Mauderer_et al._2022, title={The Scale4Edge RISC-V Ecosystem}, booktitle={In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)}, author={Ecker, Wolfgang and Adelt, Peer and Müller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and et al.}, year={2022} }","mla":"Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>, 2022.","apa":"Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., Angst, G., Wimmer, R., Mauderer, A., Stahl, R., Emrich, K., Mueller-Gritschneder, D., Becker, B., Scholl, P., Jentzsch, E., Schlamelcher, J., Grüttner, K., Bernardo, P. P., … Kunz, W. (2022). The Scale4Edge RISC-V Ecosystem. <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>.","ama":"Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>. ; 2022.","chicago":"Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In <i>In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)</i>, 2022.","ieee":"W. Ecker <i>et al.</i>, “The Scale4Edge RISC-V Ecosystem,” 2022."},"year":"2022","language":[{"iso":"eng"}],"user_id":"15931","department":[{"_id":"58"}],"_id":"29302","status":"public","abstract":[{"text":"This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned\r\ndemonstrators, which will be used in their evaluation.","lang":"eng"}],"type":"conference","publication":"In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)"},{"status":"public","abstract":[{"text":"Fault coverage analysis and fault simulation are well-established methods for the qualification of test vectors in hardware design. However, their role in virtual prototyping and the correlation to later steps in the design process need further investigation. We introduce a metric for RISC-V instruction and register coverage for binary software. The metric measures if RISC-V instruction types are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied by the means of a virtual prototype which is based on an abstract instruction and register model with direct correspondence to their bit level representation. In this context, we analyzed three different openly available test suites: the RISC-V architectural testing framework, the RISC-V unit tests, and programs which are automatically generated by the RISC-V Torture test generator. We discuss their tradeoffs and show that by combining them to a unified test suite we can arrive at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage.","lang":"eng"}],"publication":"MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"5603","_id":"32125","citation":{"mla":"Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE}, title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. VDE; 2021."},"place":"Munich, DE","year":"2021","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/9399723","relation":"confirmation"}]},"publication_identifier":{"isbn":["978-3-8007-5500-4"]},"publication_status":"published","conference":{"end_date":"2021-03-19","start_date":"2021-03-18"},"title":"Register and Instruction Coverage Analysis for Different RISC-V ISA Modules","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Christoph","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144"}],"date_created":"2022-06-23T11:52:50Z","date_updated":"2022-06-23T11:54:16Z","publisher":"VDE"},{"publication_status":"published","year":"2021","place":"Munich, DE","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). QEMU zur Simulation von Worst-Case-Ausführungszeiten. <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE}, title={QEMU zur Simulation von Worst-Case-Ausführungszeiten}, booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","mla":"Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, VDE, 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausführungszeiten. In: <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. VDE; 2021.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” In <i>MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Munich, DE: VDE, 2021."},"publisher":"VDE","date_updated":"2022-12-06T13:24:44Z","date_created":"2022-06-23T12:07:10Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Christoph","last_name":"Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618","full_name":"Scheytt, Christoph","id":"37144"}],"title":"QEMU zur Simulation von Worst-Case-Ausführungszeiten","conference":{"end_date":"2021-03-19","start_date":"2021-03-18"},"publication":"MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","type":"conference","abstract":[{"text":"Die Werkzeugdemonstration des QEMU Timing Analyzers (QTA) stellt eine Erweiterung des quelloffenen CPU Emulators QEMU zur Simulation von Softwareprogrammen und deren Worst-Case Zeitverhaltens vor, das durch eine statische Zeitanalyse vorher aus dem Softwareprogramm extrahiert wurde. Der Ablauf der Analyse gliedert sich in mehrere Schritte: Zunächst wird für das zu simulierende Binärprogramm eine WCET-Analyse mit aiT durchgeführt. Im Preprocessing des aiT-Reports wird daraufhin ein WCET-annotierter Kontrollflussgraph erzeugt. Dabei entsprechen die Knoten im Kontrollflussgraph den aiT-Blöcken und die Kanten dem jeweiligen Worst-Case-Zeitverbrauch, um das Programm im aktuellen Ausführungskontext vom Quell- bis zum Zielblock laufen zu lassen. Nach dem Preprocessing werden Binärprogramm und der zuvor erzeugte, zeitannotierte Kontrollflussgraph von QEMU geladen und gemeinsam simuliert.\r\n\r\nDie Implementierung des QTA basiert auf der Standard TGI Plugin API (Tiny Code Generator Plugin API), die seit Ende 2019 mit QEMU V4.2 verfügbar ist. Dieses API erlaubt die Entwicklung von versionsunabhängigen QEMU-Erweiterungen. Die QEMU-QTA-Erweiterung wird zum Zeitpunkt der Werkzeugdemonstration inklusive des ait2qta-Preprozessors unter github.com im Quellcode frei verfügbar sein.\r\n\r\nDie Demonstration geht von einer existierenden aiT-Analyse eines für TriCore© kompilierten binären Softwareprograms aus, erläutert das Kontrollflusszwischenformat und zeigt die zeitannotierte Simulation der Software.","lang":"ger"}],"status":"public","_id":"32132","department":[{"_id":"58"}],"user_id":"5603","keyword":["QEMU","aiT","Zeitannotation","WCET"],"language":[{"iso":"ger"}]},{"author":[{"id":"5603","full_name":"Adelt, Peer","last_name":"Adelt","first_name":"Peer"},{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618"}],"date_created":"2021-09-09T08:30:03Z","user_id":"15931","department":[{"_id":"58"}],"date_updated":"2023-01-31T13:25:48Z","_id":"23992","language":[{"iso":"eng"}],"title":"Register and Instruction Coverage Analysis for Different RISC-V ISA Modules","type":"conference","publication":"Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)","citation":{"ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>, 2021.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>. ; 2021.","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.","mla":"Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” <i>Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021)</i>, 2021."},"status":"public","year":"2021"},{"language":[{"iso":"eng"}],"_id":"24027","department":[{"_id":"58"}],"user_id":"15931","abstract":[{"text":"Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.","lang":"eng"}],"status":"public","publication":"MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop","type":"conference","title":"A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures","date_updated":"2022-01-06T06:56:06Z","author":[{"id":"5603","full_name":"Adelt, Peer","last_name":"Adelt","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","first_name":"Christoph"}],"date_created":"2021-09-09T11:50:19Z","place":"Stuttgart, DE","year":"2020","citation":{"ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. In: <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. ; 2020.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>. Stuttgart, DE, 2020.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.","mla":"Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>, 2020.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2020, place={Stuttgart, DE}, title={A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures}, booktitle={MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2020} }","apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2020). A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. <i>MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop</i>."},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/9094540","relation":"confirmation"}]}},{"abstract":[{"text":"Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.","lang":"eng"}],"status":"public","type":"conference","publication":"29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","language":[{"iso":"eng"}],"_id":"24058","user_id":"15931","department":[{"_id":"58"}],"year":"2019","place":"Rhodos, Griechenland","citation":{"apa":"Koppelmann, B., Adelt, P., Müller, W., &#38; Scheytt, C. (2019). RISC-V Extensions for Bit Manipulation Instructions. <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">https://doi.org/10.1109/PATMOS.2019.8862170</a>","bibtex":"@inproceedings{Koppelmann_Adelt_Müller_Scheytt_2019, place={Rhodos, Griechenland}, title={RISC-V Extensions for Bit Manipulation Instructions}, DOI={<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>}, booktitle={29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, author={Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","short":"B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.","mla":"Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>.","ieee":"B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>.","chicago":"Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.” In <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. Rhodos, Griechenland, 2019. <a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">https://doi.org/10.1109/PATMOS.2019.8862170</a>.","ama":"Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: <i>29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/PATMOS.2019.8862170\">10.1109/PATMOS.2019.8862170</a>"},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/8862170","relation":"confirmation"}]},"title":"RISC-V Extensions for Bit Manipulation Instructions","doi":"10.1109/PATMOS.2019.8862170","conference":{"end_date":"2019.07.03","start_date":"2019.07.01"},"date_updated":"2022-01-06T06:56:06Z","author":[{"full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann","first_name":"Bastian"},{"first_name":"Peer","full_name":"Adelt, Peer","id":"5603","last_name":"Adelt"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","first_name":"Christoph"}],"date_created":"2021-09-09T12:26:14Z"},{"date_updated":"2022-01-06T06:56:06Z","author":[{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph"}],"date_created":"2021-09-09T12:26:16Z","title":"Analyse sicherheitskritischer Software für RISC-V Prozessoren","conference":{"start_date":"2019.04.08","end_date":"2019.04.08"},"publication_identifier":{"isbn":["978-3-8007-4945-4"]},"related_material":{"link":[{"url":"https://www.vde-verlag.de/proceedings-de/454945007.html","relation":"confirmation"}]},"place":"Kaiserslautern, DE","year":"2019","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2019). Analyse sicherheitskritischer Software für RISC-V Prozessoren. <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2019, place={Kaiserslautern, DE}, title={Analyse sicherheitskritischer Software für RISC-V Prozessoren}, booktitle={MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","mla":"Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>, 2019.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer Software für RISC-V Prozessoren. In: <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>. ; 2019.","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” In <i>MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019)</i>. Kaiserslautern, DE, 2019."},"_id":"24060","department":[{"_id":"58"}],"user_id":"15931","language":[{"iso":"eng"}],"publication":"MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)","type":"conference","abstract":[{"text":"In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. ","lang":"ger"}],"status":"public"},{"related_material":{"link":[{"url":"https://www.researchgate.net/publication/334258953_QEMU_for_Dynamic_Memory_Analysis_of_Security_Sensitive_Software","relation":"confirmation"}]},"place":"Florence, Italy","year":"2019","page":"32-34","citation":{"chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” In <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 32–34. Florence, Italy, 2019.","ieee":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in <i> 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019</i>, 2019, pp. 32–34.","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory Analysis of Security Sensitive Software. In: <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>. ; 2019:32-34.","apa":"Adelt, P., Koppelmann, B., Müller, W., Scheytt, C., &#38; Driessen, B. (2019). QEMU for Dynamic Memory Analysis of Security Sensitive Software. <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 32–34.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in:  2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.","mla":"Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” <i> 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019</i>, 2019, pp. 32–34.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Scheytt_Driessen_2019, place={Florence, Italy}, title={QEMU for Dynamic Memory Analysis of Security Sensitive Software}, booktitle={ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}, year={2019}, pages={32–34} }"},"date_updated":"2022-01-06T06:56:06Z","date_created":"2021-09-09T12:26:18Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","first_name":"Christoph"},{"full_name":"Driessen, Benedikt","last_name":"Driessen","first_name":"Benedikt"}],"title":"QEMU for Dynamic Memory Analysis of Security Sensitive Software","publication":" 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019","type":"conference","status":"public","_id":"24061","department":[{"_id":"58"}],"user_id":"15931","language":[{"iso":"eng"}]},{"title":"QEMU Support for RISC-V: Current State and Future Releases","date_updated":"2022-01-06T06:56:06Z","date_created":"2021-09-09T12:26:20Z","author":[{"first_name":"Peer","last_name":"Adelt","id":"5603","full_name":"Adelt, Peer"},{"full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann","first_name":"Bastian"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Christoph","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144"}],"volume":"(Presentation)","year":"2019","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., &#38; Scheytt, C. (2019). QEMU Support for RISC-V: Current State and Future Releases. <i>2nd International Workshop on RISC-V Research Activities</i>, <i>(Presentation)</i>.","mla":"Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” <i>2nd International Workshop on RISC-V Research Activities</i>, vol. (Presentation), 2019.","short":"P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).","bibtex":"@article{Adelt_Koppelmann_Müller_Scheytt_2019, title={QEMU Support for RISC-V: Current State and Future Releases}, volume={(Presentation)}, journal={2nd International Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }","ama":"Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current State and Future Releases. <i>2nd International Workshop on RISC-V Research Activities</i>. 2019;(Presentation).","ieee":"P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” <i>2nd International Workshop on RISC-V Research Activities</i>, vol. (Presentation), 2019.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU Support for RISC-V: Current State and Future Releases.” <i>2nd International Workshop on RISC-V Research Activities</i> (Presentation) (2019)."},"related_material":{"link":[{"relation":"confirmation","url":"https://www.edacentrum.de/veranstaltungen/risc-v/2019/programm"}]},"language":[{"iso":"eng"}],"_id":"24063","user_id":"15931","department":[{"_id":"58"}],"abstract":[{"text":"It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.","lang":"eng"}],"status":"public","type":"journal_article","publication":"2nd International Workshop on RISC-V Research Activities"},{"date_updated":"2022-01-06T06:56:09Z","volume":"Presentation","date_created":"2021-09-13T07:38:01Z","author":[{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"id":"25260","full_name":"Koppelmann, Bastian","last_name":"Koppelmann","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"}],"title":"Current and Future RISC-V Activities for Virtual Prototyping and Chip Design","conference":{"location":"Munich, DE"},"related_material":{"link":[{"relation":"confirmation","url":"https://www.edacentrum.de/compact/current-and-future-risc-v-activities-virtual-prototyping-and-chip-design"}]},"year":"2018","citation":{"ieee":"P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” <i>International Workshop on RISC-V Research Activities</i>, vol. Presentation, 2018.","chicago":"Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” <i>International Workshop on RISC-V Research Activities</i> Presentation (2018).","ama":"Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. <i>International Workshop on RISC-V Research Activities</i>. 2018;Presentation.","apa":"Adelt, P., Koppelmann, B., &#38; Müller, W. (2018). Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. <i>International Workshop on RISC-V Research Activities</i>, <i>Presentation</i>.","bibtex":"@article{Adelt_Koppelmann_Müller_2018, title={Current and Future RISC-V Activities for Virtual Prototyping and Chip Design}, volume={Presentation}, journal={International Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang}, year={2018} }","mla":"Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” <i>International Workshop on RISC-V Research Activities</i>, vol. Presentation, 2018.","short":"P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018)."},"_id":"24194","department":[{"_id":"58"}],"user_id":"15931","language":[{"iso":"eng"}],"publication":"International Workshop on RISC-V Research Activities","type":"journal_article","status":"public"},{"place":"Germany, Paderborn","year":"2017","citation":{"chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder, Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” In <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>. Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017. <a href=\"https://doi.org/10.17619/UNIPB/1-93\">https://doi.org/10.17619/UNIPB/1-93</a>.","ieee":"P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,” 2017, doi: <a href=\"https://doi.org/10.17619/UNIPB/1-93\">10.17619/UNIPB/1-93</a>.","ama":"Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. In: <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>. Verlagsschriftenreihe des Heinz Nixdorf Instituts; 2017. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-93\">10.17619/UNIPB/1-93</a>","apa":"Adelt, P., Koppelmann, B., Müller, W., Mueller-Gritschneder, D., Kleinjohann, B., &#38; Scheytt, C. (2017). Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>. <a href=\"https://doi.org/10.17619/UNIPB/1-93\">https://doi.org/10.17619/UNIPB/1-93</a>","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Mueller-Gritschneder_Kleinjohann_Scheytt_2017, place={Germany, Paderborn}, title={Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-93\">10.17619/UNIPB/1-93</a>}, booktitle={Tagungsband des Wissenschaftsforums Intelligente Technische Systeme}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Mueller-Gritschneder, Daniel and Kleinjohann, Bernd and Scheytt, Christoph}, year={2017} }","short":"P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.","mla":"Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” <i>Tagungsband des Wissenschaftsforums Intelligente Technische Systeme</i>, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-93\">10.17619/UNIPB/1-93</a>."},"publication_status":"published","publication_identifier":{"isbn":["978-3-942647-88-5"]},"related_material":{"link":[{"url":"https://digital.ub.uni-paderborn.de/hs/content/titleinfo/2436759","relation":"confirmation"}]},"title":"Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen","doi":"10.17619/UNIPB/1-93","date_updated":"2022-01-06T06:56:13Z","publisher":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","date_created":"2021-09-13T08:20:35Z","author":[{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"last_name":"Koppelmann","full_name":"Koppelmann, Bastian","id":"25260","first_name":"Bastian"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Daniel","last_name":"Mueller-Gritschneder","full_name":"Mueller-Gritschneder, Daniel"},{"first_name":"Bernd","full_name":"Kleinjohann, Bernd","last_name":"Kleinjohann"},{"first_name":"Christoph","last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph"}],"status":"public","type":"conference","publication":"Tagungsband des Wissenschaftsforums Intelligente Technische Systeme","language":[{"iso":"ger"}],"_id":"24220","user_id":"15931","department":[{"_id":"58"}]},{"language":[{"iso":"eng"}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24224","status":"public","type":"conference","publication":"Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation","conference":{"start_date":"2017.03.27","end_date":"2017.03.31"},"title":"ANALISA - A Tool for Static Instruction Set Analysis","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"first_name":"Bastian","full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"Kleinjohann","full_name":"Kleinjohann, Bernd","first_name":"Bernd"},{"last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144","first_name":"Christoph"}],"date_created":"2021-09-13T08:20:40Z","date_updated":"2022-01-06T06:56:13Z","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, C. (2017). ANALISA - A Tool for Static Instruction Set Analysis. <i>Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation</i>.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, place={Lausanne, CH}, title={ANALISA - A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}, year={2017} }","mla":"Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” <i>Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation</i>, 2017.","short":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, Lausanne, CH, 2017.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In <i>Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation</i>. Lausanne, CH, 2017.","ieee":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.","ama":"Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. ANALISA - A Tool for Static Instruction Set Analysis. In: <i>Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation</i>. ; 2017."},"place":"Lausanne, CH","year":"2017","related_material":{"link":[{"url":"https://www.date-conference.com/content/date-2017-call-papers","relation":"confirmation"}]}},{"related_material":{"link":[{"relation":"confirmation","url":"https://www.edacentrum.de/rees/program"}]},"year":"2017","place":"Lausanne, Switzerland","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, C. (2017). An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries. <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES) </i>, 44.","mla":"Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES) </i>, 2017, p. 44.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, place={Lausanne, Switzerland}, title={An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries}, booktitle={2nd Workshop on Resiliency in Embedded Electronic Systems (REES) }, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}, year={2017}, pages={44} }","short":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland, 2017, p. 44.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and Christoph Scheytt. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” In <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES) </i>, 44. Lausanne, Switzerland, 2017.","ieee":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries,” in <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES) </i>, 2017, p. 44.","ama":"Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries. In: <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES) </i>. ; 2017:44."},"page":"44","date_updated":"2022-01-06T06:56:13Z","date_created":"2021-09-13T08:20:41Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Kleinjohann, Bernd","last_name":"Kleinjohann","first_name":"Bernd"},{"first_name":"Christoph","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144"}],"title":"An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries","type":"conference","publication":"2nd Workshop on Resiliency in Embedded Electronic Systems (REES) ","status":"public","_id":"24225","user_id":"15931","department":[{"_id":"58"}],"language":[{"iso":"eng"}]},{"date_created":"2021-09-28T11:08:16Z","author":[{"first_name":"Peer","id":"5603","full_name":"Adelt, Peer","last_name":"Adelt"},{"last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian","first_name":"Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"last_name":"Kleinjohann","full_name":"Kleinjohann, Bernd","first_name":"Bernd"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","full_name":"Scheytt, J. Christoph","id":"37144","first_name":"J. Christoph"}],"date_updated":"2025-02-26T14:45:09Z","conference":{"location":"Lausanne, CH, Mrz. 2017"},"title":"ANALISA - A Tool for Static Instruction Set Analysis","corporate_editor":["University Booth Interactive Presentation"],"citation":{"bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, title={ANALISA - A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and Testing in Europe (DATE)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}, editor={University Booth Interactive Presentation}, year={2017} }","mla":"Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” <i>Design Automation and Testing in Europe (DATE)</i>, edited by University Booth Interactive Presentation, 2017.","short":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe (DATE), 2017.","apa":"Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, J. C. (2017). ANALISA - A Tool for Static Instruction Set Analysis. In University Booth Interactive Presentation (Ed.), <i>Design Automation and Testing in Europe (DATE)</i>.","ieee":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” in <i>Design Automation and Testing in Europe (DATE)</i>, Lausanne, CH, Mrz. 2017, 2017.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and J. Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In <i>Design Automation and Testing in Europe (DATE)</i>, edited by University Booth Interactive Presentation, 2017.","ama":"Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt JC. ANALISA - A Tool for Static Instruction Set Analysis. In: University Booth Interactive Presentation, ed. <i>Design Automation and Testing in Europe (DATE)</i>. ; 2017."},"year":"2017","department":[{"_id":"70"}],"user_id":"5603","_id":"25068","language":[{"iso":"eng"}],"publication":"Design Automation and Testing in Europe (DATE)","type":"conference","status":"public"},{"author":[{"first_name":"Peer","last_name":"Adelt","id":"5603","full_name":"Adelt, Peer"},{"id":"25260","full_name":"Koppelmann, Bastian","last_name":"Koppelmann","first_name":"Bastian"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Bernd","last_name":"Kleinjohann","full_name":"Kleinjohann, Bernd"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","full_name":"Scheytt, J. Christoph","id":"37144","first_name":"J. Christoph"}],"date_created":"2021-09-28T11:12:00Z","date_updated":"2025-02-26T14:45:23Z","conference":{"location":"Lausanne, CH, Mrz. 2017"},"title":"ANALISA - A Tool for Static Instruction Set Analysis","citation":{"apa":"Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., &#38; Scheytt, J. C. (2017). ANALISA - A Tool for Static Instruction Set Analysis. In University Booth Interactive Presentation (Ed.), <i>Design Automation and Testing in Europe (DATE)</i>.","short":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe (DATE), 2017.","mla":"Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” <i>Design Automation and Testing in Europe (DATE)</i>, edited by University Booth Interactive Presentation, 2017.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, title={ANALISA - A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and Testing in Europe (DATE)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}, editor={University Booth Interactive Presentation}, year={2017} }","ieee":"P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” in <i>Design Automation and Testing in Europe (DATE)</i>, Lausanne, CH, Mrz. 2017, 2017.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and J. Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In <i>Design Automation and Testing in Europe (DATE)</i>, edited by University Booth Interactive Presentation, 2017.","ama":"Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt JC. ANALISA - A Tool for Static Instruction Set Analysis. In: University Booth Interactive Presentation, ed. <i>Design Automation and Testing in Europe (DATE)</i>. ; 2017."},"corporate_editor":["University Booth Interactive Presentation"],"year":"2017","user_id":"5603","department":[{"_id":"672"}],"_id":"25069","language":[{"iso":"eng"}],"type":"conference","publication":"Design Automation and Testing in Europe (DATE)","status":"public"},{"related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/7753545"}]},"publication_identifier":{"eissn":["2324-8440"]},"citation":{"ama":"Adelt P, Koppelmann B, Müller W, Becker M, Kleinjohann B, Scheytt C. Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. In: <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. ; 2016. doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>","ieee":"P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi: <a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, and Christoph Scheytt. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” In <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. Tallin, Estonia, 2016. <a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">https://doi.org/10.1109/VLSI-SoC.2016.7753545</a>.","apa":"Adelt, P., Koppelmann, B., Müller, W., Becker, M., Kleinjohann, B., &#38; Scheytt, C. (2016). Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. <a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">https://doi.org/10.1109/VLSI-SoC.2016.7753545</a>","short":"P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), Tallin, Estonia, 2016.","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Becker_Kleinjohann_Scheytt_2016, place={Tallin, Estonia}, title={Fast Dynamic Fault Injection for Virtual Microcontroller Platforms}, DOI={<a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>}, booktitle={Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Becker, Markus and Kleinjohann, Bernd and Scheytt, Christoph}, year={2016} }","mla":"Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>, 2016, doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>."},"place":"Tallin, Estonia","year":"2016","date_created":"2021-09-13T09:44:30Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"},{"first_name":"Bastian","last_name":"Koppelmann","id":"25260","full_name":"Koppelmann, Bastian"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"},{"first_name":"Bernd","last_name":"Kleinjohann","full_name":"Kleinjohann, Bernd"},{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt"}],"date_updated":"2022-02-17T13:57:45Z","conference":{"start_date":"2016.09.26","end_date":"2016.09.28"},"doi":"10.1109/VLSI-SoC.2016.7753545","title":"Fast Dynamic Fault Injection for Virtual Microcontroller Platforms","type":"conference","publication":"Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)","status":"public","abstract":[{"lang":"eng","text":"Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach."}],"user_id":"15931","department":[{"_id":"58"}],"_id":"24264","language":[{"iso":"eng"}]},{"related_material":{"link":[{"relation":"confirmation","url":"https://scholar.google.de/scholar?q=10.1016/j.protcy.2016.08.031&hl=de&as_sdt=0&as_vis=1&oi=scholart"}]},"year":"2016","place":"Paderborn, DE","citation":{"apa":"Jatzkowski, J., Adelt, P., &#38; Rettberg, A. (2016). Hierarchical Scheduling for Plug-and-Produce. <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>, 227–234. <a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\">https://doi.org/ 10.1016/j.protcy.2016.08.031</a>","short":"J. Jatzkowski, P. Adelt, A. Rettberg, in: 3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering, Elsevier, Paderborn, DE, 2016, pp. 227–234.","mla":"Jatzkowski, Jan, et al. “Hierarchical Scheduling for Plug-and-Produce.” <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>, Elsevier, 2016, pp. 227–34, doi:<a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>.","bibtex":"@inproceedings{Jatzkowski_Adelt_Rettberg_2016, place={Paderborn, DE}, title={Hierarchical Scheduling for Plug-and-Produce}, DOI={<a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>}, booktitle={3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering}, publisher={Elsevier}, author={Jatzkowski, Jan and Adelt, Peer and Rettberg, Achim}, year={2016}, pages={227–234} }","chicago":"Jatzkowski, Jan, Peer Adelt, and Achim Rettberg. “Hierarchical Scheduling for Plug-and-Produce.” In <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>, 227–34. Paderborn, DE: Elsevier, 2016. <a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\">https://doi.org/ 10.1016/j.protcy.2016.08.031</a>.","ieee":"J. Jatzkowski, P. Adelt, and A. Rettberg, “Hierarchical Scheduling for Plug-and-Produce,” in <i>3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering</i>, 2016, pp. 227–234, doi: <a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>.","ama":"Jatzkowski J, Adelt P, Rettberg A. Hierarchical Scheduling for Plug-and-Produce. In: <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>. Elsevier; 2016:227-234. doi:<a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>"},"page":"227-234","publisher":"Elsevier","date_updated":"2022-02-17T14:06:38Z","date_created":"2021-09-13T09:44:37Z","author":[{"last_name":"Jatzkowski","full_name":"Jatzkowski, Jan","first_name":"Jan"},{"last_name":"Adelt","full_name":"Adelt, Peer","id":"5603","first_name":"Peer"},{"last_name":"Rettberg","full_name":"Rettberg, Achim","first_name":"Achim"}],"title":"Hierarchical Scheduling for Plug-and-Produce","doi":" 10.1016/j.protcy.2016.08.031","type":"conference","publication":"3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering","abstract":[{"lang":"eng","text":"Today's increasing number of sensors and computation nodes covered by cyber physical systems (CPS) results in rising complexity. For instance, computation results are based on measured data whose quality strongly depends on their age. CPS therefore have real-time requirements on computation results and communication to keep temporal dependency between measured inputs and computed outputs. In addition, today's CPS shall be modular to enable flexibility and scalability, e.g., postulated for production systems in context of Industry 4.0. Enabling CPS to easily integrate components by some Plug-and-Produce mechanism is desired.In this paper, we aim at enabling Plug-and-Produce in CPS using hypervisor-based virtualization. This implies hierarchical scheduling of dependent real-time systems. Here, dependencies are given by precedence constraints of tasks. Based on an approach for detection of new components added to a real-time network, in this paper we focus on integration of enabled applications into the current schedule of a computation node. Here, enabled application refers to an application software that just got executable by plugging some component to the CPS. Applications are encapsulated by virtual machines and provide a self-description including information about required and provided data as well as timing behavior. This self-description is used to adjust global scheduling and thus include new functionality to the CPS."}],"status":"public","_id":"24269","user_id":"15931","department":[{"_id":"58"}],"language":[{"iso":"eng"}]},{"date_created":"2021-09-14T07:06:30Z","author":[{"last_name":"Adelt","id":"5603","full_name":"Adelt, Peer","first_name":"Peer"}],"publisher":"Universität Paderborn, Fakultät EIM","date_updated":"2022-02-17T09:57:44Z","title":"Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur","citation":{"mla":"Adelt, Peer. <i>Analyse von Ausführungszeiten Durch Integration Einer Statischen WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur</i>. Universität Paderborn, Fakultät EIM, 2015.","bibtex":"@book{Adelt_2015, title={Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur}, publisher={Universität Paderborn, Fakultät EIM}, author={Adelt, Peer}, year={2015} }","short":"P. Adelt, Analyse von Ausführungszeiten Durch Integration Einer Statischen WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur, Universität Paderborn, Fakultät EIM, 2015.","apa":"Adelt, P. (2015). <i>Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur</i>. Universität Paderborn, Fakultät EIM.","ieee":"P. Adelt, <i>Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur</i>. Universität Paderborn, Fakultät EIM, 2015.","chicago":"Adelt, Peer. <i>Analyse von Ausführungszeiten Durch Integration Einer Statischen WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur</i>. Universität Paderborn, Fakultät EIM, 2015.","ama":"Adelt P. <i>Analyse von Ausführungszeiten Durch Integration Einer Statischen WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur</i>. Universität Paderborn, Fakultät EIM; 2015."},"year":"2015","user_id":"15931","department":[{"_id":"58"}],"_id":"24288","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public"}]