---
_id: '29302'
abstract:
- lang: eng
text: "This paper introduces the project Scale4Edge. The project is focused on enabling
an effective RISC-V ecosystem for optimization of edge applications. We describe
the basic components of this ecosystem and introduce the envisioned\r\ndemonstrators,
which will be used in their evaluation."
author:
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Reinhold
full_name: Heckmann, Reinhold
last_name: Heckmann
- first_name: Milos
full_name: Krstic, Milos
last_name: Krstic
- first_name: Vladimir
full_name: Herdt, Vladimir
last_name: Herdt
- first_name: Rolf
full_name: Drechsler, Rolf
last_name: Drechsler
- first_name: Gerhard
full_name: Angst, Gerhard
last_name: Angst
- first_name: Ralf
full_name: Wimmer, Ralf
last_name: Wimmer
- first_name: Andreas
full_name: Mauderer, Andreas
last_name: Mauderer
- first_name: Rafael
full_name: Stahl, Rafael
last_name: Stahl
- first_name: Karsten
full_name: Emrich, Karsten
last_name: Emrich
- first_name: Daniel
full_name: Mueller-Gritschneder, Daniel
last_name: Mueller-Gritschneder
- first_name: Bernd
full_name: Becker, Bernd
last_name: Becker
- first_name: Philipp
full_name: Scholl, Philipp
last_name: Scholl
- first_name: Eyck
full_name: Jentzsch, Eyck
last_name: Jentzsch
- first_name: Jan
full_name: Schlamelcher, Jan
last_name: Schlamelcher
- first_name: Kim
full_name: Grüttner, Kim
last_name: Grüttner
- first_name: Paul Palomero
full_name: Bernardo, Paul Palomero
last_name: Bernardo
- first_name: Oliver
full_name: Brinkmann, Oliver
last_name: Brinkmann
- first_name: Mihaela
full_name: Damian, Mihaela
last_name: Damian
- first_name: Julian
full_name: Oppermann, Julian
last_name: Oppermann
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Jörg
full_name: Bormann, Jörg
last_name: Bormann
- first_name: Johannes
full_name: Partzsch, Johannes
last_name: Partzsch
- first_name: Christian
full_name: Mayr, Christian
last_name: Mayr
- first_name: Wolfgang
full_name: Kunz, Wolfgang
last_name: Kunz
citation:
ama: 'Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: In
Proceedings of the Design Automation and Test Conference and Exhibition (DATE
2022). ; 2022.'
apa: Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler,
R., Angst, G., Wimmer, R., Mauderer, A., Stahl, R., Emrich, K., Mueller-Gritschneder,
D., Becker, B., Scholl, P., Jentzsch, E., Schlamelcher, J., Grüttner, K., Bernardo,
P. P., … Kunz, W. (2022). The Scale4Edge RISC-V Ecosystem. In Proceedings of
the Design Automation and Test Conference and Exhibition (DATE 2022).
bibtex: '@inproceedings{Ecker_Adelt_Müller_Heckmann_Krstic_Herdt_Drechsler_Angst_Wimmer_Mauderer_et
al._2022, title={The Scale4Edge RISC-V Ecosystem}, booktitle={In Proceedings of
the Design Automation and Test Conference and Exhibition (DATE 2022)}, author={Ecker,
Wolfgang and Adelt, Peer and Müller, Wolfgang and Heckmann, Reinhold and Krstic,
Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf
and Mauderer, Andreas and et al.}, year={2022} }'
chicago: Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos
Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.”
In In Proceedings of the Design Automation and Test Conference and Exhibition
(DATE 2022), 2022.
ieee: W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
mla: Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” In Proceedings
of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
short: 'W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler,
G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder,
B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo,
O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr,
W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition
(DATE 2022), 2022.'
conference:
end_date: 15.03.2022
start_date: 14.03.2022
date_created: 2022-01-13T07:27:46Z
date_updated: 2022-01-13T07:30:38Z
department:
- _id: '58'
language:
- iso: eng
publication: In Proceedings of the Design Automation and Test Conference and Exhibition
(DATE 2022)
status: public
title: The Scale4Edge RISC-V Ecosystem
type: conference
user_id: '15931'
year: '2022'
...
---
_id: '32125'
abstract:
- lang: eng
text: 'Fault coverage analysis and fault simulation are well-established methods
for the qualification of test vectors in hardware design. However, their role
in virtual prototyping and the correlation to later steps in the design process
need further investigation. We introduce a metric for RISC-V instruction and register
coverage for binary software. The metric measures if RISC-V instruction types
are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied
by the means of a virtual prototype which is based on an abstract instruction
and register model with direct correspondence to their bit level representation.
In this context, we analyzed three different openly available test suites: the
RISC-V architectural testing framework, the RISC-V unit tests, and programs which
are automatically generated by the RISC-V Torture test generator. We discuss their
tradeoffs and show that by combining them to a unified test suite we can arrive
at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage.'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage
Analysis for Different RISC-V ISA Modules. In: MBMV 2021 - Methods and Description
Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.
VDE; 2021.'
apa: Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2021). Register and
Instruction Coverage Analysis for Different RISC-V ISA Modules. MBMV 2021 -
Methods and Description Languages for Modelling and Verification of Circuits and
Systems; GMM/ITG/GI-Workshop.
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE},
title={Register and Instruction Coverage Analysis for Different RISC-V ISA Modules},
booktitle={MBMV 2021 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt,
Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021}
}'
chicago: 'Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
“Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.”
In MBMV 2021 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.'
ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction
Coverage Analysis for Different RISC-V ISA Modules,” 2021.
mla: Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different
RISC-V ISA Modules.” MBMV 2021 - Methods and Description Languages for Modelling
and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods
and Description Languages for Modelling and Verification of Circuits and Systems;
GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.'
conference:
end_date: 2021-03-19
start_date: 2021-03-18
date_created: 2022-06-23T11:52:50Z
date_updated: 2022-06-23T11:54:16Z
department:
- _id: '58'
language:
- iso: eng
place: Munich, DE
publication: MBMV 2021 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop
publication_identifier:
isbn:
- 978-3-8007-5500-4
publication_status: published
publisher: VDE
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/9399723
status: public
title: Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
type: conference
user_id: '5603'
year: '2021'
...
---
_id: '32132'
abstract:
- lang: ger
text: "Die Werkzeugdemonstration des QEMU Timing Analyzers (QTA) stellt eine Erweiterung
des quelloffenen CPU Emulators QEMU zur Simulation von Softwareprogrammen und
deren Worst-Case Zeitverhaltens vor, das durch eine statische Zeitanalyse vorher
aus dem Softwareprogramm extrahiert wurde. Der Ablauf der Analyse gliedert sich
in mehrere Schritte: Zunächst wird für das zu simulierende Binärprogramm eine
WCET-Analyse mit aiT durchgeführt. Im Preprocessing des aiT-Reports wird daraufhin
ein WCET-annotierter Kontrollflussgraph erzeugt. Dabei entsprechen die Knoten
im Kontrollflussgraph den aiT-Blöcken und die Kanten dem jeweiligen Worst-Case-Zeitverbrauch,
um das Programm im aktuellen Ausführungskontext vom Quell- bis zum Zielblock laufen
zu lassen. Nach dem Preprocessing werden Binärprogramm und der zuvor erzeugte,
zeitannotierte Kontrollflussgraph von QEMU geladen und gemeinsam simuliert.\r\n\r\nDie
Implementierung des QTA basiert auf der Standard TGI Plugin API (Tiny Code Generator
Plugin API), die seit Ende 2019 mit QEMU V4.2 verfügbar ist. Dieses API erlaubt
die Entwicklung von versionsunabhängigen QEMU-Erweiterungen. Die QEMU-QTA-Erweiterung
wird zum Zeitpunkt der Werkzeugdemonstration inklusive des ait2qta-Preprozessors
unter github.com im Quellcode frei verfügbar sein.\r\n\r\nDie Demonstration geht
von einer existierenden aiT-Analyse eines für TriCore© kompilierten binären Softwareprograms
aus, erläutert das Kontrollflusszwischenformat und zeigt die zeitannotierte Simulation
der Software."
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausführungszeiten.
In: MBMV 2021 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.'
apa: Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2021). QEMU zur Simulation
von Worst-Case-Ausführungszeiten. MBMV 2021 - Methods and Description Languages
for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, place={Munich, DE},
title={QEMU zur Simulation von Worst-Case-Ausführungszeiten}, booktitle={MBMV
2021 - Methods and Description Languages for Modelling and Verification of Circuits
and Systems; GMM/ITG/GI-Workshop}, publisher={VDE}, author={Adelt, Peer and Koppelmann,
Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2021} }'
chicago: 'Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
“QEMU zur Simulation von Worst-Case-Ausführungszeiten.” In MBMV 2021 - Methods
and Description Languages for Modelling and Verification of Circuits and Systems;
GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.'
ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von
Worst-Case-Ausführungszeiten,” 2021.
mla: Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.”
MBMV 2021 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods
and Description Languages for Modelling and Verification of Circuits and Systems;
GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.'
conference:
end_date: 2021-03-19
start_date: 2021-03-18
date_created: 2022-06-23T12:07:10Z
date_updated: 2022-12-06T13:24:44Z
department:
- _id: '58'
keyword:
- QEMU
- aiT
- Zeitannotation
- WCET
language:
- iso: ger
place: Munich, DE
publication: MBMV 2021 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop
publication_status: published
publisher: VDE
status: public
title: QEMU zur Simulation von Worst-Case-Ausführungszeiten
type: conference
user_id: '5603'
year: '2021'
...
---
_id: '23992'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage
Analysis for Different RISC-V ISA Modules. In: Workshop Methoden Und Beschreibungssprachen
Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021).
; 2021.'
apa: Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2021). Register and
Instruction Coverage Analysis for Different RISC-V ISA Modules. Workshop Methoden
Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und
Systemen (MBMV 2021).
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2021, title={Register and
Instruction Coverage Analysis for Different RISC-V ISA Modules}, booktitle={Workshop
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen
und Systemen (MBMV 2021)}, author={Adelt, Peer and Koppelmann, Bastian and Müller,
Wolfgang and Scheytt, Christoph}, year={2021} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
“Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.”
In Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
von Schaltungen Und Systemen (MBMV 2021), 2021.
ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction
Coverage Analysis for Different RISC-V ISA Modules,” 2021.
mla: Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different
RISC-V ISA Modules.” Workshop Methoden Und Beschreibungssprachen Zur Modellierung
Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und
Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen
(MBMV 2021), 2021.'
date_created: 2021-09-09T08:30:03Z
date_updated: 2023-01-31T13:25:48Z
department:
- _id: '58'
language:
- iso: eng
publication: Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2021)
status: public
title: Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
type: conference
user_id: '15931'
year: '2021'
...
---
_id: '24027'
abstract:
- lang: eng
text: Fault effect simulation is a well-established technique for the qualification
of robust embedded software and hardware as required by different safety standards.
Our article introduces a Virtual Prototype based approach for the fault analysis
and fast simulation of a set of automatically generated and target compiled software
programs. The approach scales to different RISC-V ISA standard subset configurations
and is based on an instruction and hardware register coverage for automatic fault
injections of permanent and transient bitflips. The analysis of each software
binary evaluates its opcode type and register access coverage including the addressed
memory space. Based on this information dedicated sets of fault injected hardware
models, i.e., mutants, are generated. The simulation of all mutants conducted
with the different binaries finally identifies the cases with a normal termination
though executed on a faulty hardware model. They are identified as a subject for
further investigations and improvements by the implementation of additional hardware
or software safety countermeasures. Our final evaluation results with automatic
C code generation, compilation, analysis, and simulation show that QEMU provides
an adequate efficient platform, which also scales to more complex scenarios.
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based
Fault Effect Analysis for RISC-V Hardware Architectures. In: MBMV 2020 - Methods
and Description Languages for Modelling and Verification of Circuits and Systems;
GMM/ITG/GI-Workshop. ; 2020.'
apa: Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2020). A Scalable
Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.
MBMV 2020 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop.
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2020, place={Stuttgart,
DE}, title={A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V
Hardware Architectures}, booktitle={MBMV 2020 - Methods and Description Languages
for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop},
author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt,
Christoph}, year={2020} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
“A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware
Architectures.” In MBMV 2020 - Methods and Description Languages for Modelling
and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Stuttgart,
DE, 2020.
ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for
QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
mla: Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis
for RISC-V Hardware Architectures.” MBMV 2020 - Methods and Description Languages
for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop,
2020.
short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods
and Description Languages for Modelling and Verification of Circuits and Systems;
GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.'
date_created: 2021-09-09T11:50:19Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '58'
language:
- iso: eng
place: Stuttgart, DE
publication: MBMV 2020 - Methods and Description Languages for Modelling and Verification
of Circuits and Systems; GMM/ITG/GI-Workshop
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/9094540
status: public
title: A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware
Architectures
type: conference
user_id: '15931'
year: '2020'
...
---
_id: '24058'
abstract:
- lang: eng
text: Embedded systems require a high energy efficiency in combination with an optimized
performance. As such, Bit Manipulation Instructions (BMIs) were introduced for
x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled
software for various applications. Though the RISC-V platform is meanwhile widely
accepted for embedded systems application, its instruction set architecture (ISA)
currently still supports only two basic BMIs.We introduce ten advanced BMIs for
the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized
for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions
are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket
CPU hardware extensions show that RISC-V BMI extensions have no negative impact
on the critical path of the execution pipeline. Our software evaluations show
that we can, for example, expect a significant impact for time and power consuming
cryptographic applications.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation
Instructions. In: 29th International Symposium on Power and Timing Modeling,
Optimization and Simulation (PATMOS). ; 2019. doi:10.1109/PATMOS.2019.8862170'
apa: Koppelmann, B., Adelt, P., Müller, W., & Scheytt, C. (2019). RISC-V Extensions
for Bit Manipulation Instructions. 29th International Symposium on Power and
Timing Modeling, Optimization and Simulation (PATMOS). https://doi.org/10.1109/PATMOS.2019.8862170
bibtex: '@inproceedings{Koppelmann_Adelt_Müller_Scheytt_2019, place={Rhodos, Griechenland},
title={RISC-V Extensions for Bit Manipulation Instructions}, DOI={10.1109/PATMOS.2019.8862170},
booktitle={29th International Symposium on Power and Timing Modeling, Optimization
and Simulation (PATMOS)}, author={Koppelmann, Bastian and Adelt, Peer and Müller,
Wolfgang and Scheytt, Christoph}, year={2019} }'
chicago: Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt.
“RISC-V Extensions for Bit Manipulation Instructions.” In 29th International
Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).
Rhodos, Griechenland, 2019. https://doi.org/10.1109/PATMOS.2019.8862170.
ieee: 'B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for
Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.'
mla: Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.”
29th International Symposium on Power and Timing Modeling, Optimization and
Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
short: 'B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium
on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland,
2019.'
conference:
end_date: 2019.07.03
start_date: 2019.07.01
date_created: 2021-09-09T12:26:14Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '58'
doi: 10.1109/PATMOS.2019.8862170
language:
- iso: eng
place: Rhodos, Griechenland
publication: 29th International Symposium on Power and Timing Modeling, Optimization
and Simulation (PATMOS)
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/8862170
status: public
title: RISC-V Extensions for Bit Manipulation Instructions
type: conference
user_id: '15931'
year: '2019'
...
---
_id: '24060'
abstract:
- lang: ger
text: 'In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen
Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software
für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer
Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU
um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an
die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode
anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller
UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt,
dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt
und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. '
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer
Software für RISC-V Prozessoren. In: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen
Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019).
; 2019.'
apa: Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2019). Analyse sicherheitskritischer
Software für RISC-V Prozessoren. MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen
Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019).
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_2019, place={Kaiserslautern,
DE}, title={Analyse sicherheitskritischer Software für RISC-V Prozessoren}, booktitle={MBMV
2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV 2019)}, author={Adelt, Peer and Koppelmann,
Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
“Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” In MBMV 2019-22.Workshop
Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
Und Systemen (MBMV 2019). Kaiserslautern, DE, 2019.
ieee: P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer
Software für RISC-V Prozessoren,” 2019.
mla: Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.”
MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und
Verifikation von Schaltungen Und Systemen (MBMV 2019), 2019.
short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop
Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.'
conference:
end_date: 2019.04.08
start_date: 2019.04.08
date_created: 2021-09-09T12:26:16Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '58'
language:
- iso: eng
place: Kaiserslautern, DE
publication: MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung
und Verifikation von Schaltungen und Systemen (MBMV 2019)
publication_identifier:
isbn:
- 978-3-8007-4945-4
related_material:
link:
- relation: confirmation
url: https://www.vde-verlag.de/proceedings-de/454945007.html
status: public
title: Analyse sicherheitskritischer Software für RISC-V Prozessoren
type: conference
user_id: '15931'
year: '2019'
...
---
_id: '24061'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Benedikt
full_name: Driessen, Benedikt
last_name: Driessen
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory
Analysis of Security Sensitive Software. In: 2nd International Workshop on
Embedded Software for Industrial IoT in Conjunction with DATE 2019. ; 2019:32-34.'
apa: Adelt, P., Koppelmann, B., Müller, W., Scheytt, C., & Driessen, B. (2019).
QEMU for Dynamic Memory Analysis of Security Sensitive Software. 2nd International
Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019,
32–34.
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Scheytt_Driessen_2019, place={Florence,
Italy}, title={QEMU for Dynamic Memory Analysis of Security Sensitive Software},
booktitle={ 2nd International Workshop on Embedded Software for Industrial IoT
in conjunction with DATE 2019}, author={Adelt, Peer and Koppelmann, Bastian and
Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}, year={2019},
pages={32–34} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and
Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.”
In 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction
with DATE 2019, 32–34. Florence, Italy, 2019.
ieee: P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for
Dynamic Memory Analysis of Security Sensitive Software,” in 2nd International
Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019,
2019, pp. 32–34.
mla: Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive
Software.” 2nd International Workshop on Embedded Software for Industrial
IoT in Conjunction with DATE 2019, 2019, pp. 32–34.
short: 'P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International
Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019,
Florence, Italy, 2019, pp. 32–34.'
date_created: 2021-09-09T12:26:18Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '58'
language:
- iso: eng
page: 32-34
place: Florence, Italy
publication: ' 2nd International Workshop on Embedded Software for Industrial IoT
in conjunction with DATE 2019'
related_material:
link:
- relation: confirmation
url: https://www.researchgate.net/publication/334258953_QEMU_for_Dynamic_Memory_Analysis_of_Security_Sensitive_Software
status: public
title: QEMU for Dynamic Memory Analysis of Security Sensitive Software
type: conference
user_id: '15931'
year: '2019'
...
---
_id: '24063'
abstract:
- lang: eng
text: It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software
emulation in user and full system mode. We will first give an overview of the
current state of the QEMU RISC-V implementation. Thereafter, we will present the
DecodeTree tool, which will be available with the next QEMU release. DecodeTree
is a code generator included in QEMU that can generate the program logic for extracting
and decoding opcodes and operands from a formal instruction list of the target
architecture. This enables the structured implementation of just-in-time compilations
to guarantee that the QEMU implementation meets the ISA specification. As such,
we completely replaced the existing RISC-V RV32GC and RV64GC implementations by
DecodeTree generations in the next official QEMU release, which is expected in
spring 2019. We will demonstrate the DecodeTree applications by the example of
RISC-V ISA subset configurations.
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current
State and Future Releases. 2nd International Workshop on RISC-V Research Activities.
2019;(Presentation).'
apa: 'Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2019). QEMU Support
for RISC-V: Current State and Future Releases. 2nd International Workshop on
RISC-V Research Activities, (Presentation).'
bibtex: '@article{Adelt_Koppelmann_Müller_Scheytt_2019, title={QEMU Support for
RISC-V: Current State and Future Releases}, volume={(Presentation)}, journal={2nd
International Workshop on RISC-V Research Activities}, author={Adelt, Peer and
Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}, year={2019}
}'
chicago: 'Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt.
“QEMU Support for RISC-V: Current State and Future Releases.” 2nd International
Workshop on RISC-V Research Activities (Presentation) (2019).'
ieee: 'P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V:
Current State and Future Releases,” 2nd International Workshop on RISC-V Research
Activities, vol. (Presentation), 2019.'
mla: 'Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.”
2nd International Workshop on RISC-V Research Activities, vol. (Presentation),
2019.'
short: P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop
on RISC-V Research Activities (Presentation) (2019).
date_created: 2021-09-09T12:26:20Z
date_updated: 2022-01-06T06:56:06Z
department:
- _id: '58'
language:
- iso: eng
publication: 2nd International Workshop on RISC-V Research Activities
related_material:
link:
- relation: confirmation
url: https://www.edacentrum.de/veranstaltungen/risc-v/2019/programm
status: public
title: 'QEMU Support for RISC-V: Current State and Future Releases'
type: journal_article
user_id: '15931'
volume: (Presentation)
year: '2019'
...
---
_id: '24194'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual
Prototyping and Chip Design. International Workshop on RISC-V Research Activities.
2018;Presentation.
apa: Adelt, P., Koppelmann, B., & Müller, W. (2018). Current and Future RISC-V
Activities for Virtual Prototyping and Chip Design. International Workshop
on RISC-V Research Activities, Presentation.
bibtex: '@article{Adelt_Koppelmann_Müller_2018, title={Current and Future RISC-V
Activities for Virtual Prototyping and Chip Design}, volume={Presentation}, journal={International
Workshop on RISC-V Research Activities}, author={Adelt, Peer and Koppelmann, Bastian
and Müller, Wolfgang}, year={2018} }'
chicago: Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future
RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop
on RISC-V Research Activities Presentation (2018).
ieee: P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities
for Virtual Prototyping and Chip Design,” International Workshop on RISC-V
Research Activities, vol. Presentation, 2018.
mla: Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping
and Chip Design.” International Workshop on RISC-V Research Activities,
vol. Presentation, 2018.
short: P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research
Activities Presentation (2018).
conference:
location: Munich, DE
date_created: 2021-09-13T07:38:01Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '58'
language:
- iso: eng
publication: International Workshop on RISC-V Research Activities
related_material:
link:
- relation: confirmation
url: https://www.edacentrum.de/compact/current-and-future-risc-v-activities-virtual-prototyping-and-chip-design
status: public
title: Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
type: journal_article
user_id: '15931'
volume: Presentation
year: '2018'
...
---
_id: '24220'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Daniel
full_name: Mueller-Gritschneder, Daniel
last_name: Mueller-Gritschneder
- first_name: Bernd
full_name: Kleinjohann, Bernd
last_name: Kleinjohann
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt
C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen
auf der Basis virtueller Plattformen. In: Tagungsband des Wissenschaftsforums
Intelligente Technische Systeme. Verlagsschriftenreihe des Heinz Nixdorf Instituts;
2017. doi:10.17619/UNIPB/1-93'
apa: Adelt, P., Koppelmann, B., Müller, W., Mueller-Gritschneder, D., Kleinjohann,
B., & Scheytt, C. (2017). Automatisierte Fehlerinjektion zur Entwicklung sicherer
Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. Tagungsband
des Wissenschaftsforums Intelligente Technische Systeme. https://doi.org/10.17619/UNIPB/1-93
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Mueller-Gritschneder_Kleinjohann_Scheytt_2017,
place={Germany, Paderborn}, title={Automatisierte Fehlerinjektion zur Entwicklung
sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen}, DOI={10.17619/UNIPB/1-93}, booktitle={Tagungsband
des Wissenschaftsforums Intelligente Technische Systeme}, publisher={Verlagsschriftenreihe
des Heinz Nixdorf Instituts}, author={Adelt, Peer and Koppelmann, Bastian and
Müller, Wolfgang and Mueller-Gritschneder, Daniel and Kleinjohann, Bernd and Scheytt,
Christoph}, year={2017} }'
chicago: 'Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder,
Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur
Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.”
In Tagungsband des Wissenschaftsforums Intelligente Technische Systeme.
Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017. https://doi.org/10.17619/UNIPB/1-93.'
ieee: 'P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann,
and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen
auf der Basis virtueller Plattformen,” 2017, doi: 10.17619/UNIPB/1-93.'
mla: Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer
Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” Tagungsband
des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe
des Heinz Nixdorf Instituts, 2017, doi:10.17619/UNIPB/1-93.
short: 'P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann,
C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme,
Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.'
date_created: 2021-09-13T08:20:35Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
doi: 10.17619/UNIPB/1-93
language:
- iso: ger
place: Germany, Paderborn
publication: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme
publication_identifier:
isbn:
- 978-3-942647-88-5
publication_status: published
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts
related_material:
link:
- relation: confirmation
url: https://digital.ub.uni-paderborn.de/hs/content/titleinfo/2436759
status: public
title: Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen
auf der Basis virtueller Plattformen
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '24224'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Bernd
full_name: Kleinjohann, Bernd
last_name: Kleinjohann
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. ANALISA - A Tool
for Static Instruction Set Analysis. In: Design Automation and Testing in Europe
(DATE), University Booth Interactive Presentation. ; 2017.'
apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., & Scheytt, C. (2017).
ANALISA - A Tool for Static Instruction Set Analysis. Design Automation and
Testing in Europe (DATE), University Booth Interactive Presentation.
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, place={Lausanne,
CH}, title={ANALISA - A Tool for Static Instruction Set Analysis}, booktitle={Design
Automation and Testing in Europe (DATE), University Booth Interactive Presentation},
author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann,
Bernd and Scheytt, Christoph}, year={2017} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In
Design Automation and Testing in Europe (DATE), University Booth Interactive
Presentation. Lausanne, CH, 2017.
ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA
- A Tool for Static Instruction Set Analysis,” 2017.
mla: Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.”
Design Automation and Testing in Europe (DATE), University Booth Interactive
Presentation, 2017.
short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design
Automation and Testing in Europe (DATE), University Booth Interactive Presentation,
Lausanne, CH, 2017.'
conference:
end_date: 2017.03.31
start_date: 2017.03.27
date_created: 2021-09-13T08:20:40Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
language:
- iso: eng
place: Lausanne, CH
publication: Design Automation and Testing in Europe (DATE), University Booth Interactive
Presentation
related_material:
link:
- relation: confirmation
url: https://www.date-conference.com/content/date-2017-call-papers
status: public
title: ANALISA - A Tool for Static Instruction Set Analysis
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '24225'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Bernd
full_name: Kleinjohann, Bernd
last_name: Kleinjohann
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. An Automatic Injection
Framework for Safety Assessements of Embedded Software Binaries. In: 2nd Workshop
on Resiliency in Embedded Electronic Systems (REES) . ; 2017:44.'
apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., & Scheytt, C. (2017).
An Automatic Injection Framework for Safety Assessements of Embedded Software
Binaries. 2nd Workshop on Resiliency in Embedded Electronic Systems (REES)
, 44.
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, place={Lausanne,
Switzerland}, title={An Automatic Injection Framework for Safety Assessements
of Embedded Software Binaries}, booktitle={2nd Workshop on Resiliency in Embedded
Electronic Systems (REES) }, author={Adelt, Peer and Koppelmann, Bastian and Müller,
Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}, year={2017}, pages={44}
}'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
Christoph Scheytt. “An Automatic Injection Framework for Safety Assessements of
Embedded Software Binaries.” In 2nd Workshop on Resiliency in Embedded Electronic
Systems (REES) , 44. Lausanne, Switzerland, 2017.
ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic
Injection Framework for Safety Assessements of Embedded Software Binaries,” in
2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017,
p. 44.
mla: Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements
of Embedded Software Binaries.” 2nd Workshop on Resiliency in Embedded Electronic
Systems (REES) , 2017, p. 44.
short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd
Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland,
2017, p. 44.'
date_created: 2021-09-13T08:20:41Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
language:
- iso: eng
page: '44'
place: Lausanne, Switzerland
publication: '2nd Workshop on Resiliency in Embedded Electronic Systems (REES) '
related_material:
link:
- relation: confirmation
url: https://www.edacentrum.de/rees/program
status: public
title: An Automatic Injection Framework for Safety Assessements of Embedded Software
Binaries
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '25068'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Bernd
full_name: Kleinjohann, Bernd
last_name: Kleinjohann
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt JC. ANALISA - A Tool
for Static Instruction Set Analysis. In: University Booth Interactive Presentation,
ed. Design Automation and Testing in Europe (DATE). ; 2017.'
apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., & Scheytt, J. C.
(2017). ANALISA - A Tool for Static Instruction Set Analysis. In University Booth
Interactive Presentation (Ed.), Design Automation and Testing in Europe (DATE).
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, title={ANALISA
- A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and
Testing in Europe (DATE)}, author={Adelt, Peer and Koppelmann, Bastian and Müller,
Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}, editor={University
Booth Interactive Presentation}, year={2017} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
J. Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.”
In Design Automation and Testing in Europe (DATE), edited by University
Booth Interactive Presentation, 2017.
ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA
- A Tool for Static Instruction Set Analysis,” in Design Automation and Testing
in Europe (DATE), Lausanne, CH, Mrz. 2017, 2017.
mla: Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.”
Design Automation and Testing in Europe (DATE), edited by University Booth
Interactive Presentation, 2017.
short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University
Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe
(DATE), 2017.'
conference:
location: Lausanne, CH, Mrz. 2017
corporate_editor:
- University Booth Interactive Presentation
date_created: 2021-09-28T11:08:16Z
date_updated: 2025-02-26T14:45:09Z
department:
- _id: '70'
language:
- iso: eng
publication: Design Automation and Testing in Europe (DATE)
status: public
title: ANALISA - A Tool for Static Instruction Set Analysis
type: conference
user_id: '5603'
year: '2017'
...
---
_id: '25069'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Bernd
full_name: Kleinjohann, Bernd
last_name: Kleinjohann
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt JC. ANALISA - A Tool
for Static Instruction Set Analysis. In: University Booth Interactive Presentation,
ed. Design Automation and Testing in Europe (DATE). ; 2017.'
apa: Adelt, P., Koppelmann, B., Müller, W., Kleinjohann, B., & Scheytt, J. C.
(2017). ANALISA - A Tool for Static Instruction Set Analysis. In University Booth
Interactive Presentation (Ed.), Design Automation and Testing in Europe (DATE).
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Kleinjohann_Scheytt_2017, title={ANALISA
- A Tool for Static Instruction Set Analysis}, booktitle={Design Automation and
Testing in Europe (DATE)}, author={Adelt, Peer and Koppelmann, Bastian and Müller,
Wolfgang and Kleinjohann, Bernd and Scheytt, J. Christoph}, editor={University
Booth Interactive Presentation}, year={2017} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and
J. Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.”
In Design Automation and Testing in Europe (DATE), edited by University
Booth Interactive Presentation, 2017.
ieee: P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA
- A Tool for Static Instruction Set Analysis,” in Design Automation and Testing
in Europe (DATE), Lausanne, CH, Mrz. 2017, 2017.
mla: Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.”
Design Automation and Testing in Europe (DATE), edited by University Booth
Interactive Presentation, 2017.
short: 'P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University
Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe
(DATE), 2017.'
conference:
location: Lausanne, CH, Mrz. 2017
corporate_editor:
- University Booth Interactive Presentation
date_created: 2021-09-28T11:12:00Z
date_updated: 2025-02-26T14:45:23Z
department:
- _id: '672'
language:
- iso: eng
publication: Design Automation and Testing in Europe (DATE)
status: public
title: ANALISA - A Tool for Static Instruction Set Analysis
type: conference
user_id: '5603'
year: '2017'
...
---
_id: '24264'
abstract:
- lang: eng
text: Electronic systems, like they are embedded in road vehicles, have to be compliant
to functional safety standards like ISO 26262 [1], which limit the impacts of
malfunctions for safety critical systems. ISO 26262, for instance, defines different
safety levels for road vehicles, which require different means and measures for
a safety compliant system and its development process like risk analysis and fault
effect simulation. For fault effect simulation it is important to investigate
the impact of physical and hardware related effects to the correct function of
a system. This article first studies code and model mutations for fault injection
in the context of fault effect simulation through different system abstraction
levels. It demonstrates how high level mutations correlate to bit flips of software
binaries by examples from the TriCore™ instruction set and finally presents a
virtual platform based implementation for automated injection of bit flip based
mutations into software binaries. Experimental results demonstrate the efficiency
of the implemented approach.
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Bernd
full_name: Kleinjohann, Bernd
last_name: Kleinjohann
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Adelt P, Koppelmann B, Müller W, Becker M, Kleinjohann B, Scheytt C. Fast
Dynamic Fault Injection for Virtual Microcontroller Platforms. In: Proceedings
of the IEEE/IFIP International Conference on VLSI (VLSI-SOC). ; 2016. doi:10.1109/VLSI-SoC.2016.7753545'
apa: Adelt, P., Koppelmann, B., Müller, W., Becker, M., Kleinjohann, B., & Scheytt,
C. (2016). Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.
Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC).
https://doi.org/10.1109/VLSI-SoC.2016.7753545
bibtex: '@inproceedings{Adelt_Koppelmann_Müller_Becker_Kleinjohann_Scheytt_2016,
place={Tallin, Estonia}, title={Fast Dynamic Fault Injection for Virtual Microcontroller
Platforms}, DOI={10.1109/VLSI-SoC.2016.7753545},
booktitle={Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)},
author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Becker, Markus
and Kleinjohann, Bernd and Scheytt, Christoph}, year={2016} }'
chicago: Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd
Kleinjohann, and Christoph Scheytt. “Fast Dynamic Fault Injection for Virtual
Microcontroller Platforms.” In Proceedings of the IEEE/IFIP International Conference
on VLSI (VLSI-SOC). Tallin, Estonia, 2016. https://doi.org/10.1109/VLSI-SoC.2016.7753545.
ieee: 'P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt,
“Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi:
10.1109/VLSI-SoC.2016.7753545.'
mla: Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller
Platforms.” Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC),
2016, doi:10.1109/VLSI-SoC.2016.7753545.
short: 'P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt,
in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC),
Tallin, Estonia, 2016.'
conference:
end_date: 2016.09.28
start_date: 2016.09.26
date_created: 2021-09-13T09:44:30Z
date_updated: 2022-02-17T13:57:45Z
department:
- _id: '58'
doi: 10.1109/VLSI-SoC.2016.7753545
language:
- iso: eng
place: Tallin, Estonia
publication: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)
publication_identifier:
eissn:
- 2324-8440
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/7753545
status: public
title: Fast Dynamic Fault Injection for Virtual Microcontroller Platforms
type: conference
user_id: '15931'
year: '2016'
...
---
_id: '24269'
abstract:
- lang: eng
text: Today's increasing number of sensors and computation nodes covered by cyber
physical systems (CPS) results in rising complexity. For instance, computation
results are based on measured data whose quality strongly depends on their age.
CPS therefore have real-time requirements on computation results and communication
to keep temporal dependency between measured inputs and computed outputs. In addition,
today's CPS shall be modular to enable flexibility and scalability, e.g., postulated
for production systems in context of Industry 4.0. Enabling CPS to easily integrate
components by some Plug-and-Produce mechanism is desired.In this paper, we aim
at enabling Plug-and-Produce in CPS using hypervisor-based virtualization. This
implies hierarchical scheduling of dependent real-time systems. Here, dependencies
are given by precedence constraints of tasks. Based on an approach for detection
of new components added to a real-time network, in this paper we focus on integration
of enabled applications into the current schedule of a computation node. Here,
enabled application refers to an application software that just got executable
by plugging some component to the CPS. Applications are encapsulated by virtual
machines and provide a self-description including information about required and
provided data as well as timing behavior. This self-description is used to adjust
global scheduling and thus include new functionality to the CPS.
author:
- first_name: Jan
full_name: Jatzkowski, Jan
last_name: Jatzkowski
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
- first_name: Achim
full_name: Rettberg, Achim
last_name: Rettberg
citation:
ama: 'Jatzkowski J, Adelt P, Rettberg A. Hierarchical Scheduling for Plug-and-Produce.
In: 3rd International Conference on System-Integrated Intelligence: New Challenges
for Product and Production Engineering. Elsevier; 2016:227-234. doi: 10.1016/j.protcy.2016.08.031'
apa: 'Jatzkowski, J., Adelt, P., & Rettberg, A. (2016). Hierarchical Scheduling
for Plug-and-Produce. 3rd International Conference on System-Integrated Intelligence:
New Challenges for Product and Production Engineering, 227–234. https://doi.org/ 10.1016/j.protcy.2016.08.031'
bibtex: '@inproceedings{Jatzkowski_Adelt_Rettberg_2016, place={Paderborn, DE}, title={Hierarchical
Scheduling for Plug-and-Produce}, DOI={
10.1016/j.protcy.2016.08.031}, booktitle={3rd International Conference on
System-integrated Intelligence: New Challenges for Product and Production Engineering},
publisher={Elsevier}, author={Jatzkowski, Jan and Adelt, Peer and Rettberg, Achim},
year={2016}, pages={227–234} }'
chicago: 'Jatzkowski, Jan, Peer Adelt, and Achim Rettberg. “Hierarchical Scheduling
for Plug-and-Produce.” In 3rd International Conference on System-Integrated
Intelligence: New Challenges for Product and Production Engineering, 227–34.
Paderborn, DE: Elsevier, 2016. https://doi.org/
10.1016/j.protcy.2016.08.031.'
ieee: 'J. Jatzkowski, P. Adelt, and A. Rettberg, “Hierarchical Scheduling for Plug-and-Produce,”
in 3rd International Conference on System-integrated Intelligence: New Challenges
for Product and Production Engineering, 2016, pp. 227–234, doi: 10.1016/j.protcy.2016.08.031.'
mla: 'Jatzkowski, Jan, et al. “Hierarchical Scheduling for Plug-and-Produce.” 3rd
International Conference on System-Integrated Intelligence: New Challenges for
Product and Production Engineering, Elsevier, 2016, pp. 227–34, doi: 10.1016/j.protcy.2016.08.031.'
short: 'J. Jatzkowski, P. Adelt, A. Rettberg, in: 3rd International Conference on
System-Integrated Intelligence: New Challenges for Product and Production Engineering,
Elsevier, Paderborn, DE, 2016, pp. 227–234.'
date_created: 2021-09-13T09:44:37Z
date_updated: 2022-02-17T14:06:38Z
department:
- _id: '58'
doi: ' 10.1016/j.protcy.2016.08.031'
language:
- iso: eng
page: 227-234
place: Paderborn, DE
publication: '3rd International Conference on System-integrated Intelligence: New
Challenges for Product and Production Engineering'
publisher: Elsevier
related_material:
link:
- relation: confirmation
url: https://scholar.google.de/scholar?q=10.1016/j.protcy.2016.08.031&hl=de&as_sdt=0&as_vis=1&oi=scholart
status: public
title: Hierarchical Scheduling for Plug-and-Produce
type: conference
user_id: '15931'
year: '2016'
...
---
_id: '24288'
author:
- first_name: Peer
full_name: Adelt, Peer
id: '5603'
last_name: Adelt
citation:
ama: Adelt P. Analyse von Ausführungszeiten Durch Integration Einer Statischen
WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur.
Universität Paderborn, Fakultät EIM; 2015.
apa: Adelt, P. (2015). Analyse von Ausführungszeiten durch Integration einer
statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel
der TriCore-Architektur. Universität Paderborn, Fakultät EIM.
bibtex: '@book{Adelt_2015, title={Analyse von Ausführungszeiten durch Integration
einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel
der TriCore-Architektur}, publisher={Universität Paderborn, Fakultät EIM}, author={Adelt,
Peer}, year={2015} }'
chicago: Adelt, Peer. Analyse von Ausführungszeiten Durch Integration Einer Statischen
WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur.
Universität Paderborn, Fakultät EIM, 2015.
ieee: P. Adelt, Analyse von Ausführungszeiten durch Integration einer statischen
WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur.
Universität Paderborn, Fakultät EIM, 2015.
mla: Adelt, Peer. Analyse von Ausführungszeiten Durch Integration Einer Statischen
WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur.
Universität Paderborn, Fakultät EIM, 2015.
short: P. Adelt, Analyse von Ausführungszeiten Durch Integration Einer Statischen
WCET-Analyse Mit Einer Dynamischen Befehlssatzsimulation Am Beispiel Der TriCore-Architektur,
Universität Paderborn, Fakultät EIM, 2015.
date_created: 2021-09-14T07:06:30Z
date_updated: 2022-02-17T09:57:44Z
department:
- _id: '58'
language:
- iso: eng
publisher: Universität Paderborn, Fakultät EIM
status: public
title: Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse
mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur
type: mastersthesis
user_id: '15931'
year: '2015'
...