---
_id: '59232'
abstract:
- lang: eng
text: Heterogeneous computing devices comprising multiple processing systems combined
with a programmable logic like an FPGA have become increasingly popular. Developing
and runtime managing these heterogeneous platform devices, however, still poses
multiple challenges. The programming paradigms for hardware and software applications
fundamentally differ, while the runtime management requires additional attention.
The first steps towards unifying design flows have been taken by creating high-level
synthesis tools. However, these toolsfocus on the design process and lack runtime
management features. FPGA operating systems aim to close this gap by providing
runtime management features and build tools. ReconOS, as an example of an FPGA
operating system, allows bridging the hardware-software gap by integrating hardware-located
computation units as threads into a host operating system, allowing for familiar
inter-thread programming paradigms to be extended to FPGAs. This thesis presents
ReconOS64, a successor and fork of ReconOS, aiming at modern 64-bit platform systems-on-chip.
Besides establishing support for this platform and incorporating new system generation
processes, ReconOS64 provides additional features for both development and runtime
management. By providing a flexible grouping mechanism for hardware-located threads,
partial reconfiguration for exchanging individual threads at runtime is simplified.
Further runtime flexibility was achieved by implementing a multi-clock architecture,
allowing individual groups of threads to be executed at different frequencies,
which can be adapted during runtime with a low reconfiguration overhead. In addition,
this thesis provides an overview of further development approaches on various
systems based on ReconOS64 and ReconOS.
- lang: ger
text: Heterogene Architekturen, welche aus mehreren Recheneinheiten im Verbund mit
einer programmierbaren Logik bestehen, gewinnen zunehmend an Verbreitung. Die
Entwicklungsprozesse sowie die Steuerung solcher heterogenen Umgebungen stellen
jedoch nach wie vor eine Herausforderung dar. Die Programmiertechniken für Hardware-
und Software-Anwendungen unterscheiden sich bereits grundlegend; zudem benötigt
die Steuerung zusätzliche Aufmerksamkeit. Die Verwendung von Hochsprachen-Synthesewerkzeugen
(High-Level Synthesis) für das Hardwaredesign stellen einen ersten Schritt hin
zu einem einheitlichen Entwurfsprozess dar. Allerdings beschränkt sich deren Einsatz
auf den Designprozess, während das Management zur Laufzeit keine Berücksichtigung
findet.FPGA-Betriebssysteme versuchen diese Lücke durch die Bereitstellung von
Management- und Entwurfswerkzeugen zu schließen. Ein Beispiel für ein solches
System ist ReconOS, welches die Hardware-Software-Interaktion durch Anbindung
von hardwareseitigen Recheneinheiten als Threads in einem Host-Betriebssystem
ermöglicht. Dadurch werden die aus der Softwareentwicklung bekannten Methoden
zur Kommunikation zwischen mehreren Threads auf FPGA-Systeme ausgeweitet.Diese
Arbeit stellt ReconOS64 vor, welches als Ableger von ReconOS auf aktuellen 64-bit
Systemen verwendet werden kann. Neben der Unterstützung aktueller Plattformen
sowie der Einrichtung eines neuen Designprozesses werden durch ReconOS64 zusätzliche
Möglichkeiten sowohl zur Entwicklung wie auch zum Laufzeitmanagement geschaffen.
Durch flexible Gruppierungen von Hardware-basierten Threads wird die Verwendung
partieller Rekonfiguration zum Austausch einzelner Threads zur Laufzeit vereinfacht.
Zudem erhöht die Entwicklung einer Multi-Taktsignal-Architektur die Flexibilität
zur Laufzeit, da hierdurch einzelne Gruppen von Threads mit unterschiedlichen
Taktsignalen versorgt werden können, welche zudem zurLaufzeit mit geringer Unterbrechungszeit
verändert werden können.Zusätzlich werden im Rahmen dieser Arbeit weitere Entwicklungsprojekte
auf verschiedenen Systemen für ReconOS64 und ReconOS vorgestellt.
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: Clausing L. ReconOS64 - Hardware-Software Multithreading for Heterogeneous
Platform FPGAs.; 2025. doi:10.17619/UNIPB/1-2216
apa: Clausing, L. (2025). ReconOS64 - Hardware-Software Multithreading for Heterogeneous
Platform FPGAs. https://doi.org/10.17619/UNIPB/1-2216
bibtex: '@book{Clausing_2025, place={Paderborn}, title={ReconOS64 - Hardware-Software
Multithreading for Heterogeneous Platform FPGAs}, DOI={10.17619/UNIPB/1-2216},
author={Clausing, Lennart}, year={2025} }'
chicago: Clausing, Lennart. ReconOS64 - Hardware-Software Multithreading for
Heterogeneous Platform FPGAs. Paderborn, 2025. https://doi.org/10.17619/UNIPB/1-2216.
ieee: L. Clausing, ReconOS64 - Hardware-Software Multithreading for Heterogeneous
Platform FPGAs. Paderborn, 2025.
mla: Clausing, Lennart. ReconOS64 - Hardware-Software Multithreading for Heterogeneous
Platform FPGAs. 2025, doi:10.17619/UNIPB/1-2216.
short: L. Clausing, ReconOS64 - Hardware-Software Multithreading for Heterogeneous
Platform FPGAs, Paderborn, 2025.
date_created: 2025-04-01T17:00:31Z
date_updated: 2025-04-01T17:24:18Z
doi: 10.17619/UNIPB/1-2216
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.org/urn:nbn:de:hbz:466:2-54271
oa: '1'
place: Paderborn
publication_status: published
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: ReconOS64 - Hardware-Software Multithreading for Heterogeneous Platform FPGAs
type: dissertation
user_id: '74287'
year: '2025'
...
---
_id: '45913'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Zakarya
full_name: Guetattfi, Zakarya
last_name: Guetattfi
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Clausing L, Guetattfi Z, Kaufmann P, Lienen C, Platzner M. On Guaranteeing
Schedulability of Periodic Real-time Hardware Tasks under ReconOS64. In: Proceedings
of the 19th International Symposium on Applied Reconfigurable Computing (ARC).
; 2023. doi:https://doi.org/10.1007/978-3-031-42921-7_17'
apa: Clausing, L., Guetattfi, Z., Kaufmann, P., Lienen, C., & Platzner, M. (2023).
On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64.
Proceedings of the 19th International Symposium on Applied Reconfigurable Computing
(ARC). https://doi.org/10.1007/978-3-031-42921-7_17
bibtex: '@inproceedings{Clausing_Guetattfi_Kaufmann_Lienen_Platzner_2023, title={On
Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64},
DOI={https://doi.org/10.1007/978-3-031-42921-7_17},
booktitle={Proceedings of the 19th International Symposium on Applied Reconfigurable
Computing (ARC)}, author={Clausing, Lennart and Guetattfi, Zakarya and Kaufmann,
Paul and Lienen, Christian and Platzner, Marco}, year={2023} }'
chicago: Clausing, Lennart, Zakarya Guetattfi, Paul Kaufmann, Christian Lienen,
and Marco Platzner. “On Guaranteeing Schedulability of Periodic Real-Time Hardware
Tasks under ReconOS64.” In Proceedings of the 19th International Symposium
on Applied Reconfigurable Computing (ARC), 2023. https://doi.org/10.1007/978-3-031-42921-7_17.
ieee: 'L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing
Schedulability of Periodic Real-time Hardware Tasks under ReconOS64,” 2023, doi:
https://doi.org/10.1007/978-3-031-42921-7_17.'
mla: Clausing, Lennart, et al. “On Guaranteeing Schedulability of Periodic Real-Time
Hardware Tasks under ReconOS64.” Proceedings of the 19th International Symposium
on Applied Reconfigurable Computing (ARC), 2023, doi:https://doi.org/10.1007/978-3-031-42921-7_17.
short: 'L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, M. Platzner, in: Proceedings
of the 19th International Symposium on Applied Reconfigurable Computing (ARC),
2023.'
date_created: 2023-07-09T12:50:32Z
date_updated: 2024-04-30T09:11:26Z
department:
- _id: '78'
doi: https://doi.org/10.1007/978-3-031-42921-7_17
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication: Proceedings of the 19th International Symposium on Applied Reconfigurable
Computing (ARC)
status: public
title: On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64
type: conference
user_id: '398'
year: '2023'
...
---
_id: '45899'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Clausing L, Jentzsch F, Ghasemzadeh Mohammadi H, Platzner M.
Flexible Industrial Analytics on Reconfigurable Systems-On-Chip. In: Haake C-J,
Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly
Computing -- Individualized IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe
des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:225-236.
doi:10.5281/zenodo.8068713'
apa: Boschmann, A., Clausing, L., Jentzsch, F., Ghasemzadeh Mohammadi, H., &
Platzner, M. (2023). Flexible Industrial Analytics on Reconfigurable Systems-On-Chip.
In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, & H. Wehrheim
(Eds.), On-The-Fly Computing -- Individualized IT-services in dynamic markets
(Vol. 412, pp. 225–236). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.5281/zenodo.8068713
bibtex: '@inbook{Boschmann_Clausing_Jentzsch_Ghasemzadeh Mohammadi_Platzner_2023,
place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts},
title={Flexible Industrial Analytics on Reconfigurable Systems-On-Chip}, volume={412},
DOI={10.5281/zenodo.8068713},
booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets},
publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Boschmann,
Alexander and Clausing, Lennart and Jentzsch, Felix and Ghasemzadeh Mohammadi,
Hassan and Platzner, Marco}, editor={Haake, Claus-Jochen and Meyer auf der Heide,
Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023},
pages={225–236}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts}
}'
chicago: 'Boschmann, Alexander, Lennart Clausing, Felix Jentzsch, Hassan Ghasemzadeh
Mohammadi, and Marco Platzner. “Flexible Industrial Analytics on Reconfigurable
Systems-On-Chip.” In On-The-Fly Computing -- Individualized IT-Services in
Dynamic Markets, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide,
Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:225–36. Verlagsschriftenreihe
Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn,
2023. https://doi.org/10.5281/zenodo.8068713.'
ieee: 'A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, and M.
Platzner, “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip,” in
On-The-Fly Computing -- Individualized IT-services in dynamic markets,
vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and
H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023,
pp. 225–236.'
mla: Boschmann, Alexander, et al. “Flexible Industrial Analytics on Reconfigurable
Systems-On-Chip.” On-The-Fly Computing -- Individualized IT-Services in Dynamic
Markets, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut,
Universität Paderborn, 2023, pp. 225–36, doi:10.5281/zenodo.8068713.
short: 'A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, M. Platzner,
in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim
(Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets,
Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 225–236.'
date_created: 2023-07-07T08:36:58Z
date_updated: 2024-05-02T10:33:26Z
ddc:
- '004'
department:
- _id: '7'
- _id: '78'
doi: 10.5281/zenodo.8068713
editor:
- first_name: Claus-Jochen
full_name: Haake, Claus-Jochen
last_name: Haake
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
last_name: Meyer auf der Heide
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
- first_name: Henning
full_name: Wachsmuth, Henning
last_name: Wachsmuth
- first_name: Heike
full_name: Wehrheim, Heike
last_name: Wehrheim
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2023-07-07T08:36:40Z
date_updated: 2023-07-07T11:14:23Z
file_id: '45900'
file_name: T1-Chapter-SFB-Buch-Final.pdf
file_size: 468973
relation: main_file
file_date_updated: 2023-07-07T11:14:23Z
has_accepted_license: '1'
intvolume: ' 412'
language:
- iso: eng
oa: '1'
page: 225-236
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
publication: On-The-Fly Computing -- Individualized IT-services in dynamic markets
publisher: Heinz Nixdorf Institut, Universität Paderborn
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts
status: public
title: Flexible Industrial Analytics on Reconfigurable Systems-On-Chip
type: book_chapter
user_id: '398'
volume: 412
year: '2023'
...
---
_id: '32855'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Clausing L, Platzner M. ReconOS64: A Hardware Operating System for Modern
Platform FPGAs with 64-Bit Support. In: 2022 IEEE International Parallel and
Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2022:120-127. doi:10.1109/ipdpsw55747.2022.00029'
apa: 'Clausing, L., & Platzner, M. (2022). ReconOS64: A Hardware Operating System
for Modern Platform FPGAs with 64-Bit Support. 2022 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), 120–127. https://doi.org/10.1109/ipdpsw55747.2022.00029'
bibtex: '@inproceedings{Clausing_Platzner_2022, title={ReconOS64: A Hardware Operating
System for Modern Platform FPGAs with 64-Bit Support}, DOI={10.1109/ipdpsw55747.2022.00029},
booktitle={2022 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)}, publisher={IEEE}, author={Clausing, Lennart and Platzner,
Marco}, year={2022}, pages={120–127} }'
chicago: 'Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating
System for Modern Platform FPGAs with 64-Bit Support.” In 2022 IEEE International
Parallel and Distributed Processing Symposium Workshops (IPDPSW), 120–27.
IEEE, 2022. https://doi.org/10.1109/ipdpsw55747.2022.00029.'
ieee: 'L. Clausing and M. Platzner, “ReconOS64: A Hardware Operating System for
Modern Platform FPGAs with 64-Bit Support,” in 2022 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), Lyon, France, 2022,
pp. 120–127, doi: 10.1109/ipdpsw55747.2022.00029.'
mla: 'Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating System
for Modern Platform FPGAs with 64-Bit Support.” 2022 IEEE International Parallel
and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–27,
doi:10.1109/ipdpsw55747.2022.00029.'
short: 'L. Clausing, M. Platzner, in: 2022 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–127.'
conference:
end_date: 2022-06-03
location: ' Lyon, France'
name: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops
(IPDPSW)
start_date: 2022-05-30
date_created: 2022-08-16T09:58:34Z
date_updated: 2022-11-18T09:36:00Z
department:
- _id: '78'
doi: 10.1109/ipdpsw55747.2022.00029
language:
- iso: eng
page: 120-127
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
publication: 2022 IEEE International Parallel and Distributed Processing Symposium
Workshops (IPDPSW)
publication_identifier:
eisbn:
- 978-1-6654-9747-3
publication_status: published
publisher: IEEE
status: public
title: 'ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit
Support'
type: conference
user_id: '477'
year: '2022'
...
---
_id: '30909'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: 'Clausing L. ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. In: Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
ACM; 2021. doi:10.1145/3468044.3468056'
apa: 'Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip. Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
https://doi.org/10.1145/3468044.3468056'
bibtex: '@inproceedings{Clausing_2021, title={ReconOS64: High-Performance Embedded
Computing for Industrial Analytics on a Reconfigurable System-on-Chip}, DOI={10.1145/3468044.3468056}, booktitle={Proceedings
of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies}, publisher={ACM}, author={Clausing, Lennart}, year={2021} }'
chicago: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for
Industrial Analytics on a Reconfigurable System-on-Chip.” In Proceedings of
the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies. ACM, 2021. https://doi.org/10.1145/3468044.3468056.'
ieee: 'L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.'
mla: 'Clausing, Lennart. “ReconOS64: High-Performance Embedded Computing for Industrial
Analytics on a Reconfigurable System-on-Chip.” Proceedings of the 11th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies,
ACM, 2021, doi:10.1145/3468044.3468056.'
short: 'L. Clausing, in: Proceedings of the 11th International Symposium on Highly
Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.'
date_created: 2022-04-18T10:17:47Z
date_updated: 2023-07-09T13:09:11Z
department:
- _id: '78'
doi: 10.1145/3468044.3468056
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication: Proceedings of the 11th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies
publication_status: published
publisher: ACM
status: public
title: 'ReconOS64: High-Performance Embedded Computing for Industrial Analytics on
a Reconfigurable System-on-Chip'
type: conference
user_id: '398'
year: '2021'
...
---
_id: '10782'
author:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
citation:
ama: Clausing L. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum; 2018.
apa: Clausing, L. (2018). Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum.
bibtex: '@book{Clausing_2018, title={Development of a Hardware / Software Codesign
for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum},
author={Clausing, Lennart}, year={2018} }'
chicago: Clausing, Lennart. Development of a Hardware / Software Codesign for
Sonification of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
ieee: L. Clausing, Development of a Hardware / Software Codesign for sonification
of LIDAR-based sensor data. Ruhr-University Bochum, 2018.
mla: Clausing, Lennart. Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data. Ruhr-University Bochum, 2018.
short: L. Clausing, Development of a Hardware / Software Codesign for Sonification
of LIDAR-Based Sensor Data, Ruhr-University Bochum, 2018.
date_created: 2019-07-10T12:13:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: Ruhr-University Bochum
status: public
title: Development of a Hardware / Software Codesign for sonification of LIDAR-based
sensor data
type: mastersthesis
user_id: '3118'
year: '2018'
...