[{"status":"public","type":"conference","publication":"International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"52743","citation":{"mla":"Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” <i>International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024</i>, p. 1.","bibtex":"@inproceedings{Hellebrand_Sadeghi-Kohan_Wunderlich, title={Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}, booktitle={International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}, pages={1} }","short":"S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.","apa":"Hellebrand, S., Sadeghi-Kohan, S., &#38; Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. <i>International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024</i>, 1.","chicago":"Hellebrand, Sybille, Somayeh Sadeghi-Kohan, and Hans-Joachim Wunderlich. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” In <i>International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024</i>, 1, n.d.","ieee":"S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle,” in <i>International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024</i>, Xi’an, China, p. 1.","ama":"Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: <i>International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024</i>. ; :1."},"page":"1","year":"2024","publication_status":"accepted","conference":{"name":"International Symposium of EDA (ISEDA)","start_date":"2024-05-10","end_date":"2024-05-13","location":"Xi'an, China"},"title":"Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle","date_created":"2024-03-22T16:57:53Z","author":[{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_updated":"2024-03-22T17:06:02Z"},{"status":"public","type":"misc","language":[{"iso":"eng"}],"_id":"50284","user_id":"209","department":[{"_id":"48"}],"year":"2024","place":"Darmstadt, Germany","citation":{"short":"A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.","mla":"Stiballe, Alisa, et al. <i>Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression</i>. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024.","bibtex":"@book{Stiballe_Reimer_Sadeghi-Kohan_Hellebrand_2024, place={Darmstadt, Germany}, title={Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}, publisher={37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024}, author={Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2024} }","apa":"Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., &#38; Hellebrand, S. (2024). <i>Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression</i>. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024.","ama":"Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. <i>Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression</i>. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024; 2024.","chicago":"Stiballe, Alisa, Jan Dennis Reimer, Somayeh Sadeghi-Kohan, and Sybille Hellebrand. <i>Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression</i>. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024.","ieee":"A. Stiballe, J. D. Reimer, S. Sadeghi-Kohan, and S. Hellebrand, <i>Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression</i>. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024."},"publication_status":"published","title":"Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression","publisher":"37. ITG / GMM / GI -Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\"  (TuZ'24), Feb. 2024","date_updated":"2024-03-22T17:12:39Z","date_created":"2024-01-08T08:47:32Z","author":[{"last_name":"Stiballe","full_name":"Stiballe, Alisa","first_name":"Alisa"},{"first_name":"Jan Dennis","last_name":"Reimer","id":"36703","full_name":"Reimer, Jan Dennis"},{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}]},{"status":"public","type":"misc","language":[{"iso":"eng"}],"user_id":"209","_id":"51799","citation":{"mla":"Ustimova, Magdalina, et al. <i>Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks</i>. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024.","short":"M. Ustimova, S. Sadeghi-Kohan, S. Hellebrand, Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.","bibtex":"@book{Ustimova_Sadeghi-Kohan_Hellebrand_2024, place={Darmstadt, Germany}, title={Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks}, publisher={37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024}, author={Ustimova, Magdalina  and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2024} }","apa":"Ustimova, M., Sadeghi-Kohan, S., &#38; Hellebrand, S. (2024). <i>Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks</i>. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024.","ama":"Ustimova M, Sadeghi-Kohan S, Hellebrand S. <i>Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks</i>. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024; 2024.","ieee":"M. Ustimova, S. Sadeghi-Kohan, and S. Hellebrand, <i>Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks</i>. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024.","chicago":"Ustimova, Magdalina , Somayeh Sadeghi-Kohan, and Sybille Hellebrand. <i>Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks</i>. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024."},"place":"Darmstadt, Germany","year":"2024","publication_status":"published","title":"Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks","date_created":"2024-02-23T12:07:20Z","author":[{"first_name":"Magdalina ","last_name":"Ustimova","full_name":"Ustimova, Magdalina "},{"full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"}],"date_updated":"2024-03-22T17:12:00Z","publisher":"37. ITG / GMM / GI -Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\"  (TuZ'24), Feb. 2024"},{"year":"2023","place":"Beijing, China","citation":{"ieee":"S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023.","chicago":"Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.” In <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>. Beijing, China, 2023.","ama":"Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>. ; 2023.","apa":"Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>. IEEE Asian Test Symposium (ATS’23).","short":"S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.","mla":"Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” <i>IEEE Asian Test Symposium (ATS’23), October 2023</i>, 2023.","bibtex":"@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing, China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication}, booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }"},"date_updated":"2024-01-08T08:49:08Z","date_created":"2023-08-26T08:47:52Z","author":[{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer","first_name":"Jan Dennis"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"title":"Optimizing the Streaming of Sensor Data with Approximate Communication","conference":{"name":"IEEE Asian Test Symposium (ATS'23)","start_date":"2023-10-14","end_date":"2023-10-17"},"type":"conference","publication":"IEEE Asian Test Symposium (ATS'23), October 2023","status":"public","_id":"46738","user_id":"36703","department":[{"_id":"48"}],"language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"article_type":"original","department":[{"_id":"48"}],"user_id":"209","_id":"46264","status":"public","abstract":[{"lang":"eng","text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. "}],"publication":"IEEE Design &Test","type":"journal_article","doi":"10.1109/mdat.2023.3298849","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}],"title":"Workload-Aware Periodic Interconnect BIST","date_created":"2023-08-02T11:07:43Z","author":[{"last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"date_updated":"2024-03-22T17:15:10Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","page":"1-1","citation":{"apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>}, journal={IEEE Design &#38;Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &#38;Test (2023) 1–1.","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” <i>IEEE Design &#38;Test</i>, pp. 1–1, 2023, doi: <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, 2023, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>. Published online 2023:1-1. doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>"},"year":"2023","publication_identifier":{"issn":["2168-2356","2168-2364"]},"publication_status":"published"},{"year":"2023","place":"Erfurt, Germany","page":"2","citation":{"ama":"Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.","ieee":"A. Ghazal, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, <i>On Cryptography Effects on Interconnect Reliability</i>. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","chicago":"Ghazal, Abdulkarim, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. <i>On Cryptography Effects on Interconnect Reliability</i>. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","bibtex":"@book{Ghazal_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Erfurt, Germany}, title={On Cryptography Effects on Interconnect Reliability}, publisher={35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023}, author={Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2023} }","short":"A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.","mla":"Ghazal, Abdulkarim, et al. <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","apa":"Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2023). <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023."},"date_updated":"2023-04-06T21:06:37Z","publisher":"35. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'23), Feb. 2023","date_created":"2023-01-04T10:20:41Z","author":[{"first_name":"Abdulkarim","last_name":"Ghazal","full_name":"Ghazal, Abdulkarim"},{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"last_name":"Reimer","id":"36703","full_name":"Reimer, Jan Dennis","first_name":"Jan Dennis"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"title":"On Cryptography Effects on Interconnect Reliability","type":"misc","status":"public","_id":"35204","department":[{"_id":"48"}],"user_id":"36703","keyword":["WORKSHOP"],"language":[{"iso":"eng"}]},{"place":"Venice, Italy","year":"2023","citation":{"ieee":"A. Badran, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Approximate Computing: Balancing Performance, Power, Reliability, and Safety,” 2023.","chicago":"Badran, Abdalrhman , Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Approximate Computing: Balancing Performance, Power, Reliability, and Safety.” In <i>28th IEEE European Test Symposium (ETS’23), May 2023</i>. Venice, Italy, 2023.","ama":"Badran A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Approximate Computing: Balancing Performance, Power, Reliability, and Safety. In: <i>28th IEEE European Test Symposium (ETS’23), May 2023</i>. ; 2023.","apa":"Badran, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2023). Approximate Computing: Balancing Performance, Power, Reliability, and Safety. <i>28th IEEE European Test Symposium (ETS’23), May 2023</i>.","mla":"Badran, Abdalrhman, et al. “Approximate Computing: Balancing Performance, Power, Reliability, and Safety.” <i>28th IEEE European Test Symposium (ETS’23), May 2023</i>, 2023.","bibtex":"@inproceedings{Badran_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Venice, Italy}, title={Approximate Computing: Balancing Performance, Power, Reliability, and Safety}, booktitle={28th IEEE European Test Symposium (ETS’23), May 2023}, author={Badran, Abdalrhman  and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2023} }","short":"A. Badran, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: 28th IEEE European Test Symposium (ETS’23), May 2023, Venice, Italy, 2023."},"title":"Approximate Computing: Balancing Performance, Power, Reliability, and Safety","conference":{"end_date":"2023-05-26","start_date":"2023-05-22"},"date_updated":"2023-06-19T14:21:47Z","date_created":"2023-02-07T13:57:34Z","author":[{"first_name":"Abdalrhman ","last_name":"Badran","full_name":"Badran, Abdalrhman "},{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan"},{"last_name":"Reimer","full_name":"Reimer, Jan Dennis","id":"36703","first_name":"Jan Dennis"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"status":"public","type":"conference","publication":"28th IEEE European Test Symposium (ETS'23), May 2023","language":[{"iso":"eng"}],"_id":"41875","user_id":"36703"},{"doi":"10.1109/dsn-w58399.2023.00056","title":"Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication","author":[{"first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2023-08-26T10:48:31Z","date_updated":"2023-08-26T10:49:07Z","publisher":"IEEE","citation":{"ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” In <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>.","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.","mla":"Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>}, booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }"},"year":"2023","publication_status":"published","language":[{"iso":"eng"}],"user_id":"78614","department":[{"_id":"48"}],"_id":"46739","status":"public","type":"conference","publication":"2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)"},{"keyword":["Electrical and Electronic Engineering"],"article_type":"original","language":[{"iso":"eng"}],"_id":"29351","department":[{"_id":"48"}],"user_id":"209","abstract":[{"text":"Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.","lang":"eng"}],"status":"public","publication":"Journal of Electronic Testing","type":"journal_article","title":"Stress-Aware Periodic Test of Interconnects","doi":"10.1007/s10836-021-05979-5","publisher":"Springer Science and Business Media LLC","date_updated":"2022-05-11T16:10:01Z","author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2022-01-14T11:16:34Z","year":"2022","citation":{"ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic Test of Interconnects,” <i>Journal of Electronic Testing</i>, 2022, doi: <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Stress-Aware Periodic Test of Interconnects.” <i>Journal of Electronic Testing</i>, 2022. <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">https://doi.org/10.1007/s10836-021-05979-5</a>.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. <i>Journal of Electronic Testing</i>. Published online 2022. doi:<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware Periodic Test of Interconnects}, DOI={<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>}, journal={Journal of Electronic Testing}, publisher={Springer Science and Business Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.” <i>Journal of Electronic Testing</i>, Springer Science and Business Media LLC, 2022, doi:<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. <i>Journal of Electronic Testing</i>. <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">https://doi.org/10.1007/s10836-021-05979-5</a>"},"publication_identifier":{"issn":["0923-8174","1573-0727"]},"publication_status":"published"},{"title":"EM-Aware Interconnect BIST","date_updated":"2022-05-11T17:07:24Z","publisher":"European Workshop on Silicon Lifecycle Management, March 18, 2022","date_created":"2022-02-19T14:21:24Z","author":[{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"place":"Online","year":"2022","page":"2","citation":{"ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, <i>EM-Aware Interconnect BIST</i>. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. <i>EM-Aware Interconnect BIST</i>. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.","mla":"Sadeghi-Kohan, Somayeh, et al. <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, place={Online}, title={EM-Aware Interconnect BIST}, publisher={European Workshop on Silicon Lifecycle Management, March 18, 2022}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2022). <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022."},"publication_status":"published","keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"_id":"29890","department":[{"_id":"48"}],"user_id":"209","status":"public","type":"misc"},{"type":"conference","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","status":"public","user_id":"209","department":[{"_id":"48"}],"_id":"19422","language":[{"iso":"eng"}],"publication_status":"published","citation":{"ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. ; 2020.","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.","bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>, 2020.","apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>."},"place":"Virtual Conference - Originally Frascati (Rome), Italy","year":"2020","author":[{"full_name":"Sprenger, Alexander","id":"22707","last_name":"Sprenger","first_name":"Alexander"},{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"date_created":"2020-09-15T14:03:02Z","date_updated":"2022-02-19T14:16:58Z","conference":{"start_date":"2020-10-19","end_date":"2020-10-21"},"title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study"},{"keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"_id":"15419","user_id":"209","department":[{"_id":"48"}],"status":"public","type":"misc","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","date_updated":"2022-04-04T12:30:02Z","publisher":"32. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'20), 16. - 18. Februar 2020","date_created":"2019-12-29T16:13:58Z","author":[{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"year":"2020","place":"Ludwigsburg","citation":{"ama":"Sadeghi-Kohan S, Hellebrand S. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.","ieee":"S. Sadeghi-Kohan and S. Hellebrand, <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_2020, place={Ludwigsburg}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, publisher={32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","short":"S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.","mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020."},"page":"4","publication_status":"published"},{"date_updated":"2022-05-11T17:06:38Z","publisher":"IEEE","author":[{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","first_name":"Somayeh"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"}],"date_created":"2022-01-10T08:38:34Z","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","doi":"10.1109/vts48691.2020.9107591","publication_status":"published","place":"Virtual Conference - Originally San Diego, CA, USA","year":"2020","citation":{"apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. <i>38th IEEE VLSI Test Symposium (VTS)</i>. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>","short":"S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.","mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” <i>38th IEEE VLSI Test Symposium (VTS)</i>, IEEE, 2020, doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference - Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, DOI={<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>}, booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","ama":"Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: <i>38th IEEE VLSI Test Symposium (VTS)</i>. IEEE; 2020. doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>","ieee":"S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,” 2020, doi: <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” In <i>38th IEEE VLSI Test Symposium (VTS)</i>. Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>."},"_id":"29200","user_id":"209","department":[{"_id":"48"}],"language":[{"iso":"eng"}],"type":"conference","publication":"38th IEEE VLSI Test Symposium (VTS)","status":"public"},{"year":"2018","citation":{"apa":"Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &#38; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. <a href=\"https://doi.org/10.1145/3194554.3194599\">https://doi.org/10.1145/3194554.3194599</a>","mla":"Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>.","short":"R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.","bibtex":"@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}, DOI={<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>}, booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM}, author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}, year={2018} }","chicago":"Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” In <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. ACM, 2018. <a href=\"https://doi.org/10.1145/3194554.3194599\">https://doi.org/10.1145/3194554.3194599</a>.","ieee":"R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: <a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>.","ama":"Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. ACM; 2018. doi:<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>"},"publication_status":"published","title":"Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture","doi":"10.1145/3194554.3194599","publisher":"ACM","date_updated":"2022-01-19T13:44:17Z","author":[{"full_name":"Rezaeizadeh Rookerd, Ramin","last_name":"Rezaeizadeh Rookerd","first_name":"Ramin"},{"last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"last_name":"Navabi","full_name":"Navabi, Zainalabedin","first_name":"Zainalabedin"}],"date_created":"2022-01-19T13:42:27Z","abstract":[{"lang":"eng","text":"STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible."}],"status":"public","publication":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","type":"conference","language":[{"iso":"eng"}],"_id":"29460","department":[{"_id":"48"}],"user_id":"78614"},{"author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan"},{"first_name":"Arash","full_name":"Vafaei, Arash","last_name":"Vafaei"},{"first_name":"Zainalabedin","full_name":"Navabi, Zainalabedin","last_name":"Navabi"}],"date_created":"2022-01-19T13:35:37Z","publisher":"IEEE","date_updated":"2023-08-02T11:36:15Z","doi":"10.1109/iolts.2018.8474120","title":"Near-Optimal Node Selection Procedure for Aging Monitor Placement","publication_status":"published","citation":{"chicago":"Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” In <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/iolts.2018.8474120\">https://doi.org/10.1109/iolts.2018.8474120</a>.","ieee":"S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,” 2018, doi: <a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>.","ama":"Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure for Aging Monitor Placement. In: <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>","apa":"Sadeghi-Kohan, S., Vafaei, A., &#38; Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>. <a href=\"https://doi.org/10.1109/iolts.2018.8474120\">https://doi.org/10.1109/iolts.2018.8474120</a>","short":"S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.","mla":"Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” <i>2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node Selection Procedure for Aging Monitor Placement}, DOI={<a href=\"https://doi.org/10.1109/iolts.2018.8474120\">10.1109/iolts.2018.8474120</a>}, booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}, year={2018} }"},"year":"2018","user_id":"78614","department":[{"_id":"48"}],"_id":"29459","extern":"1","language":[{"iso":"eng"}],"type":"conference","publication":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","status":"public","abstract":[{"lang":"eng","text":"Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits."}]},{"title":"Self-Adjusting Monitor for Measuring Aging Rate and Advancement","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_created":"2022-01-19T13:45:51Z","year":"2017","issue":"3","keyword":["Age advancement","age monitoring clock","aging rate","self-adjusting monitors"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively."}],"publication":"IEEE Transactions on Emerging Topics in Computing","doi":"10.1109/tetc.2017.2771441","date_updated":"2023-08-02T11:36:30Z","volume":8,"author":[{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"first_name":"Mehdi","last_name":"Kamal","full_name":"Kamal, Mehdi"},{"full_name":"Navabi, Zainalabedin","last_name":"Navabi","first_name":"Zainalabedin"}],"page":"627-641","intvolume":"         8","citation":{"ama":"Sadeghi-Kohan S, Kamal M, Navabi Z. Self-Adjusting Monitor for Measuring Aging Rate and Advancement. <i>IEEE Transactions on Emerging Topics in Computing</i>. 2017;8(3):627-641. doi:<a href=\"https://doi.org/10.1109/tetc.2017.2771441\">10.1109/tetc.2017.2771441</a>","chicago":"Sadeghi-Kohan, Somayeh, Mehdi Kamal, and Zainalabedin Navabi. “Self-Adjusting Monitor for Measuring Aging Rate and Advancement.” <i>IEEE Transactions on Emerging Topics in Computing</i> 8, no. 3 (2017): 627–41. <a href=\"https://doi.org/10.1109/tetc.2017.2771441\">https://doi.org/10.1109/tetc.2017.2771441</a>.","ieee":"S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring Aging Rate and Advancement,” <i>IEEE Transactions on Emerging Topics in Computing</i>, vol. 8, no. 3, pp. 627–641, 2017, doi: <a href=\"https://doi.org/10.1109/tetc.2017.2771441\">10.1109/tetc.2017.2771441</a>.","apa":"Sadeghi-Kohan, S., Kamal, M., &#38; Navabi, Z. (2017). Self-Adjusting Monitor for Measuring Aging Rate and Advancement. <i>IEEE Transactions on Emerging Topics in Computing</i>, <i>8</i>(3), 627–641. <a href=\"https://doi.org/10.1109/tetc.2017.2771441\">https://doi.org/10.1109/tetc.2017.2771441</a>","bibtex":"@article{Sadeghi-Kohan_Kamal_Navabi_2017, title={Self-Adjusting Monitor for Measuring Aging Rate and Advancement}, volume={8}, DOI={<a href=\"https://doi.org/10.1109/tetc.2017.2771441\">10.1109/tetc.2017.2771441</a>}, number={3}, journal={IEEE Transactions on Emerging Topics in Computing}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Kamal, Mehdi and Navabi, Zainalabedin}, year={2017}, pages={627–641} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Self-Adjusting Monitor for Measuring Aging Rate and Advancement.” <i>IEEE Transactions on Emerging Topics in Computing</i>, vol. 8, no. 3, Institute of Electrical and Electronics Engineers (IEEE), 2017, pp. 627–41, doi:<a href=\"https://doi.org/10.1109/tetc.2017.2771441\">10.1109/tetc.2017.2771441</a>.","short":"S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics in Computing 8 (2017) 627–641."},"publication_identifier":{"issn":["2168-6750","2376-4562"]},"publication_status":"published","extern":"1","_id":"29462","department":[{"_id":"48"}],"user_id":"78614","status":"public","type":"journal_article"},{"author":[{"last_name":"Jenihhin","full_name":"Jenihhin, Maksim","first_name":"Maksim"},{"full_name":"Kamkin, Alexander","last_name":"Kamkin","first_name":"Alexander"},{"last_name":"Navabi","full_name":"Navabi, Zainalabedin","first_name":"Zainalabedin"},{"first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"}],"date_created":"2022-01-19T13:50:13Z","publisher":"IEEE","date_updated":"2023-08-02T11:36:43Z","doi":"10.1109/ewdts.2016.7807635","title":"Universal mitigation of NBTI-induced aging by design randomization","publication_status":"published","citation":{"apa":"Jenihhin, M., Kamkin, A., Navabi, Z., &#38; Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. <i>2016 IEEE East-West Design &#38; Test Symposium (EWDTS)</i>. <a href=\"https://doi.org/10.1109/ewdts.2016.7807635\">https://doi.org/10.1109/ewdts.2016.7807635</a>","ama":"Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced aging by design randomization. In: <i>2016 IEEE East-West Design &#38; Test Symposium (EWDTS)</i>. IEEE; 2017. doi:<a href=\"https://doi.org/10.1109/ewdts.2016.7807635\">10.1109/ewdts.2016.7807635</a>","mla":"Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.” <i>2016 IEEE East-West Design &#38; Test Symposium (EWDTS)</i>, IEEE, 2017, doi:<a href=\"https://doi.org/10.1109/ewdts.2016.7807635\">10.1109/ewdts.2016.7807635</a>.","short":"M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West Design &#38; Test Symposium (EWDTS), IEEE, 2017.","bibtex":"@inproceedings{Jenihhin_Kamkin_Navabi_Sadeghi-Kohan_2017, title={Universal mitigation of NBTI-induced aging by design randomization}, DOI={<a href=\"https://doi.org/10.1109/ewdts.2016.7807635\">10.1109/ewdts.2016.7807635</a>}, booktitle={2016 IEEE East-West Design &#38; Test Symposium (EWDTS)}, publisher={IEEE}, author={Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan, Somayeh}, year={2017} }","ieee":"M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation of NBTI-induced aging by design randomization,” 2017, doi: <a href=\"https://doi.org/10.1109/ewdts.2016.7807635\">10.1109/ewdts.2016.7807635</a>.","chicago":"Jenihhin, Maksim, Alexander Kamkin, Zainalabedin Navabi, and Somayeh Sadeghi-Kohan. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.” In <i>2016 IEEE East-West Design &#38; Test Symposium (EWDTS)</i>. IEEE, 2017. <a href=\"https://doi.org/10.1109/ewdts.2016.7807635\">https://doi.org/10.1109/ewdts.2016.7807635</a>."},"year":"2017","department":[{"_id":"48"}],"user_id":"78614","_id":"29463","extern":"1","language":[{"iso":"eng"}],"publication":"2016 IEEE East-West Design & Test Symposium (EWDTS)","type":"conference","status":"public","abstract":[{"text":"In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.","lang":"eng"}]},{"year":"2015","citation":{"mla":"Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>, IEEE, 2015, doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Kamran_Forooghifar_Navabi_2015, title={Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation}, DOI={<a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>}, booktitle={2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}, year={2015} }","short":"S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.","apa":"Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., &#38; Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. <a href=\"https://doi.org/10.1109/dtis.2015.7127373\">https://doi.org/10.1109/dtis.2015.7127373</a>","ieee":"S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi: <a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>.","chicago":"Sadeghi-Kohan, Somayeh, Arezoo Kamran, Farnaz Forooghifar, and Zainalabedin Navabi. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” In <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE, 2015. <a href=\"https://doi.org/10.1109/dtis.2015.7127373\">https://doi.org/10.1109/dtis.2015.7127373</a>.","ama":"Sadeghi-Kohan S, Kamran A, Forooghifar F, Navabi Z. Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. In: <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE; 2015. doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127373\">10.1109/dtis.2015.7127373</a>"},"publication_status":"published","title":"Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation","doi":"10.1109/dtis.2015.7127373","publisher":"IEEE","date_updated":"2023-08-02T11:35:56Z","author":[{"orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"full_name":"Kamran, Arezoo","last_name":"Kamran","first_name":"Arezoo"},{"first_name":"Farnaz","full_name":"Forooghifar, Farnaz","last_name":"Forooghifar"},{"last_name":"Navabi","full_name":"Navabi, Zainalabedin","first_name":"Zainalabedin"}],"date_created":"2022-01-19T13:51:35Z","abstract":[{"lang":"eng","text":"Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors."}],"status":"public","publication":"2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","type":"conference","extern":"1","language":[{"iso":"eng"}],"_id":"29465","department":[{"_id":"48"}],"user_id":"78614"},{"publication_status":"published","citation":{"mla":"Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>, IEEE, 2015, doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Kamal_McNeil_Prinetto_Navabi_2015, title={Online self adjusting progressive age monitoring of timing variations}, DOI={<a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>}, booktitle={2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}, year={2015} }","short":"S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.","apa":"Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., &#38; Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. <a href=\"https://doi.org/10.1109/dtis.2015.7127368\">https://doi.org/10.1109/dtis.2015.7127368</a>","chicago":"Sadeghi-Kohan, Somayeh, Mehdi Kamal, John McNeil, Paolo Prinetto, and Zain Navabi. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” In <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE, 2015. <a href=\"https://doi.org/10.1109/dtis.2015.7127368\">https://doi.org/10.1109/dtis.2015.7127368</a>.","ieee":"S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” 2015, doi: <a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>.","ama":"Sadeghi-Kohan S, Kamal M, McNeil J, Prinetto P, Navabi Z. Online self adjusting progressive age monitoring of timing variations. In: <i>2015 10th International Conference on Design &#38; Technology of Integrated Systems in Nanoscale Era (DTIS)</i>. IEEE; 2015. doi:<a href=\"https://doi.org/10.1109/dtis.2015.7127368\">10.1109/dtis.2015.7127368</a>"},"year":"2015","author":[{"first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","id":"78614","full_name":"Sadeghi-Kohan, Somayeh"},{"first_name":"Mehdi","full_name":"Kamal, Mehdi","last_name":"Kamal"},{"first_name":"John","last_name":"McNeil","full_name":"McNeil, John"},{"first_name":"Paolo","full_name":"Prinetto, Paolo","last_name":"Prinetto"},{"first_name":"Zain","full_name":"Navabi, Zain","last_name":"Navabi"}],"date_created":"2022-01-19T13:52:32Z","date_updated":"2023-08-02T11:36:58Z","publisher":"IEEE","doi":"10.1109/dtis.2015.7127368","title":"Online self adjusting progressive age monitoring of timing variations","type":"conference","publication":"2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","status":"public","abstract":[{"lang":"eng","text":"Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes."}],"user_id":"78614","department":[{"_id":"48"}],"_id":"29466","language":[{"iso":"eng"}],"extern":"1"},{"publication_identifier":{"issn":["0018-9340"]},"publication_status":"published","year":"2014","page":"1-1","citation":{"chicago":"Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, 2014, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>.","ieee":"B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2014, doi: <a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>.","ama":"Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>. Published online 2014:1-1. doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>","bibtex":"@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }","mla":"Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” <i>IEEE Transactions on Computers</i>, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>.","short":"B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1.","apa":"Alizadeh, B., Behnam, P., &#38; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>"},"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2023-08-02T11:32:37Z","date_created":"2023-08-02T11:15:22Z","author":[{"first_name":"Bijan","full_name":"Alizadeh, Bijan","last_name":"Alizadeh"},{"full_name":"Behnam, Payman","last_name":"Behnam","first_name":"Payman"},{"first_name":"Somayeh","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610"}],"title":"A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs","doi":"10.1109/tc.2014.2329687","publication":"IEEE Transactions on Computers","type":"journal_article","status":"public","_id":"46266","department":[{"_id":"48"}],"user_id":"78614","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"extern":"1","language":[{"iso":"eng"}]}]