[{"language":[{"iso":"eng"}],"project":[{"_id":"296","name":"EKI-App: EKI-App: Energieeffiziente Künstliche Intelligenz im Rechenzentrum durch Approximation von tiefen neuronalen Netzen für Field-Programmable Gate Arrays"}],"_id":"59804","user_id":"67601","department":[{"_id":"518"}],"status":"public","type":"conference","publication":"Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","title":"FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC","doi":"10.1145/3728179.3728189","conference":{"end_date":"2025-05-28","location":"Kumamoto, Japan","name":"The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025)","start_date":"2025-05-26"},"date_updated":"2025-06-23T08:39:26Z","publisher":"ACM","date_created":"2025-05-05T11:12:47Z","author":[{"first_name":"Linus","full_name":"Jungemann, Linus","id":"67601","orcid":"0009-0003-9757-988X","last_name":"Jungemann"},{"first_name":"Bjarne","last_name":"Wintermann","full_name":"Wintermann, Bjarne"},{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"place":"New York City","year":"2025","citation":{"ama":"Jungemann L, Wintermann B, Riebler H, Plessl C. FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC. In: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM; 2025. doi:10.1145/3728179.3728189","chicago":"Jungemann, Linus, Bjarne Wintermann, Heinrich Riebler, and Christian Plessl. “FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC.” In Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. New York City: ACM, 2025. https://doi.org/10.1145/3728179.3728189.","ieee":"L. Jungemann, B. Wintermann, H. Riebler, and C. Plessl, “FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC,” presented at the The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025), Kumamoto, Japan, 2025, doi: 10.1145/3728179.3728189.","mla":"Jungemann, Linus, et al. “FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC.” Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2025, doi:10.1145/3728179.3728189.","short":"L. Jungemann, B. Wintermann, H. Riebler, C. Plessl, in: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, New York City, 2025.","bibtex":"@inproceedings{Jungemann_Wintermann_Riebler_Plessl_2025, place={New York City}, title={FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC}, DOI={10.1145/3728179.3728189}, booktitle={Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={ACM}, author={Jungemann, Linus and Wintermann, Bjarne and Riebler, Heinrich and Plessl, Christian}, year={2025} }","apa":"Jungemann, L., Wintermann, B., Riebler, H., & Plessl, C. (2025). FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC. Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025), Kumamoto, Japan. https://doi.org/10.1145/3728179.3728189"},"publication_status":"published","publication_identifier":{"unknown":["979-8-4007-1432-0/25/05"]}},{"status":"public","type":"conference","publication":"Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","language":[{"iso":"eng"}],"user_id":"67601","department":[{"_id":"27"}],"project":[{"name":"EKI-App: EKI-App: Energieeffiziente Künstliche Intelligenz im Rechenzentrum durch Approximation von tiefen neuronalen Netzen für Field-Programmable Gate Arrays","_id":"296"}],"_id":"59816","citation":{"apa":"Pape, G., Wintermann, B., Jungemann, L., Lass, M., Meyer, M., Riebler, H., & Plessl, C. (2025). AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan. https://doi.org/10.1145/3728179.3728190","bibtex":"@inproceedings{Pape_Wintermann_Jungemann_Lass_Meyer_Riebler_Plessl_2025, title={AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference}, DOI={10.1145/3728179.3728190}, booktitle={Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Pape, Gerrit and Wintermann, Bjarne and Jungemann, Linus and Lass, Michael and Meyer, Marius and Riebler, Heinrich and Plessl, Christian}, year={2025} }","mla":"Pape, Gerrit, et al. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025, doi:10.1145/3728179.3728190.","short":"G. Pape, B. Wintermann, L. Jungemann, M. Lass, M. Meyer, H. Riebler, C. Plessl, in: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025.","ama":"Pape G, Wintermann B, Jungemann L, et al. AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. In: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ; 2025. doi:10.1145/3728179.3728190","ieee":"G. Pape et al., “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference,” presented at the The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan, 2025, doi: 10.1145/3728179.3728190.","chicago":"Pape, Gerrit, Bjarne Wintermann, Linus Jungemann, Michael Lass, Marius Meyer, Heinrich Riebler, and Christian Plessl. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” In Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025. https://doi.org/10.1145/3728179.3728190."},"year":"2025","publication_status":"published","doi":"10.1145/3728179.3728190","conference":{"name":"The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) ","start_date":"2025-05-26","end_date":"2025-05-28","location":"Kumamoto, Japan"},"title":"AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference","author":[{"first_name":"Gerrit","last_name":"Pape","full_name":"Pape, Gerrit"},{"first_name":"Bjarne","orcid":"0009-0000-0856-6250","last_name":"Wintermann","id":"62900","full_name":"Wintermann, Bjarne"},{"orcid":"0009-0003-9757-988X","last_name":"Jungemann","full_name":"Jungemann, Linus","id":"67601","first_name":"Linus"},{"first_name":"Michael","full_name":"Lass, Michael","last_name":"Lass"},{"first_name":"Marius","last_name":"Meyer","full_name":"Meyer, Marius"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_created":"2025-05-06T09:53:41Z","date_updated":"2025-06-23T08:40:28Z"},{"oa":"1","date_updated":"2026-03-25T11:50:31Z","author":[{"last_name":"Ehtesabi","id":"116116","full_name":"Ehtesabi, Sadaf","first_name":"Sadaf"},{"first_name":"Manoar","full_name":"Hossain, Manoar","id":"114619","orcid":"https://orcid.org/0000-0002-0737-7981","last_name":"Hossain"},{"full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter","first_name":"Tobias"},{"last_name":"Krawinkel","id":"15275","full_name":"Krawinkel, Andreas","first_name":"Andreas"},{"last_name":"Ostermann","full_name":"Ostermann, Lukas","id":"69976","first_name":"Lukas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Stefan","last_name":"Rohde","full_name":"Rohde, Stefan","id":"34009"},{"id":"75963","full_name":"Schade, Robert","orcid":"0000-0002-6268-5397","last_name":"Schade","first_name":"Robert"},{"last_name":"Schwarz","full_name":"Schwarz, Michael","id":"5312","first_name":"Michael"},{"full_name":"Simon, Jens","id":"15273","last_name":"Simon","first_name":"Jens"},{"last_name":"Winnwa","full_name":"Winnwa, Nils","id":"61189","first_name":"Nils"},{"first_name":"Alex","last_name":"Wiens","orcid":"0000-0003-1764-9773","full_name":"Wiens, Alex","id":"23522"},{"first_name":"Xin","last_name":"Wu","id":"77439","full_name":"Wu, Xin"}],"volume":1,"doi":"10.48550/ARXIV.2512.07401","publication_status":"published","has_accepted_license":"1","place":"Paderborn","citation":{"ama":"Ehtesabi S, Hossain M, Kenter T, et al. Otus Supercomputer. Vol 1. Paderborn Center for Parallel Computing (PC2); 2025. doi:10.48550/ARXIV.2512.07401","ieee":"S. Ehtesabi et al., Otus Supercomputer, vol. 1. Paderborn: Paderborn Center for Parallel Computing (PC2), 2025.","chicago":"Ehtesabi, Sadaf, Manoar Hossain, Tobias Kenter, Andreas Krawinkel, Lukas Ostermann, Christian Plessl, Heinrich Riebler, et al. Otus Supercomputer. Vol. 1. PC2 Tech­nic­al Re­port Series. Paderborn: Paderborn Center for Parallel Computing (PC2), 2025. https://doi.org/10.48550/ARXIV.2512.07401.","apa":"Ehtesabi, S., Hossain, M., Kenter, T., Krawinkel, A., Ostermann, L., Plessl, C., Riebler, H., Rohde, S., Schade, R., Schwarz, M., Simon, J., Winnwa, N., Wiens, A., & Wu, X. (2025). Otus Supercomputer (Vol. 1). Paderborn Center for Parallel Computing (PC2). https://doi.org/10.48550/ARXIV.2512.07401","bibtex":"@book{Ehtesabi_Hossain_Kenter_Krawinkel_Ostermann_Plessl_Riebler_Rohde_Schade_Schwarz_et al._2025, place={Paderborn}, series={PC2 Tech­nic­al Re­port Series}, title={Otus Supercomputer}, volume={1}, DOI={10.48550/ARXIV.2512.07401}, publisher={Paderborn Center for Parallel Computing (PC2)}, author={Ehtesabi, Sadaf and Hossain, Manoar and Kenter, Tobias and Krawinkel, Andreas and Ostermann, Lukas and Plessl, Christian and Riebler, Heinrich and Rohde, Stefan and Schade, Robert and Schwarz, Michael and et al.}, year={2025}, collection={PC2 Tech­nic­al Re­port Series} }","short":"S. Ehtesabi, M. Hossain, T. Kenter, A. Krawinkel, L. Ostermann, C. Plessl, H. Riebler, S. Rohde, R. Schade, M. Schwarz, J. Simon, N. Winnwa, A. Wiens, X. Wu, Otus Supercomputer, Paderborn Center for Parallel Computing (PC2), Paderborn, 2025.","mla":"Ehtesabi, Sadaf, et al. Otus Supercomputer. Paderborn Center for Parallel Computing (PC2), 2025, doi:10.48550/ARXIV.2512.07401."},"page":"33","intvolume":" 1","_id":"62981","series_title":"PC2 Tech­nic­al Re­port Series","user_id":"23522","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2026-03-25T11:50:30Z","type":"report","status":"public","publisher":"Paderborn Center for Parallel Computing (PC2)","date_created":"2025-12-09T09:11:04Z","title":"Otus Supercomputer","year":"2025","ddc":["004"],"keyword":["Otus","Supercomputer","FPGA","PC2","Paderborn Center for Parallel Computing","Noctua 2","HPC"],"language":[{"iso":"eng"}],"report_number":"PC2TR-2025-1","abstract":[{"text":"Otus is a high-performance computing cluster that was launched in 2025 and is operated by the Paderborn Center for Parallel Computing (PC2) at Paderborn University in Germany. The system is part of the National High Performance Computing (NHR) initiative. Otus complements the previous supercomputer Noctua 2, offering approximately twice the computing power while retaining the three node types that were characteristic of Noctua 2: 1) CPU compute nodes with different memory capacities, 2) high-end GPU nodes, and 3) HPC-grade FPGA nodes. On the Top500 list, which ranks the 500 most powerful supercomputers in the world, Otus is in position 164 with the CPU partition and in position 255 with the GPU partition (June 2025). On the Green500 list, ranking the 500 most energy-efficient supercomputers in the world, Otus is in position 5 with the GPU partition (June 2025).\r\n\r\n\r\nThis article provides a comprehensive overview of the system in terms of its hardware, software, system integration, and its overall integration into the data center building to ensure energy-efficient operation. The article aims to provide unique insights for scientists using the system and for other centers operating HPC clusters. The article will be continuously updated to reflect the latest system setup and measurements. ","lang":"eng"}],"file":[{"access_level":"open_access","file_name":"2512.07401v1.pdf","file_id":"62982","file_size":4535595,"creator":"deffel","date_created":"2025-12-09T09:19:12Z","date_updated":"2026-03-25T11:50:30Z","relation":"main_file","content_type":"application/pdf"}]},{"has_accepted_license":"1","publication_status":"published","intvolume":" 9","citation":{"chicago":"Bauer, Carsten, Tobias Kenter, Michael Lass, Lukas Mazur, Marius Meyer, Holger Nitsche, Heinrich Riebler, et al. “Noctua 2 Supercomputer.” Journal of Large-Scale Research Facilities 9 (2024). https://doi.org/10.17815/jlsrf-8-187 .","ieee":"C. Bauer et al., “Noctua 2 Supercomputer,” Journal of large-scale research facilities, vol. 9, 2024, doi: 10.17815/jlsrf-8-187 .","ama":"Bauer C, Kenter T, Lass M, et al. Noctua 2 Supercomputer. Journal of large-scale research facilities. 2024;9. doi:10.17815/jlsrf-8-187 ","bibtex":"@article{Bauer_Kenter_Lass_Mazur_Meyer_Nitsche_Riebler_Schade_Schwarz_Winnwa_et al._2024, title={Noctua 2 Supercomputer}, volume={9}, DOI={10.17815/jlsrf-8-187 }, journal={Journal of large-scale research facilities}, author={Bauer, Carsten and Kenter, Tobias and Lass, Michael and Mazur, Lukas and Meyer, Marius and Nitsche, Holger and Riebler, Heinrich and Schade, Robert and Schwarz, Michael and Winnwa, Nils and et al.}, year={2024} }","mla":"Bauer, Carsten, et al. “Noctua 2 Supercomputer.” Journal of Large-Scale Research Facilities, vol. 9, 2024, doi:10.17815/jlsrf-8-187 .","short":"C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler, R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal of Large-Scale Research Facilities 9 (2024).","apa":"Bauer, C., Kenter, T., Lass, M., Mazur, L., Meyer, M., Nitsche, H., Riebler, H., Schade, R., Schwarz, M., Winnwa, N., Wiens, A., Wu, X., Plessl, C., & Simon, J. (2024). Noctua 2 Supercomputer. Journal of Large-Scale Research Facilities, 9. https://doi.org/10.17815/jlsrf-8-187 "},"volume":9,"author":[{"id":"90082","full_name":"Bauer, Carsten","last_name":"Bauer","first_name":"Carsten"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"first_name":"Michael","id":"24135","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass"},{"orcid":" 0000-0001-6304-7082","last_name":"Mazur","full_name":"Mazur, Lukas","id":"90492","first_name":"Lukas"},{"first_name":"Marius","id":"40778","full_name":"Meyer, Marius","last_name":"Meyer"},{"first_name":"Holger","last_name":"Nitsche","full_name":"Nitsche, Holger","id":"15272"},{"last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961","first_name":"Heinrich"},{"id":"75963","full_name":"Schade, Robert","last_name":"Schade","orcid":"0000-0002-6268-5397","first_name":"Robert"},{"first_name":"Michael","id":"5312","full_name":"Schwarz, Michael","last_name":"Schwarz"},{"first_name":"Nils","id":"61189","full_name":"Winnwa, Nils","last_name":"Winnwa"},{"last_name":"Wiens","orcid":"0000-0003-1764-9773","full_name":"Wiens, Alex","id":"23522","first_name":"Alex"},{"full_name":"Wu, Xin","id":"77439","last_name":"Wu","first_name":"Xin"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"first_name":"Jens","full_name":"Simon, Jens","id":"15273","last_name":"Simon"}],"oa":"1","date_updated":"2024-04-26T08:44:30Z","doi":"10.17815/jlsrf-8-187 ","type":"journal_article","status":"public","department":[{"_id":"27"},{"_id":"518"}],"user_id":"8961","_id":"53663","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"file_date_updated":"2024-04-26T08:35:17Z","article_type":"original","year":"2024","date_created":"2024-04-26T07:39:41Z","title":"Noctua 2 Supercomputer","publication":"Journal of large-scale research facilities","file":[{"file_name":"Noctua2_Supercomputer.pdf","file_id":"53664","access_level":"open_access","file_size":3825480,"date_created":"2024-04-26T07:30:20Z","creator":"deffel","date_updated":"2024-04-26T08:35:17Z","relation":"main_file","content_type":"application/pdf"}],"abstract":[{"lang":"eng","text":"Noctua 2 is a supercomputer operated at the Paderborn Center for Parallel Computing (PC2) at Paderborn University in Germany. Noctua 2 was inaugurated in 2022 and is an Atos BullSequana XH2000 system. It consists mainly of three node types: 1) CPU Compute nodes with AMD EPYC processors in different main memory configurations, 2) GPU nodes with NVIDIA A100 GPUs, and 3) FPGA nodes with Xilinx Alveo U280 and Intel Stratix 10 FPGA cards. While CPUs and GPUs are known off-the-shelf components in HPC systems, the operation of a large number of FPGA cards from different vendors and a dedicated FPGA-to-FPGA network are unique characteristics of Noctua 2. This paper describes in detail the overall setup of Noctua 2 and gives insights into the operation of the cluster from a hardware, software and facility perspective."}],"language":[{"iso":"eng"}],"keyword":["Noctua 2","Supercomputer","FPGA","PC2","Paderborn Center for Parallel Computing"],"ddc":["004"]},{"publication":"ACM Transactions on Reconfigurable Technology and Systems","abstract":[{"text":"This manuscript makes the claim of having computed the 9th Dedekind number, D(9). This was done by accelerating the core operation of the process with an efficient FPGA design that outperforms an optimized 64-core CPU reference by 95x. The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn University. The resulting value for D(9) is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490 M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. The paper explains the mathematical approach in the first part, before putting the focus on a deep dive into the FPGA accelerator implementation followed by a performance analysis. The FPGA implementation was done in Register-Transfer Level using a dual-clock architecture and shows how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800 FPGAs. The total compute time used was 47,000 FPGA hours.","lang":"eng"}],"language":[{"iso":"eng"}],"issue":"3","quality_controlled":"1","year":"2024","date_created":"2024-10-14T07:38:29Z","publisher":"Association for Computing Machinery (ACM)","title":"A Computation of the Ninth Dedekind Number Using FPGA Supercomputing","type":"journal_article","status":"public","department":[{"_id":"27"},{"_id":"518"}],"user_id":"3145","_id":"56604","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_identifier":{"issn":["1936-7406","1936-7414"]},"publication_status":"published","page":"1-28","intvolume":" 17","citation":{"ama":"Van Hirtum L, De Causmaecker P, Goemaere J, et al. A Computation of the Ninth Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and Systems. 2024;17(3):1-28. doi:10.1145/3674147","chicago":"Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of the Ninth Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems 17, no. 3 (2024): 1–28. https://doi.org/10.1145/3674147.","ieee":"L. Van Hirtum et al., “A Computation of the Ninth Dedekind Number Using FPGA Supercomputing,” ACM Transactions on Reconfigurable Technology and Systems, vol. 17, no. 3, pp. 1–28, 2024, doi: 10.1145/3674147.","short":"L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems 17 (2024) 1–28.","bibtex":"@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2024, title={A Computation of the Ninth Dedekind Number Using FPGA Supercomputing}, volume={17}, DOI={10.1145/3674147}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems}, publisher={Association for Computing Machinery (ACM)}, author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian}, year={2024}, pages={1–28} }","mla":"Van Hirtum, Lennart, et al. “A Computation of the Ninth Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems, vol. 17, no. 3, Association for Computing Machinery (ACM), 2024, pp. 1–28, doi:10.1145/3674147.","apa":"Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Lass, M., & Plessl, C. (2024). A Computation of the Ninth Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and Systems, 17(3), 1–28. https://doi.org/10.1145/3674147"},"volume":17,"author":[{"last_name":"Van Hirtum","id":"100210","full_name":"Van Hirtum, Lennart","first_name":"Lennart"},{"full_name":"De Causmaecker, Patrick","last_name":"De Causmaecker","first_name":"Patrick"},{"first_name":"Jens","full_name":"Goemaere, Jens","last_name":"Goemaere"},{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"first_name":"Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","full_name":"Lass, Michael","id":"24135"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_updated":"2025-11-04T09:53:26Z","oa":"1","doi":"10.1145/3674147","main_file_link":[{"open_access":"1"}]},{"language":[{"iso":"eng"}],"_id":"43439","external_id":{"arxiv":["2304.03039"]},"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"3145","abstract":[{"text":"This preprint makes the claim of having computed the $9^{th}$ Dedekind\r\nNumber. This was done by building an efficient FPGA Accelerator for the core\r\noperation of the process, and parallelizing it on the Noctua 2 Supercluster at\r\nPaderborn University. The resulting value is\r\n286386577668298411128469151667598498812366. This value can be verified in two\r\nsteps. We have made the data file containing the 490M results available, each\r\nof which can be verified separately on CPU, and the whole file sums to our\r\nproposed value.","lang":"eng"}],"status":"public","publication":"arXiv:2304.03039","type":"preprint","title":"A computation of D(9) using FPGA Supercomputing","date_updated":"2024-01-22T09:56:42Z","author":[{"first_name":"Lennart","last_name":"Van Hirtum","full_name":"Van Hirtum, Lennart"},{"full_name":"De Causmaecker, Patrick","last_name":"De Causmaecker","first_name":"Patrick"},{"last_name":"Goemaere","full_name":"Goemaere, Jens","first_name":"Jens"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"orcid":"0000-0002-5708-7632","last_name":"Lass","full_name":"Lass, Michael","id":"24135","first_name":"Michael"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"date_created":"2023-04-08T11:05:29Z","year":"2023","citation":{"chicago":"Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.","ieee":"L. Van Hirtum et al., “A computation of D(9) using FPGA Supercomputing,” arXiv:2304.03039. 2023.","ama":"Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using FPGA Supercomputing. arXiv:230403039. Published online 2023.","apa":"Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Lass, M., & Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing. In arXiv:2304.03039.","short":"L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ArXiv:2304.03039 (2023).","mla":"Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.","bibtex":"@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2023, title={A computation of D(9) using FPGA Supercomputing}, journal={arXiv:2304.03039}, author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian}, year={2023} }"}},{"type":"book_chapter","editor":[{"full_name":"Haake, Claus-Jochen","last_name":"Haake","first_name":"Claus-Jochen"},{"last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner"},{"last_name":"Wachsmuth","full_name":"Wachsmuth, Henning","first_name":"Henning"},{"first_name":"Heike","full_name":"Wehrheim, Heike","last_name":"Wehrheim"}],"status":"public","project":[{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)"}],"_id":"45893","series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","user_id":"398","department":[{"_id":"7"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2023-07-07T11:17:33Z","has_accepted_license":"1","place":"Paderborn","citation":{"ama":"Hansmeier T, Kenter T, Meyer M, Riebler H, Platzner M, Plessl C. Compute Centers I: Heterogeneous Execution Environments. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:165-182. doi:10.5281/zenodo.8068642","ieee":"T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, and C. Plessl, “Compute Centers I: Heterogeneous Execution Environments,” in On-The-Fly Computing -- Individualized IT-services in dynamic markets, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–182.","chicago":"Hansmeier, Tim, Tobias Kenter, Marius Meyer, Heinrich Riebler, Marco Platzner, and Christian Plessl. “Compute Centers I: Heterogeneous Execution Environments.” In On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:165–82. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. https://doi.org/10.5281/zenodo.8068642.","apa":"Hansmeier, T., Kenter, T., Meyer, M., Riebler, H., Platzner, M., & Plessl, C. (2023). Compute Centers I: Heterogeneous Execution Environments. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, & H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-services in dynamic markets (Vol. 412, pp. 165–182). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.5281/zenodo.8068642","short":"T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.","mla":"Hansmeier, Tim, et al. “Compute Centers I: Heterogeneous Execution Environments.” On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–82, doi:10.5281/zenodo.8068642.","bibtex":"@inbook{Hansmeier_Kenter_Meyer_Riebler_Platzner_Plessl_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Compute Centers I: Heterogeneous Execution Environments}, volume={412}, DOI={10.5281/zenodo.8068642}, booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Hansmeier, Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco and Plessl, Christian}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, pages={165–182}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }"},"page":"165-182","intvolume":" 412","oa":"1","date_updated":"2024-05-02T10:33:00Z","author":[{"id":"49992","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","last_name":"Hansmeier","first_name":"Tim"},{"full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Marius","full_name":"Meyer, Marius","id":"40778","last_name":"Meyer"},{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"volume":412,"doi":"10.5281/zenodo.8068642","publication":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","file":[{"date_updated":"2023-07-07T11:17:33Z","creator":"florida","date_created":"2023-07-07T08:15:35Z","file_size":2288788,"file_name":"C2-Chapter-SFB-Buch-Final.pdf","access_level":"open_access","file_id":"45894","content_type":"application/pdf","relation":"main_file"}],"ddc":["004"],"language":[{"iso":"eng"}],"year":"2023","publisher":"Heinz Nixdorf Institut, Universität Paderborn","date_created":"2023-07-07T08:15:45Z","title":"Compute Centers I: Heterogeneous Execution Environments"},{"language":[{"iso":"eng"}],"keyword":["htrop"],"ddc":["000"],"file":[{"date_created":"2019-02-13T14:59:07Z","creator":"deffel","date_updated":"2019-02-13T14:59:07Z","file_name":"htrop19_taco.pdf","file_id":"7695","access_level":"closed","file_size":872822,"content_type":"application/pdf","relation":"main_file"}],"publication":"ACM Trans. Archit. Code Optim. (TACO)","title":"Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL","date_created":"2019-02-13T15:01:43Z","publisher":"ACM","year":"2019","issue":"2","quality_controlled":"1","file_date_updated":"2019-02-13T14:59:07Z","article_type":"original","department":[{"_id":"27"},{"_id":"518"}],"user_id":"16153","_id":"7689","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"status":"public","type":"journal_article","doi":"10.1145/3319423","volume":16,"author":[{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_updated":"2022-01-06T07:03:44Z","intvolume":" 16","page":"14:1–14:26","citation":{"short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, ACM Trans. Archit. Code Optim. (TACO) 16 (2019) 14:1–14:26.","mla":"Riebler, Heinrich, et al. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:10.1145/3319423.","bibtex":"@article{Riebler_Vaz_Kenter_Plessl_2019, title={Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}, volume={16}, DOI={10.1145/3319423}, number={2}, journal={ACM Trans. Archit. Code Optim. (TACO)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2019}, pages={14:1–14:26} }","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2019). Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans. Archit. Code Optim. (TACO), 16(2), 14:1–14:26. https://doi.org/10.1145/3319423","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans Archit Code Optim (TACO). 2019;16(2):14:1–14:26. doi:10.1145/3319423","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO) 16, no. 2 (2019): 14:1–14:26. https://doi.org/10.1145/3319423."},"has_accepted_license":"1","publication_status":"published"},{"type":"dissertation","status":"public","_id":"34167","project":[{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"department":[{"_id":"27"}],"user_id":"15504","language":[{"iso":"eng"}],"year":"2019","citation":{"apa":"Riebler, H. (2019). Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. https://doi.org/10.17619/UNIPB/1-830","mla":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs. 2019, doi:10.17619/UNIPB/1-830.","short":"H. Riebler, Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019.","bibtex":"@book{Riebler_2019, title={Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs}, DOI={10.17619/UNIPB/1-830}, author={Riebler, Heinrich}, year={2019} }","chicago":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019. https://doi.org/10.17619/UNIPB/1-830.","ieee":"H. Riebler, Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. 2019.","ama":"Riebler H. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs.; 2019. doi:10.17619/UNIPB/1-830"},"date_updated":"2022-11-30T14:44:15Z","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"}],"supervisor":[{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_created":"2022-11-30T14:36:04Z","title":"Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs","doi":"10.17619/UNIPB/1-830"},{"type":"conference","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"_id":"1204","file_date_updated":"2018-11-02T14:43:37Z","publication_status":"published","has_accepted_license":"1","publication_identifier":{"isbn":["9781450349826"]},"citation":{"bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534."},"author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"},{"id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_updated":"2023-09-26T11:47:23Z","doi":"10.1145/3178487.3178534","publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":447769,"access_level":"closed","file_id":"5281","file_name":"p417-riebler.pdf","date_updated":"2018-11-02T14:43:37Z","creator":"ups","date_created":"2018-11-02T14:43:37Z"}],"language":[{"iso":"eng"}],"ddc":["000"],"keyword":["htrop"],"quality_controlled":"1","year":"2018","date_created":"2018-03-08T14:45:18Z","publisher":"ACM","title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices"},{"file_date_updated":"2018-11-02T16:04:14Z","department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","_id":"18","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","type":"journal_article","doi":"10.1145/3053687","volume":10,"author":[{"first_name":"Heinrich","id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler"},{"last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","id":"24135","first_name":"Michael"},{"full_name":"Mittendorf, Robert","last_name":"Mittendorf","first_name":"Robert"},{"full_name":"Löcke, Thomas","last_name":"Löcke","first_name":"Thomas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2023-09-26T13:23:58Z","page":"24:1-24:23","intvolume":" 10","citation":{"chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.","ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi: 10.1145/3053687.","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687.","short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.","bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={10.1145/3053687}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23. https://doi.org/10.1145/3053687"},"has_accepted_license":"1","publication_identifier":{"issn":["1936-7406"]},"publication_status":"published","language":[{"iso":"eng"}],"keyword":["coldboot"],"ddc":["000"],"file":[{"file_size":2131617,"file_id":"5322","file_name":"a24-riebler.pdf","access_level":"closed","date_updated":"2018-11-02T16:04:14Z","creator":"ups","date_created":"2018-11-02T16:04:14Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"abstract":[{"text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.","lang":"eng"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","date_created":"2017-07-25T14:17:32Z","publisher":"Association for Computing Machinery (ACM)","year":"2017","issue":"3","quality_controlled":"1"},{"citation":{"chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)."},"year":"2016","quality_controlled":"1","has_accepted_license":"1","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G.","first_name":"Ettore M. G."},{"first_name":"Gianluca C.","full_name":"Durelli, Gianluca C.","last_name":"Durelli"},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"date_created":"2017-07-26T15:16:31Z","date_updated":"2023-09-26T13:25:59Z","file":[{"file_size":394563,"access_level":"closed","file_id":"6626","file_name":"wrc_upb_polimi_final.pdf","date_updated":"2019-01-11T11:56:55Z","date_created":"2019-01-11T11:56:55Z","creator":"deffel","success":1,"relation":"main_file","content_type":"application/pdf"}],"status":"public","type":"conference","publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","file_date_updated":"2019-01-11T11:56:55Z","language":[{"iso":"eng"}],"ddc":["040"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"31"},{"ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-21T13:01:09Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"138","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"file":[{"date_updated":"2018-03-21T13:01:09Z","creator":"florida","date_created":"2018-03-21T13:01:09Z","file_size":184334,"access_level":"closed","file_id":"1560","file_name":"138-07740545.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"status":"public","type":"conference","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","doi":"10.1109/RTSI.2016.7740545","date_updated":"2023-09-26T13:28:11Z","publisher":"IEEE","date_created":"2017-10-17T12:41:18Z","author":[{"first_name":"Heinrich","id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz","first_name":"Gavin Francis"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G. ","first_name":"Ettore M. G. "},{"last_name":"Durelli","full_name":"Durelli, Gianluca C.","first_name":"Gianluca C."},{"first_name":"Emanuele","last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele"},{"first_name":"Marco D. ","full_name":"Santambrogio, Marco D. ","last_name":"Santambrogio"},{"first_name":"Christina","last_name":"Bolchini","full_name":"Bolchini, Christina"}],"year":"2016","citation":{"bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.","ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545"},"page":"1-5","has_accepted_license":"1","quality_controlled":"1"},{"year":"2016","quality_controlled":"1","title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code","publisher":"Elsevier","date_created":"2017-10-17T12:41:24Z","abstract":[{"lang":"eng","text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes."}],"file":[{"file_name":"165-1-s2.0-S0045790616301021-main.pdf","access_level":"closed","file_id":"1544","file_size":3037854,"creator":"florida","date_created":"2018-03-21T12:45:47Z","date_updated":"2018-03-21T12:45:47Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"publication":"Computers and Electrical Engineering","ddc":["040"],"language":[{"iso":"eng"}],"page":"91-111","intvolume":" 55","citation":{"ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021"},"has_accepted_license":"1","publication_identifier":{"issn":["0045-7906"]},"doi":"10.1016/j.compeleceng.2016.04.021","date_updated":"2023-09-26T13:26:38Z","volume":55,"author":[{"last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Heinrich","last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"status":"public","type":"journal_article","file_date_updated":"2018-03-21T12:45:47Z","_id":"165","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278"},{"date_updated":"2023-09-26T13:27:21Z","date_created":"2017-10-17T12:41:25Z","author":[{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz","first_name":"Gavin Francis"},{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","quality_controlled":"1","has_accepted_license":"1","year":"2016","citation":{"apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016."},"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"171","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-21T12:39:46Z","type":"conference","publication":"Workshop on Reconfigurable Computing (WRC)","file":[{"date_created":"2018-03-21T12:39:46Z","creator":"florida","date_updated":"2018-03-21T12:39:46Z","access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","file_id":"1538","file_size":54421,"content_type":"application/pdf","relation":"main_file","success":1}],"status":"public"},{"type":"conference","status":"public","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"238","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2018-03-21T10:29:49Z","has_accepted_license":"1","citation":{"apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124"},"page":"1078-1083","date_updated":"2023-09-26T13:31:44Z","author":[{"first_name":"Marvin","last_name":"Damschen","full_name":"Damschen, Marvin"},{"first_name":"Heinrich","id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"doi":"10.7873/DATE.2015.1124","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-21T10:29:49Z","creator":"florida","date_created":"2018-03-21T10:29:49Z","file_size":380552,"file_name":"238-plessl15_date.pdf","file_id":"1500","access_level":"closed"}],"ddc":["040"],"language":[{"iso":"eng"}],"quality_controlled":"1","year":"2015","publisher":"EDA Consortium / IEEE","date_created":"2017-10-17T12:41:38Z","title":"Transparent offloading of computational hotspots from binary code to Xeon Phi"},{"doi":"10.1109/FCCM.2014.67","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"}],"date_updated":"2023-09-26T13:33:50Z","citation":{"apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67"},"page":"222-229","has_accepted_license":"1","file_date_updated":"2018-03-20T07:14:20Z","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"377","status":"public","type":"conference","title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","date_created":"2017-10-17T12:42:05Z","publisher":"IEEE","year":"2014","quality_controlled":"1","language":[{"iso":"eng"}],"ddc":["040"],"keyword":["coldboot"],"file":[{"date_updated":"2018-03-20T07:14:20Z","creator":"florida","date_created":"2018-03-20T07:14:20Z","file_size":1003907,"access_level":"closed","file_id":"1397","file_name":"377-FCCM14.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)"},{"type":"conference","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","status":"public","project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"1778","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"language":[{"iso":"eng"}],"quality_controlled":"1","year":"2014","citation":{"bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27"},"page":"142-149","publisher":"IEEE","date_updated":"2023-09-26T13:35:40Z","author":[{"first_name":"Gianluca","full_name":"C. Durelli, Gianluca","last_name":"C. Durelli"},{"first_name":"Marcello","full_name":"Pogliani, Marcello","last_name":"Pogliani"},{"first_name":"Antonio","last_name":"Miele","full_name":"Miele, Antonio"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961","first_name":"Heinrich"},{"first_name":"Gavin Francis","last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"first_name":"Cristiana","last_name":"Bolchini","full_name":"Bolchini, Cristiana"}],"date_created":"2018-03-26T13:40:14Z","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","doi":"10.1109/ISPA.2014.27"},{"quality_controlled":"1","year":"2014","publisher":"IEEE","date_created":"2017-10-17T12:42:17Z","title":"Deferring Accelerator Offloading Decisions to Application Runtime","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_id":"1353","access_level":"closed","file_name":"439-plessl14a_reconfig.pdf","file_size":557362,"creator":"florida","date_created":"2018-03-16T11:29:52Z","date_updated":"2018-03-16T11:29:52Z"}],"ddc":["040"],"language":[{"iso":"eng"}],"has_accepted_license":"1","page":"1-8","citation":{"ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509"},"date_updated":"2023-09-26T13:37:02Z","author":[{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"doi":"10.1109/ReConFig.2014.7032509","type":"conference","status":"public","_id":"439","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","file_date_updated":"2018-03-16T11:29:52Z"},{"date_created":"2017-10-17T12:42:34Z","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"}],"publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:46Z","title":"Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs","citation":{"apa":"Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn.","mla":"Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","bibtex":"@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Universität Paderborn}, author={Riebler, Heinrich}, year={2013} }","short":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs, Universität Paderborn, 2013.","ieee":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","chicago":"Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","ama":"Riebler H. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn; 2013."},"year":"2013","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"13","name":"SFB 901 - Subprojekt C1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"_id":"521","language":[{"iso":"ger"}],"keyword":["coldboot"],"type":"mastersthesis","status":"public"}]