@article{62148,
  author       = {{Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}},
  issn         = {{1063-8210}},
  journal      = {{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
  publisher    = {{IEEE}},
  title        = {{{60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}}},
  doi          = {{10.1109/TVLSI.2025.3625787}},
  year         = {{2025}},
}

@inproceedings{62126,
  author       = {{Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{IEEE Nordic Circuits and Systems Conference (NORCAS)}},
  location     = {{Riga, Latvia}},
  title        = {{{A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}}},
  doi          = {{10.1109/NorCAS66540.2025.11231203}},
  year         = {{2025}},
}

@article{62644,
  author       = {{Schwabe, Tobias and Kress, Christian and Sadiye, Babak and Kruse, Stephan and Scheytt, J. Christoph}},
  journal      = {{IEEE Access}},
  keywords     = {{Optical attenuators, Equalizers, Phase shifters, Optical modulation, Electro-optic modulators, Optical amplifiers, Circuits, Silicon photonics, Optical saturation, Integrated circuit modeling, Data communication, equalization, electro-optical transmitter, silicon photonics, phase shifter, optical modulator, free-carrier plasma dispersion effect, driver architectures, biasing schemes}},
  pages        = {{192433--192450}},
  title        = {{{Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits}}},
  doi          = {{10.1109/ACCESS.2025.3629385}},
  volume       = {{13}},
  year         = {{2025}},
}

@inproceedings{53579,
  author       = {{Palomero Bernardo, Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel and Feldner, Ingo and Ecker, Wolfgang}},
  booktitle    = {{DATE 24 - Design Automation and Test in Europe}},
  location     = {{Valencia, Spain}},
  title        = {{{A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing}}},
  year         = {{2024}},
}

@inproceedings{45778,
  abstract     = {{RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple
RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core
processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells
(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.
This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level
(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based
implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This
work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with
different local address spaces.}},
  author       = {{Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}},
  booktitle    = {{MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}},
  location     = {{Germany,  Freiburg}},
  publisher    = {{VDE Verlag}},
  title        = {{{Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}}},
  year         = {{2024}},
}

@inproceedings{45776,
  author       = {{Ecker, Wolfgang and Krstic, Milos and Ulbricht, Markus and Mauderer, Andreas and Jentzsch, Eyck and Koch, Andreas and Koppelmann, Bastian and Müller, Wolfgang and Sadiye, Babak and Bruns, Niklas and Drechsler, Rolf and Müller-Gritschneder, Daniel and Schlamelcher, Jan and Grüttner, Kim and Bormann, Jörg and Kunz, Wolfgang and Heckmann, Reinhold and Angst, Gerhard and Wimmer, Ralf and Becker, Bernd and Faller, Tobias and Palomero Bernardo, Paul and Brinkmann, Oliver and Partzsch, Johannes and Mayr, Christian}},
  booktitle    = {{RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.}},
  location     = {{ Barcelona, Spain,}},
  title        = {{{Scale4Edge – Scaling RISC-V for Edge Applications}}},
  year         = {{2023}},
}

@inproceedings{48961,
  author       = {{Iftekhar, Mohammed and Gowda, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}},
  location     = {{Monterey, CA, USA}},
  title        = {{{A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology}}},
  doi          = {{10.1109/BCICTS54660.2023.10310954}},
  year         = {{2023}},
}

@inproceedings{45775,
  abstract     = {{RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple
RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core
processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells
(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.
This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level
(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based
implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This
work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with
different local address spaces.}},
  author       = {{Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}},
  booktitle    = {{MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}},
  location     = {{Freiburg}},
  publisher    = {{VDE Verlag}},
  title        = {{{Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}}},
  year         = {{2023}},
}

@inproceedings{47064,
  author       = {{Iftekhar, Mohammed and Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}},
  location     = {{MONTEREY, CALIFORNIA, USA}},
  title        = {{{A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology }}},
  year         = {{2023}},
}