[{"publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","type":"journal_article","status":"public","department":[{"_id":"58"}],"user_id":"93634","_id":"62148","project":[{"name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing","_id":"325"}],"language":[{"iso":"eng"}],"publication_identifier":{"issn":["1063-8210"]},"publication_status":"published","citation":{"ama":"Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. Published online 2025. doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>","chicago":"Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>.","ieee":"B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025, doi: <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","apa":"Sadiye, B., Iftekhar, M., Müller, W., &#38; Scheytt, J. C. (2025). 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>","short":"B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).","mla":"Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","bibtex":"@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }"},"year":"2025","author":[{"id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye","first_name":"Babak"},{"first_name":"Mohammed","last_name":"Iftekhar","id":"47944","full_name":"Iftekhar, Mohammed"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"last_name":"Scheytt","orcid":"0000-0002-5950-6618 ","full_name":"Scheytt, J. Christoph","id":"37144","first_name":"J. Christoph"}],"date_created":"2025-11-10T08:31:47Z","publisher":"IEEE","date_updated":"2025-11-10T08:38:07Z","doi":"10.1109/TVLSI.2025.3625787","title":"60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design"},{"conference":{"end_date":"2025-10-29","location":"Riga, Latvia","name":"IEEE Nordic Circuits and Systems Conference (NORCAS)","start_date":"2025-10-28"},"doi":"10.1109/NorCAS66540.2025.11231203","title":"A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology","author":[{"last_name":"Iftekhar","id":"47944","full_name":"Iftekhar, Mohammed","first_name":"Mohammed"},{"full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye","first_name":"Babak"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","first_name":"J. Christoph"}],"date_created":"2025-11-07T10:41:45Z","date_updated":"2025-11-20T10:34:13Z","citation":{"ama":"Iftekhar M, Sadiye B, Müller W, Scheytt JC. A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. In: <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. ; 2025. doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>","chicago":"Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>.","ieee":"M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia, 2025, doi: <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","mla":"Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025, doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","short":"M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits and Systems Conference (NORCAS), 2025.","bibtex":"@inproceedings{Iftekhar_Sadiye_Müller_Scheytt_2025, title={A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>}, booktitle={IEEE Nordic Circuits and Systems Conference (NORCAS)}, author={Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","apa":"Iftekhar, M., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2025). A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>"},"year":"2025","language":[{"iso":"eng"}],"user_id":"47944","department":[{"_id":"58"}],"project":[{"_id":"325","name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing"}],"_id":"62126","status":"public","type":"conference","publication":"IEEE Nordic Circuits and Systems Conference (NORCAS)"},{"keyword":["Optical attenuators","Equalizers","Phase shifters","Optical modulation","Electro-optic modulators","Optical amplifiers","Circuits","Silicon photonics","Optical saturation","Integrated circuit modeling","Data communication","equalization","electro-optical transmitter","silicon photonics","phase shifter","optical modulator","free-carrier plasma dispersion effect","driver architectures","biasing schemes"],"language":[{"iso":"eng"}],"_id":"62644","user_id":"38254","department":[{"_id":"58"}],"status":"public","type":"journal_article","publication":"IEEE Access","title":"Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits","doi":"10.1109/ACCESS.2025.3629385","date_updated":"2025-11-27T07:16:06Z","author":[{"first_name":"Tobias","full_name":"Schwabe, Tobias","id":"39217","last_name":"Schwabe"},{"first_name":"Christian","full_name":"Kress, Christian","id":"13256","orcid":"0000-0002-4403-2237","last_name":"Kress"},{"first_name":"Babak","id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye"},{"id":"38254","full_name":"Kruse, Stephan","last_name":"Kruse","first_name":"Stephan"},{"full_name":"Scheytt, J. Christoph","id":"37144","last_name":"Scheytt","orcid":"0000-0002-5950-6618 ","first_name":"J. Christoph"}],"date_created":"2025-11-27T07:14:48Z","volume":13,"year":"2025","citation":{"apa":"Schwabe, T., Kress, C., Sadiye, B., Kruse, S., &#38; Scheytt, J. C. (2025). Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits. <i>IEEE Access</i>, <i>13</i>, 192433–192450. <a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">https://doi.org/10.1109/ACCESS.2025.3629385</a>","bibtex":"@article{Schwabe_Kress_Sadiye_Kruse_Scheytt_2025, title={Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits}, volume={13}, DOI={<a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>}, journal={IEEE Access}, author={Schwabe, Tobias and Kress, Christian and Sadiye, Babak and Kruse, Stephan and Scheytt, J. Christoph}, year={2025}, pages={192433–192450} }","mla":"Schwabe, Tobias, et al. “Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits.” <i>IEEE Access</i>, vol. 13, 2025, pp. 192433–50, doi:<a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>.","short":"T. Schwabe, C. Kress, B. Sadiye, S. Kruse, J.C. Scheytt, IEEE Access 13 (2025) 192433–192450.","ama":"Schwabe T, Kress C, Sadiye B, Kruse S, Scheytt JC. Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits. <i>IEEE Access</i>. 2025;13:192433-192450. doi:<a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>","chicago":"Schwabe, Tobias, Christian Kress, Babak Sadiye, Stephan Kruse, and J. Christoph Scheytt. “Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits.” <i>IEEE Access</i> 13 (2025): 192433–50. <a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">https://doi.org/10.1109/ACCESS.2025.3629385</a>.","ieee":"T. Schwabe, C. Kress, B. Sadiye, S. Kruse, and J. C. Scheytt, “Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits,” <i>IEEE Access</i>, vol. 13, pp. 192433–192450, 2025, doi: <a href=\"https://doi.org/10.1109/ACCESS.2025.3629385\">10.1109/ACCESS.2025.3629385</a>."},"page":"192433-192450","intvolume":"        13"},{"status":"public","publication":"DATE 24 - Design Automation and Test in Europe","type":"conference","language":[{"iso":"eng"}],"_id":"53579","department":[{"_id":"58"}],"user_id":"16243","year":"2024","citation":{"chicago":"Palomero Bernardo, Paul, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” In <i>DATE 24 - Design Automation and Test in Europe</i>, 2024.","ieee":"P. Palomero Bernardo <i>et al.</i>, “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.","ama":"Palomero Bernardo P, Schmid P, Bringmann O, et al. A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. In: <i>DATE 24 - Design Automation and Test in Europe</i>. ; 2024.","mla":"Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” <i>DATE 24 - Design Automation and Test in Europe</i>, 2024.","bibtex":"@inproceedings{Palomero Bernardo_Schmid_Bringmann_Iftekhar_Sadiye_Müller_Koch_Jentsch_Sauer_Feldner_et al._2024, title={A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing}, booktitle={DATE 24 - Design Automation and Test in Europe}, author={Palomero Bernardo, Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel and Feldner, Ingo and et al.}, year={2024} }","short":"P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W. Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design Automation and Test in Europe, 2024.","apa":"Palomero Bernardo, P., Schmid, P., Bringmann, O., Iftekhar, M., Sadiye, B., Müller, W., Koch, A., Jentsch, E., Sauer, A., Feldner, I., &#38; Ecker, W. (2024). A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. <i>DATE 24 - Design Automation and Test in Europe</i>."},"title":"A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing","conference":{"location":"Valencia, Spain"},"date_updated":"2024-04-18T20:25:29Z","author":[{"first_name":"Paul","last_name":"Palomero Bernardo","full_name":"Palomero Bernardo, Paul"},{"first_name":"Patrick","last_name":"Schmid","full_name":"Schmid, Patrick"},{"first_name":"Oliver","full_name":"Bringmann, Oliver","last_name":"Bringmann"},{"first_name":"Mohammed","last_name":"Iftekhar","id":"47944","full_name":"Iftekhar, Mohammed"},{"last_name":"Sadiye","full_name":"Sadiye, Babak","id":"93634","first_name":"Babak"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"last_name":"Koch","full_name":"Koch, Andreas","first_name":"Andreas"},{"full_name":"Jentsch, Eyck","last_name":"Jentsch","first_name":"Eyck"},{"full_name":"Sauer, Axel","last_name":"Sauer","first_name":"Axel"},{"full_name":"Feldner, Ingo","last_name":"Feldner","first_name":"Ingo"},{"last_name":"Ecker","full_name":"Ecker, Wolfgang","first_name":"Wolfgang"}],"date_created":"2024-04-18T20:25:23Z"},{"year":"2024","citation":{"ama":"Luchterhandt L, Nellius T, Beck R, et al. Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. In: <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>. VDE Verlag; 2024.","chicago":"Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>. VDE Verlag, 2024.","ieee":"L. Luchterhandt <i>et al.</i>, “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg, 2024.","short":"L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.","bibtex":"@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2024, title={Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}, booktitle={MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2024} }","mla":"Luchterhandt, Lars, et al. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>, VDE Verlag, 2024.","apa":"Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., &#38; Sadiye, B. (2024). Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. <i>MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“</i>. MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg."},"title":"Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells","conference":{"name":"MBMV 2023 - 26. Workshop, Freiburg, ","start_date":"2023.03.23","end_date":"2023.03.24","location":"Germany,  Freiburg"},"date_updated":"2025-02-24T10:40:29Z","publisher":"VDE Verlag","author":[{"last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","first_name":"Lars"},{"last_name":"Nellius","full_name":"Nellius, Tom","first_name":"Tom"},{"first_name":"Robert","full_name":"Beck, Robert","last_name":"Beck"},{"first_name":"Rainer","last_name":"Dömer","full_name":"Dömer, Rainer"},{"first_name":"Pascal","last_name":"Kneuper","full_name":"Kneuper, Pascal","id":"47367"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Babak","id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye"}],"date_created":"2023-06-26T12:32:07Z","abstract":[{"lang":"eng","text":"RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple\r\nRISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.\r\nThis paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This\r\nwork also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with\r\ndifferent local address spaces."}],"status":"public","type":"conference","publication":"MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“","language":[{"iso":"eng"}],"_id":"45778","user_id":"16243","department":[{"_id":"58"}]},{"date_created":"2023-06-26T12:16:36Z","author":[{"full_name":"Ecker, Wolfgang","last_name":"Ecker","first_name":"Wolfgang"},{"first_name":"Milos","last_name":"Krstic","full_name":"Krstic, Milos"},{"first_name":"Markus","last_name":"Ulbricht","full_name":"Ulbricht, Markus"},{"full_name":"Mauderer, Andreas","last_name":"Mauderer","first_name":"Andreas"},{"last_name":"Jentzsch","full_name":"Jentzsch, Eyck","first_name":"Eyck"},{"first_name":"Andreas","last_name":"Koch","full_name":"Koch, Andreas"},{"first_name":"Bastian","full_name":"Koppelmann, Bastian","id":"25260","last_name":"Koppelmann"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye","first_name":"Babak"},{"last_name":"Bruns","full_name":"Bruns, Niklas","first_name":"Niklas"},{"first_name":"Rolf","full_name":"Drechsler, Rolf","last_name":"Drechsler"},{"full_name":"Müller-Gritschneder, Daniel","last_name":"Müller-Gritschneder","first_name":"Daniel"},{"last_name":"Schlamelcher","full_name":"Schlamelcher, Jan","first_name":"Jan"},{"first_name":"Kim","last_name":"Grüttner","full_name":"Grüttner, Kim"},{"full_name":"Bormann, Jörg","last_name":"Bormann","first_name":"Jörg"},{"first_name":"Wolfgang","last_name":"Kunz","full_name":"Kunz, Wolfgang"},{"first_name":"Reinhold","last_name":"Heckmann","full_name":"Heckmann, Reinhold"},{"full_name":"Angst, Gerhard","last_name":"Angst","first_name":"Gerhard"},{"full_name":"Wimmer, Ralf","last_name":"Wimmer","first_name":"Ralf"},{"first_name":"Bernd","full_name":"Becker, Bernd","last_name":"Becker"},{"last_name":"Faller","full_name":"Faller, Tobias","first_name":"Tobias"},{"full_name":"Palomero Bernardo, Paul","last_name":"Palomero Bernardo","first_name":"Paul"},{"first_name":"Oliver","last_name":"Brinkmann","full_name":"Brinkmann, Oliver"},{"first_name":"Johannes","full_name":"Partzsch, Johannes","last_name":"Partzsch"},{"full_name":"Mayr, Christian","last_name":"Mayr","first_name":"Christian"}],"date_updated":"2024-04-18T20:07:44Z","conference":{"location":" Barcelona, Spain,","end_date":"2023.06.09","start_date":"2023.06.05","name":"RISC-V Summit Europe 2023, Barcelona, Spain, June 2023."},"title":"Scale4Edge – Scaling RISC-V for Edge Applications","related_material":{"link":[{"url":"https://riscv-europe.org/media/proceedings/posters/2023-06-06-Wolfgang-ECKER-abstract.pdf","relation":"slides"},{"url":"https://riscv-europe.org/","relation":"other"}]},"citation":{"ama":"Ecker W, Krstic M, Ulbricht M, et al. Scale4Edge – Scaling RISC-V for Edge Applications. In: <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i> ; 2023.","chicago":"Ecker, Wolfgang, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” In <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i>, 2023.","ieee":"W. Ecker <i>et al.</i>, “Scale4Edge – Scaling RISC-V for Edge Applications,” presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.,  Barcelona, Spain, 2023.","apa":"Ecker, W., Krstic, M., Ulbricht, M., Mauderer, A., Jentzsch, E., Koch, A., Koppelmann, B., Müller, W., Sadiye, B., Bruns, N., Drechsler, R., Müller-Gritschneder, D., Schlamelcher, J., Grüttner, K., Bormann, J., Kunz, W., Heckmann, R., Angst, G., Wimmer, R., … Mayr, C. (2023). Scale4Edge – Scaling RISC-V for Edge Applications. <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i> RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.,  Barcelona, Spain,.","bibtex":"@inproceedings{Ecker_Krstic_Ulbricht_Mauderer_Jentzsch_Koch_Koppelmann_Müller_Sadiye_Bruns_et al._2023, title={Scale4Edge – Scaling RISC-V for Edge Applications}, booktitle={RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.}, author={Ecker, Wolfgang and Krstic, Milos and Ulbricht, Markus and Mauderer, Andreas and Jentzsch, Eyck and Koch, Andreas and Koppelmann, Bastian and Müller, Wolfgang and Sadiye, Babak and Bruns, Niklas and et al.}, year={2023} }","short":"W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B. Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder, J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer, B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr, in: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.","mla":"Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” <i>RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.</i>, 2023."},"year":"2023","user_id":"16243","department":[{"_id":"58"}],"_id":"45776","language":[{"iso":"eng"}],"type":"conference","publication":"RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.","status":"public"},{"conference":{"name":"2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","start_date":"2023-10-16","end_date":"2023-10-18","location":"Monterey, CA, USA"},"doi":"10.1109/BCICTS54660.2023.10310954","title":"A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology","author":[{"full_name":"Iftekhar, Mohammed","id":"47944","last_name":"Iftekhar","first_name":"Mohammed"},{"first_name":"Harshan","last_name":"Gowda","full_name":"Gowda, Harshan"},{"first_name":"Pascal","last_name":"Kneuper","full_name":"Kneuper, Pascal","id":"47367"},{"first_name":"Babak","last_name":"Sadiye","id":"93634","full_name":"Sadiye, Babak"},{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph"}],"date_created":"2023-11-16T11:04:41Z","date_updated":"2024-04-19T11:43:21Z","citation":{"apa":"Iftekhar, M., Gowda, H., Kneuper, P., Sadiye, B., Müller, W., &#38; Scheytt, C. (2023). A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA. <a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">https://doi.org/10.1109/BCICTS54660.2023.10310954</a>","short":"M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023.","bibtex":"@inproceedings{Iftekhar_Gowda_Kneuper_Sadiye_Müller_Scheytt_2023, title={A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>}, booktitle={2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}, author={Iftekhar, Mohammed and Gowda, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph}, year={2023} }","mla":"Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>, 2023, doi:<a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>.","ama":"Iftekhar M, Gowda H, Kneuper P, Sadiye B, Müller W, Scheytt C. A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. In: <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>. ; 2023. doi:<a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>","ieee":"M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi: <a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">10.1109/BCICTS54660.2023.10310954</a>.","chicago":"Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” In <i>2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)</i>, 2023. <a href=\"https://doi.org/10.1109/BCICTS54660.2023.10310954\">https://doi.org/10.1109/BCICTS54660.2023.10310954</a>."},"year":"2023","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/10310954","relation":"confirmation"}]},"publication_identifier":{"eisbn":["979-8-3503-0764-1"]},"language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"15931","_id":"48961","status":"public","publication":"2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","type":"conference_abstract"},{"citation":{"ama":"Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. In: <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. VDE Verlag; 2023.","chicago":"Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. VDE Verlag, 2023.","ieee":"L. Luchterhandt <i>et al.</i>, “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.","short":"L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.","mla":"Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>, VDE Verlag, 2023.","bibtex":"@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023, title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}, booktitle={MBMV 2023 - 26. Workshop \"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023} }","apa":"Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., &#38; Sadiye, B. (2023). Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. <i>MBMV 2023 - 26. Workshop \"Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>. MBMV 2023, Freiburg, Freiburg."},"year":"2023","conference":{"end_date":"2023.03.24","location":"Freiburg","name":"MBMV 2023, Freiburg","start_date":"2023.03.23"},"title":"Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture","date_created":"2023-06-26T11:47:42Z","author":[{"full_name":"Luchterhandt, Lars","last_name":"Luchterhandt","first_name":"Lars"},{"first_name":"Tom","full_name":"Nellius, Tom","last_name":"Nellius"},{"last_name":"Beck","full_name":"Beck, Robert","first_name":"Robert"},{"full_name":"Dömer, Rainer","last_name":"Dömer","first_name":"Rainer"},{"first_name":"Pascal","id":"47367","full_name":"Kneuper, Pascal","last_name":"Kneuper"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye","first_name":"Babak"}],"publisher":"VDE Verlag","date_updated":"2025-02-24T10:41:01Z","status":"public","abstract":[{"lang":"eng","text":"RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple\r\nRISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.\r\nThis paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This\r\nwork also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with\r\ndifferent local address spaces."}],"publication":"MBMV 2023 - 26. Workshop \"Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg","type":"conference","language":[{"iso":"eng"}],"user_id":"16243","_id":"45775"},{"publication":"BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium","type":"conference_abstract","status":"public","department":[{"_id":"58"}],"user_id":"15931","_id":"47064","language":[{"iso":"eng"}],"related_material":{"link":[{"url":"https://bcicts.org/","relation":"contains"}]},"citation":{"bibtex":"@inproceedings{Iftekhar_Nagaraju_Kneuper_Sadiye_Müller_Scheytt_2023, title={A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology }, booktitle={BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}, author={Iftekhar, Mohammed and Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2023} }","short":"M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, J.C. Scheytt, in: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.","mla":"Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>, 2023.","apa":"Iftekhar, M., Nagaraju, H., Kneuper, P., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2023). A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology . <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>.","ama":"Iftekhar M, Nagaraju H, Kneuper P, Sadiye B, Müller W, Scheytt JC. A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology . In: <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>. ; 2023.","ieee":"M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt, “A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023.","chicago":"Iftekhar, Mohammed, Harshan Nagaraju, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” In <i>BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium</i>, 2023."},"year":"2023","author":[{"first_name":"Mohammed","id":"47944","full_name":"Iftekhar, Mohammed","last_name":"Iftekhar"},{"full_name":"Nagaraju, Harshan","last_name":"Nagaraju","first_name":"Harshan"},{"first_name":"Pascal","id":"47367","full_name":"Kneuper, Pascal","last_name":"Kneuper"},{"last_name":"Sadiye","full_name":"Sadiye, Babak","id":"93634","first_name":"Babak"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"J. Christoph","id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt"}],"date_created":"2023-09-14T11:30:36Z","date_updated":"2025-02-26T14:41:53Z","conference":{"start_date":"2023-10-15","location":"MONTEREY, CALIFORNIA, USA","end_date":"2023-10-18"},"title":"A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology "}]