---
_id: '62148'
author:
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm
FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Published
online 2025. doi:10.1109/TVLSI.2025.3625787'
apa: 'Sadiye, B., Iftekhar, M., Müller, W., & Scheytt, J. C. (2025). 60-Gb/s
1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems. https://doi.org/10.1109/TVLSI.2025.3625787'
bibtex: '@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer
in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis
and Design}, DOI={10.1109/TVLSI.2025.3625787},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE},
author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2025} }'
chicago: 'Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt.
“60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 2025. https://doi.org/10.1109/TVLSI.2025.3625787.'
ieee: 'B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer
in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis
and Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2025, doi: 10.1109/TVLSI.2025.3625787.'
mla: 'Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology
Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, IEEE, 2025, doi:10.1109/TVLSI.2025.3625787.'
short: B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems (2025).
date_created: 2025-11-10T08:31:47Z
date_updated: 2025-11-10T08:38:07Z
department:
- _id: '58'
doi: 10.1109/TVLSI.2025.3625787
language:
- iso: eng
project:
- _id: '325'
name: 'Scale4Edge: Skalierbare Infrastruktur für Edge-Computing'
publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
publication_identifier:
issn:
- 1063-8210
publication_status: published
publisher: IEEE
status: public
title: '60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design'
type: journal_article
user_id: '93634'
year: '2025'
...
---
_id: '62126'
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Iftekhar M, Sadiye B, Müller W, Scheytt JC. A 50 Gbps Reference-less NRZ Full-rate
Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology.
In: IEEE Nordic Circuits and Systems Conference (NORCAS). ; 2025. doi:10.1109/NorCAS66540.2025.11231203'
apa: Iftekhar, M., Sadiye, B., Müller, W., & Scheytt, J. C. (2025). A 50 Gbps
Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition
in 130 nm SiGe:C BiCMOS Technology. IEEE Nordic Circuits and Systems Conference
(NORCAS). IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia.
https://doi.org/10.1109/NorCAS66540.2025.11231203
bibtex: '@inproceedings{Iftekhar_Sadiye_Müller_Scheytt_2025, title={A 50 Gbps Reference-less
NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C
BiCMOS Technology}, DOI={10.1109/NorCAS66540.2025.11231203},
booktitle={IEEE Nordic Circuits and Systems Conference (NORCAS)}, author={Iftekhar,
Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025}
}'
chicago: Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt.
“A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency
Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In IEEE Nordic Circuits and
Systems Conference (NORCAS), 2025. https://doi.org/10.1109/NorCAS66540.2025.11231203.
ieee: 'M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less
NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C
BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference
(NORCAS), Riga, Latvia, 2025, doi: 10.1109/NorCAS66540.2025.11231203.'
mla: Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang
CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.”
IEEE Nordic Circuits and Systems Conference (NORCAS), 2025, doi:10.1109/NorCAS66540.2025.11231203.
short: 'M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits
and Systems Conference (NORCAS), 2025.'
conference:
end_date: 2025-10-29
location: Riga, Latvia
name: IEEE Nordic Circuits and Systems Conference (NORCAS)
start_date: 2025-10-28
date_created: 2025-11-07T10:41:45Z
date_updated: 2025-11-20T10:34:13Z
department:
- _id: '58'
doi: 10.1109/NorCAS66540.2025.11231203
language:
- iso: eng
project:
- _id: '325'
name: 'Scale4Edge: Skalierbare Infrastruktur für Edge-Computing'
publication: IEEE Nordic Circuits and Systems Conference (NORCAS)
status: public
title: A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency
Acquisition in 130 nm SiGe:C BiCMOS Technology
type: conference
user_id: '47944'
year: '2025'
...
---
_id: '62644'
author:
- first_name: Tobias
full_name: Schwabe, Tobias
id: '39217'
last_name: Schwabe
- first_name: Christian
full_name: Kress, Christian
id: '13256'
last_name: Kress
orcid: 0000-0002-4403-2237
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Stephan
full_name: Kruse, Stephan
id: '38254'
last_name: Kruse
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: Schwabe T, Kress C, Sadiye B, Kruse S, Scheytt JC. Analysis and Design of Forward
Biased Silicon Photonics Phase Shifter Equalizer Circuits. IEEE Access.
2025;13:192433-192450. doi:10.1109/ACCESS.2025.3629385
apa: Schwabe, T., Kress, C., Sadiye, B., Kruse, S., & Scheytt, J. C. (2025).
Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer
Circuits. IEEE Access, 13, 192433–192450. https://doi.org/10.1109/ACCESS.2025.3629385
bibtex: '@article{Schwabe_Kress_Sadiye_Kruse_Scheytt_2025, title={Analysis and Design
of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits}, volume={13},
DOI={10.1109/ACCESS.2025.3629385},
journal={IEEE Access}, author={Schwabe, Tobias and Kress, Christian and Sadiye,
Babak and Kruse, Stephan and Scheytt, J. Christoph}, year={2025}, pages={192433–192450}
}'
chicago: 'Schwabe, Tobias, Christian Kress, Babak Sadiye, Stephan Kruse, and J.
Christoph Scheytt. “Analysis and Design of Forward Biased Silicon Photonics Phase
Shifter Equalizer Circuits.” IEEE Access 13 (2025): 192433–50. https://doi.org/10.1109/ACCESS.2025.3629385.'
ieee: 'T. Schwabe, C. Kress, B. Sadiye, S. Kruse, and J. C. Scheytt, “Analysis and
Design of Forward Biased Silicon Photonics Phase Shifter Equalizer Circuits,”
IEEE Access, vol. 13, pp. 192433–192450, 2025, doi: 10.1109/ACCESS.2025.3629385.'
mla: Schwabe, Tobias, et al. “Analysis and Design of Forward Biased Silicon Photonics
Phase Shifter Equalizer Circuits.” IEEE Access, vol. 13, 2025, pp. 192433–50,
doi:10.1109/ACCESS.2025.3629385.
short: T. Schwabe, C. Kress, B. Sadiye, S. Kruse, J.C. Scheytt, IEEE Access 13 (2025)
192433–192450.
date_created: 2025-11-27T07:14:48Z
date_updated: 2025-11-27T07:16:06Z
department:
- _id: '58'
doi: 10.1109/ACCESS.2025.3629385
intvolume: ' 13'
keyword:
- Optical attenuators
- Equalizers
- Phase shifters
- Optical modulation
- Electro-optic modulators
- Optical amplifiers
- Circuits
- Silicon photonics
- Optical saturation
- Integrated circuit modeling
- Data communication
- equalization
- electro-optical transmitter
- silicon photonics
- phase shifter
- optical modulator
- free-carrier plasma dispersion effect
- driver architectures
- biasing schemes
language:
- iso: eng
page: 192433-192450
publication: IEEE Access
status: public
title: Analysis and Design of Forward Biased Silicon Photonics Phase Shifter Equalizer
Circuits
type: journal_article
user_id: '38254'
volume: 13
year: '2025'
...
---
_id: '53579'
author:
- first_name: Paul
full_name: Palomero Bernardo, Paul
last_name: Palomero Bernardo
- first_name: Patrick
full_name: Schmid, Patrick
last_name: Schmid
- first_name: Oliver
full_name: Bringmann, Oliver
last_name: Bringmann
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Eyck
full_name: Jentsch, Eyck
last_name: Jentsch
- first_name: Axel
full_name: Sauer, Axel
last_name: Sauer
- first_name: Ingo
full_name: Feldner, Ingo
last_name: Feldner
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
citation:
ama: 'Palomero Bernardo P, Schmid P, Bringmann O, et al. A Scalable RISC-V Hardware
Platform for Intelligent Sensor Processing. In: DATE 24 - Design Automation
and Test in Europe. ; 2024.'
apa: Palomero Bernardo, P., Schmid, P., Bringmann, O., Iftekhar, M., Sadiye, B.,
Müller, W., Koch, A., Jentsch, E., Sauer, A., Feldner, I., & Ecker, W. (2024).
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. DATE
24 - Design Automation and Test in Europe.
bibtex: '@inproceedings{Palomero Bernardo_Schmid_Bringmann_Iftekhar_Sadiye_Müller_Koch_Jentsch_Sauer_Feldner_et
al._2024, title={A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing},
booktitle={DATE 24 - Design Automation and Test in Europe}, author={Palomero Bernardo,
Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye,
Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel
and Feldner, Ingo and et al.}, year={2024} }'
chicago: Palomero Bernardo, Paul, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar,
Babak Sadiye, Wolfgang Müller, Andreas Koch, et al. “A Scalable RISC-V Hardware
Platform for Intelligent Sensor Processing.” In DATE 24 - Design Automation
and Test in Europe, 2024.
ieee: P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for
Intelligent Sensor Processing,” Valencia, Spain, 2024.
mla: Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent
Sensor Processing.” DATE 24 - Design Automation and Test in Europe, 2024.
short: 'P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W.
Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design
Automation and Test in Europe, 2024.'
conference:
location: Valencia, Spain
date_created: 2024-04-18T20:25:23Z
date_updated: 2024-04-18T20:25:29Z
department:
- _id: '58'
language:
- iso: eng
publication: DATE 24 - Design Automation and Test in Europe
status: public
title: A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
type: conference
user_id: '16243'
year: '2024'
...
---
_id: '45778'
abstract:
- lang: eng
text: "RISC-V has received worldwide acceptance in the industry and by the academic
community. As of today, multiple\r\nRISC-V applications and variants are under
investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors
up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid
of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel
grid-oriented network of processor cores with local memories.\r\nThis paper describes
a prototype design of the GPC platform for hardware implementation at Register-Transfer
Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories.
It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket
cores with RTL generation and a functional test using Verilator simulation. This\r\nwork
also includes the adaptation of the Chipyard software toolchain to extend the
compiler to multi-core grids with\r\ndifferent local address spaces."
author:
- first_name: Lars
full_name: Luchterhandt, Lars
last_name: Luchterhandt
- first_name: Tom
full_name: Nellius, Tom
last_name: Nellius
- first_name: Robert
full_name: Beck, Robert
last_name: Beck
- first_name: Rainer
full_name: Dömer, Rainer
last_name: Dömer
- first_name: Pascal
full_name: Kneuper, Pascal
id: '47367'
last_name: Kneuper
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
citation:
ama: 'Luchterhandt L, Nellius T, Beck R, et al. Implementation of Different Communication
Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. In: MBMV
2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
von Schaltungen Und Systemen“. VDE Verlag; 2024.'
apa: Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W.,
& Sadiye, B. (2024). Implementation of Different Communication Structures
for a Rocket Chip Based RISC-V Grid of Processing Cells. MBMV 2024 - 27. Workshop
Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
Und Systemen“. MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg.
bibtex: '@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2024,
title={Implementation of Different Communication Structures for a Rocket Chip
Based RISC-V Grid of Processing Cells}, booktitle={MBMV 2024 - 27. Workshop Methoden
und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
Systemen“}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom
and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and
Sadiye, Babak}, year={2024} }'
chicago: Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper,
Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication
Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In MBMV
2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
von Schaltungen Und Systemen“. VDE Verlag, 2024.
ieee: L. Luchterhandt et al., “Implementation of Different Communication
Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented
at the MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg, 2024.
mla: Luchterhandt, Lars, et al. “Implementation of Different Communication Structures
for a Rocket Chip Based RISC-V Grid of Processing Cells.” MBMV 2024 - 27. Workshop
Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
Und Systemen“, VDE Verlag, 2024.
short: 'L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B.
Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung
Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.'
conference:
end_date: 2023.03.24
location: Germany, Freiburg
name: 'MBMV 2023 - 26. Workshop, Freiburg, '
start_date: 2023.03.23
date_created: 2023-06-26T12:32:07Z
date_updated: 2025-02-24T10:40:29Z
department:
- _id: '58'
language:
- iso: eng
publication: MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung
und Verifikation von Schaltungen und Systemen“
publisher: VDE Verlag
status: public
title: Implementation of Different Communication Structures for a Rocket Chip Based
RISC-V Grid of Processing Cells
type: conference
user_id: '16243'
year: '2024'
...
---
_id: '45776'
author:
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
- first_name: Milos
full_name: Krstic, Milos
last_name: Krstic
- first_name: Markus
full_name: Ulbricht, Markus
last_name: Ulbricht
- first_name: Andreas
full_name: Mauderer, Andreas
last_name: Mauderer
- first_name: Eyck
full_name: Jentzsch, Eyck
last_name: Jentzsch
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Niklas
full_name: Bruns, Niklas
last_name: Bruns
- first_name: Rolf
full_name: Drechsler, Rolf
last_name: Drechsler
- first_name: Daniel
full_name: Müller-Gritschneder, Daniel
last_name: Müller-Gritschneder
- first_name: Jan
full_name: Schlamelcher, Jan
last_name: Schlamelcher
- first_name: Kim
full_name: Grüttner, Kim
last_name: Grüttner
- first_name: Jörg
full_name: Bormann, Jörg
last_name: Bormann
- first_name: Wolfgang
full_name: Kunz, Wolfgang
last_name: Kunz
- first_name: Reinhold
full_name: Heckmann, Reinhold
last_name: Heckmann
- first_name: Gerhard
full_name: Angst, Gerhard
last_name: Angst
- first_name: Ralf
full_name: Wimmer, Ralf
last_name: Wimmer
- first_name: Bernd
full_name: Becker, Bernd
last_name: Becker
- first_name: Tobias
full_name: Faller, Tobias
last_name: Faller
- first_name: Paul
full_name: Palomero Bernardo, Paul
last_name: Palomero Bernardo
- first_name: Oliver
full_name: Brinkmann, Oliver
last_name: Brinkmann
- first_name: Johannes
full_name: Partzsch, Johannes
last_name: Partzsch
- first_name: Christian
full_name: Mayr, Christian
last_name: Mayr
citation:
ama: 'Ecker W, Krstic M, Ulbricht M, et al. Scale4Edge – Scaling RISC-V for Edge
Applications. In: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.
; 2023.'
apa: Ecker, W., Krstic, M., Ulbricht, M., Mauderer, A., Jentzsch, E., Koch, A.,
Koppelmann, B., Müller, W., Sadiye, B., Bruns, N., Drechsler, R., Müller-Gritschneder,
D., Schlamelcher, J., Grüttner, K., Bormann, J., Kunz, W., Heckmann, R., Angst,
G., Wimmer, R., … Mayr, C. (2023). Scale4Edge – Scaling RISC-V for Edge Applications.
RISC-V Summit Europe 2023, Barcelona, Spain, June 2023. RISC-V Summit Europe
2023, Barcelona, Spain, June 2023., Barcelona, Spain,.
bibtex: '@inproceedings{Ecker_Krstic_Ulbricht_Mauderer_Jentzsch_Koch_Koppelmann_Müller_Sadiye_Bruns_et
al._2023, title={Scale4Edge – Scaling RISC-V for Edge Applications}, booktitle={RISC-V
Summit Europe 2023, Barcelona, Spain, June 2023.}, author={Ecker, Wolfgang and
Krstic, Milos and Ulbricht, Markus and Mauderer, Andreas and Jentzsch, Eyck and
Koch, Andreas and Koppelmann, Bastian and Müller, Wolfgang and Sadiye, Babak and
Bruns, Niklas and et al.}, year={2023} }'
chicago: Ecker, Wolfgang, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck
Jentzsch, Andreas Koch, Bastian Koppelmann, et al. “Scale4Edge – Scaling RISC-V
for Edge Applications.” In RISC-V Summit Europe 2023, Barcelona, Spain, June
2023., 2023.
ieee: W. Ecker et al., “Scale4Edge – Scaling RISC-V for Edge Applications,”
presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., Barcelona,
Spain, 2023.
mla: Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.”
RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
short: 'W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B.
Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder,
J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer,
B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr,
in: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.'
conference:
end_date: 2023.06.09
location: ' Barcelona, Spain,'
name: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.
start_date: 2023.06.05
date_created: 2023-06-26T12:16:36Z
date_updated: 2024-04-18T20:07:44Z
department:
- _id: '58'
language:
- iso: eng
publication: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.
related_material:
link:
- relation: slides
url: https://riscv-europe.org/media/proceedings/posters/2023-06-06-Wolfgang-ECKER-abstract.pdf
- relation: other
url: https://riscv-europe.org/
status: public
title: Scale4Edge – Scaling RISC-V for Edge Applications
type: conference
user_id: '16243'
year: '2023'
...
---
_id: '48961'
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Harshan
full_name: Gowda, Harshan
last_name: Gowda
- first_name: Pascal
full_name: Kneuper, Pascal
id: '47367'
last_name: Kneuper
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Iftekhar M, Gowda H, Kneuper P, Sadiye B, Müller W, Scheytt C. A 28-Gb/s 27.2mW
NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology.
In: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS). ; 2023. doi:10.1109/BCICTS54660.2023.10310954'
apa: Iftekhar, M., Gowda, H., Kneuper, P., Sadiye, B., Müller, W., & Scheytt,
C. (2023). A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in
22 nm FD-SOI CMOS Technology. 2023 IEEE BiCMOS and Compound Semiconductor Integrated
Circuits and Technology Symposium (BCICTS). 2023 IEEE BiCMOS und Compound
Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey,
CA, USA. https://doi.org/10.1109/BCICTS54660.2023.10310954
bibtex: '@inproceedings{Iftekhar_Gowda_Kneuper_Sadiye_Müller_Scheytt_2023, title={A
28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology}, DOI={10.1109/BCICTS54660.2023.10310954},
booktitle={2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and
Technology Symposium (BCICTS)}, author={Iftekhar, Mohammed and Gowda, Harshan
and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph},
year={2023} }'
chicago: Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang
Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology.” In 2023 IEEE BiCMOS and
Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS),
2023. https://doi.org/10.1109/BCICTS54660.2023.10310954.
ieee: 'M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt,
“A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor
Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023,
doi: 10.1109/BCICTS54660.2023.10310954.'
mla: Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology.” 2023 IEEE BiCMOS and Compound
Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023,
doi:10.1109/BCICTS54660.2023.10310954.
short: 'M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in:
2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS), 2023.'
conference:
end_date: 2023-10-18
location: Monterey, CA, USA
name: 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS)
start_date: 2023-10-16
date_created: 2023-11-16T11:04:41Z
date_updated: 2024-04-19T11:43:21Z
department:
- _id: '58'
doi: 10.1109/BCICTS54660.2023.10310954
language:
- iso: eng
publication: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS)
publication_identifier:
eisbn:
- 979-8-3503-0764-1
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/10310954
status: public
title: A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology
type: conference_abstract
user_id: '15931'
year: '2023'
...
---
_id: '45775'
abstract:
- lang: eng
text: "RISC-V has received worldwide acceptance in the industry and by the academic
community. As of today, multiple\r\nRISC-V applications and variants are under
investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors
up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid
of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel
grid-oriented network of processor cores with local memories.\r\nThis paper describes
a prototype design of the GPC platform for hardware implementation at Register-Transfer
Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories.
It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket
cores with RTL generation and a functional test using Verilator simulation. This\r\nwork
also includes the adaptation of the Chipyard software toolchain to extend the
compiler to multi-core grids with\r\ndifferent local address spaces."
author:
- first_name: Lars
full_name: Luchterhandt, Lars
last_name: Luchterhandt
- first_name: Tom
full_name: Nellius, Tom
last_name: Nellius
- first_name: Robert
full_name: Beck, Robert
last_name: Beck
- first_name: Rainer
full_name: Dömer, Rainer
last_name: Dömer
- first_name: Pascal
full_name: Kneuper, Pascal
id: '47367'
last_name: Kneuper
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
citation:
ama: 'Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation
of the RISC-V GPC Architecture. In: MBMV 2023 - 26. Workshop "Methoden Und
Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“,
MBMV 2023, Freiburg. VDE Verlag; 2023.'
apa: Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W.,
& Sadiye, B. (2023). Towards a Rocket Chip Based Implementation of the RISC-V
GPC Architecture. MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen
Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg.
MBMV 2023, Freiburg, Freiburg.
bibtex: '@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023,
title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture},
booktitle={MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung
und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE
Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer,
Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023}
}'
chicago: Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper,
Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation
of the RISC-V GPC Architecture.” In MBMV 2023 - 26. Workshop "Methoden Und
Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“,
MBMV 2023, Freiburg. VDE Verlag, 2023.
ieee: L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation
of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg,
2023.
mla: Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the
RISC-V GPC Architecture.” MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen
Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg,
VDE Verlag, 2023.
short: 'L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B.
Sadiye, in: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung
Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag,
2023.'
conference:
end_date: 2023.03.24
location: Freiburg
name: MBMV 2023, Freiburg
start_date: 2023.03.23
date_created: 2023-06-26T11:47:42Z
date_updated: 2025-02-24T10:41:01Z
language:
- iso: eng
publication: MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung
und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg
publisher: VDE Verlag
status: public
title: Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture
type: conference
user_id: '16243'
year: '2023'
...
---
_id: '47064'
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Harshan
full_name: Nagaraju, Harshan
last_name: Nagaraju
- first_name: Pascal
full_name: Kneuper, Pascal
id: '47367'
last_name: Kneuper
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Iftekhar M, Nagaraju H, Kneuper P, Sadiye B, Müller W, Scheytt JC. A 28-Gb/s
27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
. In: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium. ; 2023.'
apa: Iftekhar, M., Nagaraju, H., Kneuper, P., Sadiye, B., Müller, W., & Scheytt,
J. C. (2023). A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery
in 22 nm FD-SOI CMOS Technology . BCICTS 2023 IEEE BiCMOS and Compound Semiconductor
Integrated Circuits and Technology Symposium.
bibtex: '@inproceedings{Iftekhar_Nagaraju_Kneuper_Sadiye_Müller_Scheytt_2023, title={A
28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology }, booktitle={BCICTS 2023 IEEE BiCMOS and Compound Semiconductor
Integrated Circuits and Technology Symposium}, author={Iftekhar, Mohammed and
Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and
Scheytt, J. Christoph}, year={2023} }'
chicago: Iftekhar, Mohammed, Harshan Nagaraju, Pascal Kneuper, Babak Sadiye, Wolfgang
Müller, and J. Christoph Scheytt. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology .” In BCICTS 2023 IEEE BiCMOS
and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
ieee: M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt,
“A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023.
mla: Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology .” BCICTS 2023 IEEE BiCMOS
and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
short: 'M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, J.C. Scheytt,
in: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and
Technology Symposium, 2023.'
conference:
end_date: 2023-10-18
location: MONTEREY, CALIFORNIA, USA
start_date: 2023-10-15
date_created: 2023-09-14T11:30:36Z
date_updated: 2025-02-26T14:41:53Z
department:
- _id: '58'
language:
- iso: eng
publication: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium
related_material:
link:
- relation: contains
url: https://bcicts.org/
status: public
title: 'A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm
FD-SOI CMOS Technology '
type: conference_abstract
user_id: '15931'
year: '2023'
...