@misc{10714, author = {{Meißner, Roland}}, publisher = {{Universität Paderborn}}, title = {{{Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}}}, year = {{2015}}, } @misc{5927, author = {{N, N}}, publisher = {{Universität Paderborn}}, title = {{{Simultane bilaterale Verhandlungen - Zur Zusammenstellung eines Sortiments}}}, year = {{2015}}, } @misc{5928, author = {{N, N}}, publisher = {{Universität Paderborn}}, title = {{{Cournot-Nash-Bertrand Wettbewerb im serviceorientierten Internet}}}, year = {{2015}}, } @misc{5929, author = {{N, N}}, publisher = {{Universität Paderborn}}, title = {{{Multilaterale Verhandlungen aus Produzentensicht}}}, year = {{2015}}, } @misc{5925, author = {{N, N}}, publisher = {{Universität Paderborn}}, title = {{{Produktdifferenzierung und Verhandlungsposition im duopolistischen Wettbewerb}}}, year = {{2015}}, } @misc{5923, author = {{N, N}}, publisher = {{Universität Paderborn}}, title = {{{Aggregating Online Reputation Feedback}}}, year = {{2015}}, } @misc{5926, author = {{N, N}}, publisher = {{Universität Paderborn}}, title = {{{Verhandlungserfolg durch Reduktion von Verhandlungsasymmetrien - eine Analyse mit dem Adjusted-Winner-Verfahren}}}, year = {{2015}}, } @inproceedings{307, author = {{Herrmann, Philipp and Kundisch, Dennis and Zimmermann, Steffen and Nault, Barry}}, location = {{Philadelphia, USA}}, title = {{{Different Sources of the Variance of Online Consumer Ratings and their Impact on Price and Demand}}}, year = {{2015}}, } @article{296, abstract = {{FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.}}, author = {{Kenter, Tobias and Schmitz, Henning and Plessl, Christian}}, journal = {{International Journal of Reconfigurable Computing (IJRC)}}, publisher = {{Hindawi}}, title = {{{Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}}}, doi = {{10.1155/2015/859425}}, volume = {{2015}}, year = {{2015}}, } @inproceedings{303, abstract = {{This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.}}, author = {{Damschen, Marvin and Plessl, Christian}}, booktitle = {{Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}}, title = {{{Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}}}, year = {{2015}}, } @inproceedings{238, abstract = {{In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.}}, author = {{Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}}, booktitle = {{Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}}, pages = {{1078--1083}}, publisher = {{EDA Consortium / IEEE}}, title = {{{Transparent offloading of computational hotspots from binary code to Xeon Phi}}}, doi = {{10.7873/DATE.2015.1124}}, year = {{2015}}, } @article{2522, author = {{Brangewitz, Sonja and Gamp, Jan-Philip}}, issn = {{0938-2259}}, journal = {{Economic Theory}}, number = {{3}}, pages = {{529--554}}, publisher = {{Springer Nature}}, title = {{{Competitive outcomes and the inner core of NTU market games}}}, doi = {{10.1007/s00199-014-0846-7}}, volume = {{57}}, year = {{2014}}, } @inproceedings{329, abstract = {{Network emulations are widely used for testing novel network protocols and routing algorithms in realistic scenarios. Up to now, there is no emulation tool that is able to emulate large software-defined data center networks that consist of several thousand nodes. Mininet is the most common tool to emulate Software-Defined Networks of several hundred nodes. We extend Mininet to span an emulated network over several physical machines, making it possible to emulate networks of several thousand nodes on just a handful of physical machines. This enables us to emulate, e.g., large data center networks. To test this approach, we additionally introduce a traffic generator for data center traffic. Since there are no data center traffic traces publicly available we use the results of two recent traffic studies to create synthetic traffic. We show the design and discuss some challenges we had in building our traffic generator. As a showcase for our work we emulated a data center consisting of 3200 hosts on a cluster of only 12 physical machines. We show the resulting workloads and the trade-offs involved.}}, author = {{Wette, Philip and Dräxler, Martin and Schwabe, Arne and Wallaschek, Felix and Zahraee, Mohammad Hassan and Karl, Holger}}, booktitle = {{Proceedings of the 2014 IFIP Networking Conference (Networking 2014)}}, pages = {{1--9}}, title = {{{MaxiNet: Distributed Emulation of Software-Defined Networks}}}, doi = {{10.1109/IFIPNetworking.2014.6857078}}, year = {{2014}}, } @misc{330, author = {{Drigalsky, Liesa}}, publisher = {{Universität Paderborn}}, title = {{{Zur Ausbreitung und Behinderung von Epidemien - Eine Netzwerkanalyse}}}, year = {{2014}}, } @misc{331, author = {{Wu, Sen}}, publisher = {{Universität Paderborn}}, title = {{{Webcam application using virtual FPGA}}}, year = {{2014}}, } @misc{332, author = {{Lange, Maximilian}}, publisher = {{Universität Paderborn}}, title = {{{Was tun um Kunden von der Qualität seiner Produkte zu überzeugen - Möglichkeiten der Zertifizierung und von Reputationssystemen auf Onlinemärkten}}}, year = {{2014}}, } @misc{333, author = {{Osterbrink, Sebastian}}, publisher = {{Universität Paderborn}}, title = {{{Visualisierung von SMT-Solver-Ausgaben}}}, year = {{2014}}, } @misc{334, author = {{Wagener, Peter}}, publisher = {{Universität Paderborn}}, title = {{{Vertical Thread Migration in FPGA based Sound Localization}}}, year = {{2014}}, } @inproceedings{336, abstract = {{Today, service compositions often need to be assembled or changed on-the-fly, which leaves only little time for quality assurance. Moreover, quality assurance is complicated by service providers only giving information on their services in terms of domain specific concepts with only limited semantic meaning. In this paper, we propose a method to construct service compositions based on pre-verifiedtemplates. Templates, given as workflow descriptions, are typed over a (domain-independent) template ontology defining concepts and predicates. Templates are proven correct using an abstract semantics, leaving the specific meaning of ontology concepts open, however, only up to given ontology rules. Construction of service compositions amounts to instantiation of templates with domain-specific services.Correctness of an instantiation can then simply be checked by verifying that the domain ontology(a) adheres to the rules of the template ontology, and (b) fulfills the constraints of the employed template.}}, author = {{Walther, Sven and Wehrheim, Heike}}, booktitle = {{Proceedings of the 11th International Symposium on Formal Aspects of Component Software (FACS)}}, editor = {{Lanese, Ivan and Madelaine, Eric}}, pages = {{31--48}}, title = {{{Verified Service Compositions by Template-Based Construction}}}, doi = {{10.1007/978-3-319-15317-9_3}}, year = {{2014}}, } @misc{337, author = {{Berkemeier, Christopher}}, publisher = {{Universität Paderborn}}, title = {{{Verhandlungen vs Auktionen im Beschäftigungsmanagement}}}, year = {{2014}}, }