---
_id: '435'
abstract:
- lang: eng
text: We give a polynomial time algorithm to compute an optimal energy and fractional
weighted flow trade-off schedule for a speed-scalable processor with discrete
speeds.Our algorithm uses a geometric approach that is based on structural properties
obtained from a primal-dual formulation of the problem.
author:
- first_name: Antonios
full_name: Antoniadis, Antonios
last_name: Antoniadis
- first_name: Neal
full_name: Barcelo, Neal
last_name: Barcelo
- first_name: Mario
full_name: Consuegra, Mario
last_name: Consuegra
- first_name: Peer
full_name: Kling, Peer
last_name: Kling
- first_name: Michael
full_name: Nugent, Michael
last_name: Nugent
- first_name: Kirk
full_name: Pruhs, Kirk
last_name: Pruhs
- first_name: Michele
full_name: Scquizzato, Michele
last_name: Scquizzato
citation:
ama: 'Antoniadis A, Barcelo N, Consuegra M, et al. Efficient Computation of Optimal
Energy and Fractional Weighted Flow Trade-off Schedules. In: Proceedings of
the 31st Symposium on Theoretical Aspects of Computer Science (STACS). LIPIcs.
; 2014:63--74. doi:10.4230/LIPIcs.STACS.2014.63'
apa: Antoniadis, A., Barcelo, N., Consuegra, M., Kling, P., Nugent, M., Pruhs, K.,
& Scquizzato, M. (2014). Efficient Computation of Optimal Energy and Fractional
Weighted Flow Trade-off Schedules. In Proceedings of the 31st Symposium on
Theoretical Aspects of Computer Science (STACS) (pp. 63--74). https://doi.org/10.4230/LIPIcs.STACS.2014.63
bibtex: '@inproceedings{Antoniadis_Barcelo_Consuegra_Kling_Nugent_Pruhs_Scquizzato_2014,
series={LIPIcs}, title={Efficient Computation of Optimal Energy and Fractional
Weighted Flow Trade-off Schedules}, DOI={10.4230/LIPIcs.STACS.2014.63},
booktitle={Proceedings of the 31st Symposium on Theoretical Aspects of Computer
Science (STACS)}, author={Antoniadis, Antonios and Barcelo, Neal and Consuegra,
Mario and Kling, Peer and Nugent, Michael and Pruhs, Kirk and Scquizzato, Michele},
year={2014}, pages={63--74}, collection={LIPIcs} }'
chicago: Antoniadis, Antonios, Neal Barcelo, Mario Consuegra, Peer Kling, Michael
Nugent, Kirk Pruhs, and Michele Scquizzato. “Efficient Computation of Optimal
Energy and Fractional Weighted Flow Trade-off Schedules.” In Proceedings of
the 31st Symposium on Theoretical Aspects of Computer Science (STACS), 63--74.
LIPIcs, 2014. https://doi.org/10.4230/LIPIcs.STACS.2014.63.
ieee: A. Antoniadis et al., “Efficient Computation of Optimal Energy and
Fractional Weighted Flow Trade-off Schedules,” in Proceedings of the 31st Symposium
on Theoretical Aspects of Computer Science (STACS), 2014, pp. 63--74.
mla: Antoniadis, Antonios, et al. “Efficient Computation of Optimal Energy and Fractional
Weighted Flow Trade-off Schedules.” Proceedings of the 31st Symposium on Theoretical
Aspects of Computer Science (STACS), 2014, pp. 63--74, doi:10.4230/LIPIcs.STACS.2014.63.
short: 'A. Antoniadis, N. Barcelo, M. Consuegra, P. Kling, M. Nugent, K. Pruhs,
M. Scquizzato, in: Proceedings of the 31st Symposium on Theoretical Aspects of
Computer Science (STACS), 2014, pp. 63--74.'
date_created: 2017-10-17T12:42:16Z
date_updated: 2022-01-06T07:00:58Z
ddc:
- '040'
department:
- _id: '63'
doi: 10.4230/LIPIcs.STACS.2014.63
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:30:23Z
date_updated: 2018-03-16T11:30:23Z
file_id: '1354'
file_name: 435-Kling_C2_STACS2014.pdf
file_size: 525851
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:30:23Z
has_accepted_license: '1'
language:
- iso: eng
page: 63--74
project:
- _id: '1'
name: SFB 901
- _id: '16'
name: SFB 901 - Subprojekt C4
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 31st Symposium on Theoretical Aspects of Computer
Science (STACS)
series_title: LIPIcs
status: public
title: Efficient Computation of Optimal Energy and Fractional Weighted Flow Trade-off
Schedules
type: conference
user_id: '477'
year: '2014'
...
---
_id: '436'
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
citation:
ama: Damschen M. Easy-to-Use on-the-Fly Binary Program Acceleration on Many-Cores.
Universität Paderborn; 2014.
apa: Damschen, M. (2014). Easy-to-use on-the-fly binary program acceleration
on many-cores. Universität Paderborn.
bibtex: '@book{Damschen_2014, title={Easy-to-use on-the-fly binary program acceleration
on many-cores}, publisher={Universität Paderborn}, author={Damschen, Marvin},
year={2014} }'
chicago: Damschen, Marvin. Easy-to-Use on-the-Fly Binary Program Acceleration
on Many-Cores. Universität Paderborn, 2014.
ieee: M. Damschen, Easy-to-use on-the-fly binary program acceleration on many-cores.
Universität Paderborn, 2014.
mla: Damschen, Marvin. Easy-to-Use on-the-Fly Binary Program Acceleration on
Many-Cores. Universität Paderborn, 2014.
short: M. Damschen, Easy-to-Use on-the-Fly Binary Program Acceleration on Many-Cores,
Universität Paderborn, 2014.
date_created: 2017-10-17T12:42:16Z
date_updated: 2022-01-06T07:00:58Z
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
title: Easy-to-use on-the-fly binary program acceleration on many-cores
type: mastersthesis
user_id: '15504'
year: '2014'
...
---
_id: '437'
author:
- first_name: Vanessa
full_name: Wemhöner, Vanessa
last_name: Wemhöner
citation:
ama: Wemhöner V. Die ökonomischen Auswirkungen der Kronzeugenregelung am Beispiel
des Kaffeerösterkartells. Universität Paderborn; 2014.
apa: Wemhöner, V. (2014). Die ökonomischen Auswirkungen der Kronzeugenregelung
am Beispiel des Kaffeerösterkartells. Universität Paderborn.
bibtex: '@book{Wemhöner_2014, title={Die ökonomischen Auswirkungen der Kronzeugenregelung
am Beispiel des Kaffeerösterkartells}, publisher={Universität Paderborn}, author={Wemhöner,
Vanessa}, year={2014} }'
chicago: Wemhöner, Vanessa. Die ökonomischen Auswirkungen der Kronzeugenregelung
am Beispiel des Kaffeerösterkartells. Universität Paderborn, 2014.
ieee: V. Wemhöner, Die ökonomischen Auswirkungen der Kronzeugenregelung am Beispiel
des Kaffeerösterkartells. Universität Paderborn, 2014.
mla: Wemhöner, Vanessa. Die ökonomischen Auswirkungen der Kronzeugenregelung
am Beispiel des Kaffeerösterkartells. Universität Paderborn, 2014.
short: V. Wemhöner, Die ökonomischen Auswirkungen der Kronzeugenregelung am Beispiel
des Kaffeerösterkartells, Universität Paderborn, 2014.
date_created: 2017-10-17T12:42:17Z
date_updated: 2022-01-06T07:00:59Z
department:
- _id: '280'
language:
- iso: ger
project:
- _id: '1'
name: SFB 901
- _id: '7'
name: SFB 901 - Subprojekt A3
- _id: '2'
name: SFB 901 - Project Area A
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Burkhard
full_name: Hehenkamp, Burkhard
id: '37339'
last_name: Hehenkamp
title: Die ökonomischen Auswirkungen der Kronzeugenregelung am Beispiel des Kaffeerösterkartells
type: bachelorsthesis
user_id: '42447'
year: '2014'
...
---
_id: '438'
author:
- first_name: Andreas
full_name: Kokoschka, Andreas
last_name: Kokoschka
citation:
ama: Kokoschka A. Designing an Anonymous and Secure Reputation System Using a
Group Signature Variant. Universität Paderborn; 2014.
apa: Kokoschka, A. (2014). Designing an Anonymous and Secure Reputation System
Using a Group Signature Variant. Universität Paderborn.
bibtex: '@book{Kokoschka_2014, title={Designing an Anonymous and Secure Reputation
System Using a Group Signature Variant}, publisher={Universität Paderborn}, author={Kokoschka,
Andreas}, year={2014} }'
chicago: Kokoschka, Andreas. Designing an Anonymous and Secure Reputation System
Using a Group Signature Variant. Universität Paderborn, 2014.
ieee: A. Kokoschka, Designing an Anonymous and Secure Reputation System Using
a Group Signature Variant. Universität Paderborn, 2014.
mla: Kokoschka, Andreas. Designing an Anonymous and Secure Reputation System
Using a Group Signature Variant. Universität Paderborn, 2014.
short: A. Kokoschka, Designing an Anonymous and Secure Reputation System Using a
Group Signature Variant, Universität Paderborn, 2014.
date_created: 2017-10-17T12:42:17Z
date_updated: 2022-01-06T07:01:00Z
project:
- _id: '1'
name: SFB 901
- _id: '13'
name: SFB 901 - Subprojekt C1
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
title: Designing an Anonymous and Secure Reputation System Using a Group Signature
Variant
type: bachelorsthesis
user_id: '15504'
year: '2014'
...
---
_id: '440'
author:
- first_name: Daniel
full_name: Kaimann, Daniel
id: '18949'
last_name: Kaimann
citation:
ama: 'Kaimann D. Decision Making under Asymmetric Information in Markets for
Experience Goods: Empirical Evidence of Signaling Effects on Consumer Perceptions.
Universität Paderborn; 2014.'
apa: 'Kaimann, D. (2014). Decision Making under Asymmetric Information in Markets
for Experience Goods: Empirical Evidence of Signaling Effects on Consumer Perceptions.
Universität Paderborn.'
bibtex: '@book{Kaimann_2014, title={Decision Making under Asymmetric Information
in Markets for Experience Goods: Empirical Evidence of Signaling Effects on Consumer
Perceptions}, publisher={Universität Paderborn}, author={Kaimann, Daniel}, year={2014}
}'
chicago: 'Kaimann, Daniel. Decision Making under Asymmetric Information in Markets
for Experience Goods: Empirical Evidence of Signaling Effects on Consumer Perceptions.
Universität Paderborn, 2014.'
ieee: 'D. Kaimann, Decision Making under Asymmetric Information in Markets for
Experience Goods: Empirical Evidence of Signaling Effects on Consumer Perceptions.
Universität Paderborn, 2014.'
mla: 'Kaimann, Daniel. Decision Making under Asymmetric Information in Markets
for Experience Goods: Empirical Evidence of Signaling Effects on Consumer Perceptions.
Universität Paderborn, 2014.'
short: 'D. Kaimann, Decision Making under Asymmetric Information in Markets for
Experience Goods: Empirical Evidence of Signaling Effects on Consumer Perceptions,
Universität Paderborn, 2014.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2022-01-06T07:01:01Z
ddc:
- '330'
department:
- _id: '19'
- _id: '200'
- _id: '205'
- _id: '183'
file:
- access_level: closed
content_type: application/pdf
creator: dkaimann
date_created: 2018-11-08T09:29:04Z
date_updated: 2018-11-08T09:29:04Z
file_id: '5424'
file_name: Dissertation_2014_Kaimann.pdf
file_size: 531139
relation: main_file
success: 1
file_date_updated: 2018-11-08T09:29:04Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '7'
name: SFB 901 - Subprojekt A3
- _id: '2'
name: SFB 901 - Project Area A
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Claus-Jochen
full_name: Haake, Claus-Jochen
id: '20801'
last_name: Haake
- first_name: Bernd
full_name: Frick, Bernd
last_name: Frick
title: 'Decision Making under Asymmetric Information in Markets for Experience Goods:
Empirical Evidence of Signaling Effects on Consumer Perceptions'
type: dissertation
user_id: '477'
year: '2014'
...
---
_id: '5189'
author:
- first_name: Steven
full_name: Arzt, Steven
last_name: Arzt
- first_name: Siegfried
full_name: Rasthofer, Siegfried
last_name: Rasthofer
- first_name: Christian
full_name: Fritz, Christian
last_name: Fritz
- first_name: Eric
full_name: Bodden, Eric
id: '59256'
last_name: Bodden
orcid: 0000-0003-3470-3647
- first_name: Alexandre
full_name: Bartel, Alexandre
last_name: Bartel
- first_name: Jacques
full_name: Klein, Jacques
last_name: Klein
- first_name: Yves
full_name: Le Traon, Yves
last_name: Le Traon
- first_name: Damien
full_name: Octeau, Damien
last_name: Octeau
- first_name: Patrick
full_name: McDaniel, Patrick
last_name: McDaniel
citation:
ama: 'Arzt S, Rasthofer S, Fritz C, et al. FlowDroid: Precise Context, Flow, Field,
Object-sensitive and Lifecycle-aware Taint Analysis for Android Apps. In: Proceedings
of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation
- PLDI ’14. ACM Press; 2014. doi:10.1145/2594291.2594299'
apa: 'Arzt, S., Rasthofer, S., Fritz, C., Bodden, E., Bartel, A., Klein, J., … McDaniel,
P. (2014). FlowDroid: Precise Context, Flow, Field, Object-sensitive and Lifecycle-aware
Taint Analysis for Android Apps. In Proceedings of the 35th ACM SIGPLAN Conference
on Programming Language Design and Implementation - PLDI ’14. ACM Press. https://doi.org/10.1145/2594291.2594299'
bibtex: '@inproceedings{Arzt_Rasthofer_Fritz_Bodden_Bartel_Klein_Le Traon_Octeau_McDaniel_2014,
title={FlowDroid: Precise Context, Flow, Field, Object-sensitive and Lifecycle-aware
Taint Analysis for Android Apps}, DOI={10.1145/2594291.2594299},
booktitle={Proceedings of the 35th ACM SIGPLAN Conference on Programming Language
Design and Implementation - PLDI ’14}, publisher={ACM Press}, author={Arzt, Steven
and Rasthofer, Siegfried and Fritz, Christian and Bodden, Eric and Bartel, Alexandre
and Klein, Jacques and Le Traon, Yves and Octeau, Damien and McDaniel, Patrick},
year={2014} }'
chicago: 'Arzt, Steven, Siegfried Rasthofer, Christian Fritz, Eric Bodden, Alexandre
Bartel, Jacques Klein, Yves Le Traon, Damien Octeau, and Patrick McDaniel. “FlowDroid:
Precise Context, Flow, Field, Object-Sensitive and Lifecycle-Aware Taint Analysis
for Android Apps.” In Proceedings of the 35th ACM SIGPLAN Conference on Programming
Language Design and Implementation - PLDI ’14. ACM Press, 2014. https://doi.org/10.1145/2594291.2594299.'
ieee: 'S. Arzt et al., “FlowDroid: Precise Context, Flow, Field, Object-sensitive
and Lifecycle-aware Taint Analysis for Android Apps,” in Proceedings of the
35th ACM SIGPLAN Conference on Programming Language Design and Implementation
- PLDI ’14, 2014.'
mla: 'Arzt, Steven, et al. “FlowDroid: Precise Context, Flow, Field, Object-Sensitive
and Lifecycle-Aware Taint Analysis for Android Apps.” Proceedings of the 35th
ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI
’14, ACM Press, 2014, doi:10.1145/2594291.2594299.'
short: 'S. Arzt, S. Rasthofer, C. Fritz, E. Bodden, A. Bartel, J. Klein, Y. Le Traon,
D. Octeau, P. McDaniel, in: Proceedings of the 35th ACM SIGPLAN Conference on
Programming Language Design and Implementation - PLDI ’14, ACM Press, 2014.'
date_created: 2018-10-31T10:55:28Z
date_updated: 2022-01-06T07:01:42Z
ddc:
- '000'
department:
- _id: '76'
doi: 10.1145/2594291.2594299
extern: '1'
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T13:59:33Z
date_updated: 2018-11-02T13:59:33Z
file_id: '5258'
file_name: p259-arzt.pdf
file_size: 406920
relation: main_file
success: 1
file_date_updated: 2018-11-02T13:59:33Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- url: http://www.bodden.de/pubs/far+14flowdroid.pdf
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: Proceedings of the 35th ACM SIGPLAN Conference on Programming Language
Design and Implementation - PLDI '14
publication_identifier:
isbn:
- '9781450327848'
publication_status: published
publisher: ACM Press
status: public
title: 'FlowDroid: Precise Context, Flow, Field, Object-sensitive and Lifecycle-aware
Taint Analysis for Android Apps'
type: conference
user_id: '477'
year: '2014'
...
---
_id: '5190'
author:
- first_name: Steven
full_name: Arzt, Steven
last_name: Arzt
- first_name: Siegfried
full_name: Rasthofer, Siegfried
last_name: Rasthofer
- first_name: Enrico
full_name: Lovat, Enrico
last_name: Lovat
- first_name: Eric
full_name: Bodden, Eric
id: '59256'
last_name: Bodden
orcid: 0000-0003-3470-3647
citation:
ama: 'Arzt S, Rasthofer S, Lovat E, Bodden E. DroidForce: Enforcing Complex, Data-Centric,
System-Wide Policies in Android. In: International Conference on Availability,
Reliability and Security (ARES 2014). IEEE; 2014:40-49.'
apa: 'Arzt, S., Rasthofer, S., Lovat, E., & Bodden, E. (2014). DroidForce: Enforcing
Complex, Data-Centric, System-Wide Policies in Android. In International Conference
on Availability, Reliability and Security (ARES 2014) (pp. 40–49). IEEE.'
bibtex: '@inproceedings{Arzt_Rasthofer_Lovat_Bodden_2014, title={DroidForce: Enforcing
Complex, Data-Centric, System-Wide Policies in Android}, booktitle={International
Conference on Availability, Reliability and Security (ARES 2014)}, publisher={IEEE},
author={Arzt, Steven and Rasthofer, Siegfried and Lovat, Enrico and Bodden, Eric},
year={2014}, pages={40–49} }'
chicago: 'Arzt, Steven, Siegfried Rasthofer, Enrico Lovat, and Eric Bodden. “DroidForce:
Enforcing Complex, Data-Centric, System-Wide Policies in Android.” In International
Conference on Availability, Reliability and Security (ARES 2014), 40–49. IEEE,
2014.'
ieee: 'S. Arzt, S. Rasthofer, E. Lovat, and E. Bodden, “DroidForce: Enforcing Complex,
Data-Centric, System-Wide Policies in Android,” in International Conference
on Availability, Reliability and Security (ARES 2014), 2014, pp. 40–49.'
mla: 'Arzt, Steven, et al. “DroidForce: Enforcing Complex, Data-Centric, System-Wide
Policies in Android.” International Conference on Availability, Reliability
and Security (ARES 2014), IEEE, 2014, pp. 40–49.'
short: 'S. Arzt, S. Rasthofer, E. Lovat, E. Bodden, in: International Conference
on Availability, Reliability and Security (ARES 2014), IEEE, 2014, pp. 40–49.'
date_created: 2018-10-31T11:04:43Z
date_updated: 2022-01-06T07:01:43Z
ddc:
- '004'
department:
- _id: '76'
extern: '1'
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T13:21:13Z
date_updated: 2018-11-02T13:21:13Z
file_id: '5247'
file_name: ralb14droidforce.pdf
file_size: 661565
relation: main_file
file_date_updated: 2018-11-02T13:21:13Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- url: http://www.bodden.de/pubs/ralb14droidforce.pdf
page: 40-49
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: International Conference on Availability, Reliability and Security (ARES
2014)
publisher: IEEE
status: public
title: 'DroidForce: Enforcing Complex, Data-Centric, System-Wide Policies in Android'
type: conference
user_id: '477'
year: '2014'
...
---
_id: '335'
abstract:
- lang: eng
text: Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware
und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten
nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung
der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung
von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen
wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren
insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir
beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der
Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige
Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem
Computersystem besser in Hardware und welche besser in Software realisiert werden
sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen
Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat.
Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze
zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt,
um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten
Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software
beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen
eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption,
dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware
und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen
auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware
eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie
f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw.
l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer
flexiblen Software damit auf.
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software.
In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender
Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.”
Wilhelm Fink; 2014:123-144.'
apa: 'Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen
Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144).
Wilhelm Fink.'
bibtex: '@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe
des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen
Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen},
publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller,
Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144},
collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }'
chicago: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44.
Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink,
2014.'
ieee: 'M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware
und Software,” in Logiken strukturbildender Prozesse: Automatismen, J.
Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink,
2014, pp. 123–144.'
mla: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.'
short: 'M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn,
2014, pp. 123–144.'
date_created: 2017-10-17T12:41:57Z
date_updated: 2023-09-26T13:32:49Z
ddc:
- '040'
department:
- _id: '518'
- _id: '27'
- _id: '78'
editor:
- first_name: Jörn
full_name: Künsemöller, Jörn
last_name: Künsemöller
- first_name: Norber Otto
full_name: Eke, Norber Otto
last_name: Eke
- first_name: Lioba
full_name: Foit, Lioba
last_name: Foit
- first_name: Timo
full_name: Kaerlein, Timo
last_name: Kaerlein
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:29:58Z
date_updated: 2018-03-20T07:29:58Z
file_id: '1424'
file_name: 335-2014_plessl_automatismen.pdf
file_size: 2848154
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:29:58Z
has_accepted_license: '1'
language:
- iso: ger
page: 123-144
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: 'Logiken strukturbildender Prozesse: Automatismen'
publication_identifier:
isbn:
- 978-3-7705-5730-1
publication_status: published
publisher: Wilhelm Fink
quality_controlled: '1'
series_title: Schriftenreihe des Graduiertenkollegs "Automatismen"
status: public
title: Verschiebungen an der Grenze zwischen Hardware und Software
type: book_chapter
user_id: '15278'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '363'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, these temperature simulations
require a high computational effort if a detailed thermal model is used and their
accuracies are often unclear. In contrast to simulations, the use of synthetic
heat sources allows for experimental evaluation of temperature management methods.
In this paper we investigate the creation of significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments. To that end, we have developed seven different heat-generating
cores that use different subsets of FPGA resources. Our experimental results show
that, according to external temperature probes connected to the FPGA’s heat sink,
we can increase the temperature by an average of 81 !C. This corresponds to an
average increase of 156.3 !C as measured by the built-in thermal diodes of our
Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting
Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems.
2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven
Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors
and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001},
number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={911–919} }'
chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian
Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”
Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.'
ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors
and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.'
mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook
on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8,
Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and
Microsystems 38 (2014) 911–919.
date_created: 2017-10-17T12:42:02Z
date_updated: 2023-09-26T13:33:06Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2013.12.001
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:20:31Z
date_updated: 2018-03-20T07:20:31Z
file_id: '1408'
file_name: 363-plessl13_micpro.pdf
file_size: 1499996
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:20:31Z
has_accepted_license: '1'
intvolume: ' 38'
issue: 8, Part B
language:
- iso: eng
page: 911-919
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Microprocessors and Microsystems
publisher: Elsevier
quality_controlled: '1'
status: public
title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
type: journal_article
user_id: '15278'
volume: 38
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '365'
abstract:
- lang: eng
text: Self-aware computing is a paradigm for structuring and simplifying the design
and operation of computing systems that face unprecedented levels of system dynamics
and thus require novel forms of adaptivity. The generality of the paradigm makes
it applicable to many types of computing systems and, previously, researchers
started to introduce concepts of self-awareness to multicore architectures. In
our work we build on a recent reference architectural framework as a model for
self-aware computing and instantiate it for an FPGA-based heterogeneous multicore
running the ReconOS reconfigurable architecture and operating system. After presenting
the model for self-aware computing and ReconOS, we demonstrate with a case study
how a multicore application built on the principle of self-awareness, autonomously
adapts to changes in the workload and system state. Our work shows that the reference
architectural framework as a model for self-aware computing can be practically
applied and allows us to structure and simplify the design process, which is essential
for designing complex future computing systems.
article_number: '13'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for
Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable
Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions
on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13.
https://doi.org/10.1145/2617596
bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as
a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM
Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM},
author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian
and Platzner, Marco}, year={2014} }'
chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner.
“Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no.
2 (2014). https://doi.org/10.1145/2617596.
ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions
on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no.
13, 2014, doi: 10.1145/2617596.'
mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating
Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and
Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.
short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on
Reconfigurable Technology and Systems (TRETS) 7 (2014).
date_created: 2017-10-17T12:42:03Z
date_updated: 2023-09-26T13:33:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '78'
- _id: '518'
doi: 10.1145/2617596
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:19:19Z
date_updated: 2018-03-20T07:19:19Z
file_id: '1406'
file_name: 365-plessl14_trets_01.pdf
file_size: 916052
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:19:19Z
has_accepted_license: '1'
intvolume: ' 7'
issue: '2'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
publisher: ACM
quality_controlled: '1'
status: public
title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
type: journal_article
user_id: '15278'
volume: 7
year: '2014'
...
---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '2543'
author:
- first_name: Sonja
full_name: Brangewitz, Sonja
last_name: Brangewitz
- first_name: Jan-Philip
full_name: Gamp, Jan-Philip
last_name: Gamp
citation:
ama: Brangewitz S, Gamp J-P. Asymmetric Nash bargaining solutions and competitive
payoffs. Economics Letters. 2013;121(2):224-227. doi:10.1016/j.econlet.2013.08.013
apa: Brangewitz, S., & Gamp, J.-P. (2013). Asymmetric Nash bargaining solutions
and competitive payoffs. Economics Letters, 121(2), 224–227. https://doi.org/10.1016/j.econlet.2013.08.013
bibtex: '@article{Brangewitz_Gamp_2013, title={Asymmetric Nash bargaining solutions
and competitive payoffs}, volume={121}, DOI={10.1016/j.econlet.2013.08.013},
number={2}, journal={Economics Letters}, publisher={Elsevier}, author={Brangewitz,
Sonja and Gamp, Jan-Philip}, year={2013}, pages={224–227} }'
chicago: 'Brangewitz, Sonja, and Jan-Philip Gamp. “Asymmetric Nash Bargaining Solutions
and Competitive Payoffs.” Economics Letters 121, no. 2 (2013): 224–27.
https://doi.org/10.1016/j.econlet.2013.08.013.'
ieee: S. Brangewitz and J.-P. Gamp, “Asymmetric Nash bargaining solutions and competitive
payoffs,” Economics Letters, vol. 121, no. 2, pp. 224–227, 2013.
mla: Brangewitz, Sonja, and Jan-Philip Gamp. “Asymmetric Nash Bargaining Solutions
and Competitive Payoffs.” Economics Letters, vol. 121, no. 2, Elsevier,
2013, pp. 224–27, doi:10.1016/j.econlet.2013.08.013.
short: S. Brangewitz, J.-P. Gamp, Economics Letters 121 (2013) 224–227.
date_created: 2018-04-26T11:29:16Z
date_updated: 2022-01-06T06:57:04Z
ddc:
- '040'
department:
- _id: '205'
- _id: '475'
doi: 10.1016/j.econlet.2013.08.013
file:
- access_level: closed
content_type: application/pdf
creator: cjhaake
date_created: 2018-08-09T09:49:34Z
date_updated: 2018-08-09T09:49:34Z
file_id: '3869'
file_name: Asymmetric Nash bargaining solutions and competitive payoffs.pdf
file_size: 374977
relation: main_file
success: 1
file_date_updated: 2018-08-09T09:49:34Z
has_accepted_license: '1'
intvolume: ' 121'
issue: '2'
language:
- iso: eng
page: 224-227
project:
- _id: '1'
name: SFB 901
- _id: '2'
name: SFB 901 - Project Area A
- _id: '7'
name: SFB 901 - Subproject A3
publication: Economics Letters
publication_identifier:
issn:
- 0165-1765
publication_status: published
publisher: Elsevier
status: public
title: Asymmetric Nash bargaining solutions and competitive payoffs
type: journal_article
user_id: '65453'
volume: 121
year: '2013'
...
---
_id: '18000'
author:
- first_name: Fritz
full_name: Blumentritt, Fritz
last_name: Blumentritt
citation:
ama: Blumentritt F. Cliquenbildung in Verteilten Systemen. Universität Paderborn;
2013.
apa: Blumentritt, F. (2013). Cliquenbildung in verteilten Systemen. Universität
Paderborn.
bibtex: '@book{Blumentritt_2013, title={Cliquenbildung in verteilten Systemen},
publisher={Universität Paderborn}, author={Blumentritt, Fritz}, year={2013} }'
chicago: Blumentritt, Fritz. Cliquenbildung in Verteilten Systemen. Universität
Paderborn, 2013.
ieee: F. Blumentritt, Cliquenbildung in verteilten Systemen. Universität
Paderborn, 2013.
mla: Blumentritt, Fritz. Cliquenbildung in Verteilten Systemen. Universität
Paderborn, 2013.
short: F. Blumentritt, Cliquenbildung in Verteilten Systemen, Universität Paderborn,
2013.
date_created: 2020-08-17T08:14:17Z
date_updated: 2022-01-06T06:53:25Z
department:
- _id: '79'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '2'
name: SFB 901 - Project Area A
- _id: '5'
name: SFB 901 - Subproject A1
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
full_name: Scheideler, Christian
id: '20792'
last_name: Scheideler
title: Cliquenbildung in verteilten Systemen
type: bachelorsthesis
user_id: '477'
year: '2013'
...
---
_id: '469'
abstract:
- lang: eng
text: Runtime monitoring aims at ensuring program safety by monitoring the program's
behaviour during execution and taking appropriate action before a program violates
some property.Runtime monitoring is in particular important when an exhaustive
formal verification fails. While the approach allows for a safe execution of programs,
it may impose a significant runtime overhead.In this paper, we propose a novel
technique combining verification and monitoring which incurs no overhead during
runtime at all. The technique proceeds by using the inconclusive result of a verification
run as the basis for transforming the program into one where all potential points
of failure are replaced by HALT statements. The new program is safe by construction,
behaviourally equivalent to the original program (except for unsafe behaviour),and
has the same performance characteristics.
author:
- first_name: Daniel
full_name: Wonisch, Daniel
last_name: Wonisch
- first_name: Alexander
full_name: Schremmer, Alexander
last_name: Schremmer
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
citation:
ama: 'Wonisch D, Schremmer A, Wehrheim H. Zero Overhead Runtime Monitoring. In:
Proceedings of the 11th International Conference on Software Engineering and
Formal Methods (SEFM). LNCS. ; 2013:244-258. doi:10.1007/978-3-642-40561-7_17'
apa: Wonisch, D., Schremmer, A., & Wehrheim, H. (2013). Zero Overhead Runtime
Monitoring. In Proceedings of the 11th International Conference on Software
Engineering and Formal Methods (SEFM) (pp. 244–258). https://doi.org/10.1007/978-3-642-40561-7_17
bibtex: '@inproceedings{Wonisch_Schremmer_Wehrheim_2013, series={LNCS}, title={Zero
Overhead Runtime Monitoring}, DOI={10.1007/978-3-642-40561-7_17},
booktitle={Proceedings of the 11th International Conference on Software Engineering
and Formal Methods (SEFM)}, author={Wonisch, Daniel and Schremmer, Alexander and
Wehrheim, Heike}, year={2013}, pages={244–258}, collection={LNCS} }'
chicago: Wonisch, Daniel, Alexander Schremmer, and Heike Wehrheim. “Zero Overhead
Runtime Monitoring.” In Proceedings of the 11th International Conference on
Software Engineering and Formal Methods (SEFM), 244–58. LNCS, 2013. https://doi.org/10.1007/978-3-642-40561-7_17.
ieee: D. Wonisch, A. Schremmer, and H. Wehrheim, “Zero Overhead Runtime Monitoring,”
in Proceedings of the 11th International Conference on Software Engineering
and Formal Methods (SEFM), 2013, pp. 244–258.
mla: Wonisch, Daniel, et al. “Zero Overhead Runtime Monitoring.” Proceedings
of the 11th International Conference on Software Engineering and Formal Methods
(SEFM), 2013, pp. 244–58, doi:10.1007/978-3-642-40561-7_17.
short: 'D. Wonisch, A. Schremmer, H. Wehrheim, in: Proceedings of the 11th International
Conference on Software Engineering and Formal Methods (SEFM), 2013, pp. 244–258.'
date_created: 2017-10-17T12:42:23Z
date_updated: 2022-01-06T07:01:18Z
ddc:
- '040'
department:
- _id: '77'
doi: 10.1007/978-3-642-40561-7_17
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:18:41Z
date_updated: 2018-03-16T11:18:41Z
file_id: '1332'
file_name: 469-WSW2013-2.pdf
file_size: 394804
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:18:41Z
has_accepted_license: '1'
language:
- iso: eng
page: 244-258
project:
- _id: '1'
name: SFB 901
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '3'
name: SFB 901 - Project Area B
publication: Proceedings of the 11th International Conference on Software Engineering
and Formal Methods (SEFM)
series_title: LNCS
status: public
title: Zero Overhead Runtime Monitoring
type: conference
user_id: '477'
year: '2013'
...
---
_id: '470'
abstract:
- lang: eng
text: In OpenFlow [1], multiple switches share the same control plane which is centralized
atwhat is called the OpenFlow controller. A switch only consists of a forwarding
plane. Rules for forwarding individual packets (called ow entries in OpenFlow)
are pushed from the controller to the switches. In a network with a high arrival
rate of new ows, such as in a data center, the control trac between the switch
and controller can become very high. As a consequence, routing of new ows will
be slow. One way to reduce control trac is to use wildcarded ow entries. Wildcard
ow entries can be used to create default routes in the network. However, since
switches do not keep track of ows covered by a wildcard ow entry, the controller
no longer has knowledge about individual ows. To nd out about these individual
ows we propose an extension to the current OpenFlow standard to enable packet
sampling of wildcard ow entries.
author:
- first_name: Philip
full_name: Wette, Philip
last_name: Wette
- first_name: Holger
full_name: Karl, Holger
id: '126'
last_name: Karl
citation:
ama: 'Wette P, Karl H. Which Flows Are Hiding Behind My Wildcard Rule? Adding Packet
Sampling to OpenFlow. In: Proceedings of the ACM SIGCOMM ’13. Digital Library.
; 2013:541-542. doi:10.1145/2486001.2491710'
apa: Wette, P., & Karl, H. (2013). Which Flows Are Hiding Behind My Wildcard
Rule? Adding Packet Sampling to OpenFlow. In Proceedings of the ACM SIGCOMM
’13 (pp. 541–542). https://doi.org/10.1145/2486001.2491710
bibtex: '@inproceedings{Wette_Karl_2013, series={Digital Library}, title={Which
Flows Are Hiding Behind My Wildcard Rule? Adding Packet Sampling to OpenFlow},
DOI={10.1145/2486001.2491710},
booktitle={Proceedings of the ACM SIGCOMM ’13}, author={Wette, Philip and Karl,
Holger}, year={2013}, pages={541–542}, collection={Digital Library} }'
chicago: Wette, Philip, and Holger Karl. “Which Flows Are Hiding Behind My Wildcard
Rule? Adding Packet Sampling to OpenFlow.” In Proceedings of the ACM SIGCOMM
’13, 541–42. Digital Library, 2013. https://doi.org/10.1145/2486001.2491710.
ieee: P. Wette and H. Karl, “Which Flows Are Hiding Behind My Wildcard Rule? Adding
Packet Sampling to OpenFlow,” in Proceedings of the ACM SIGCOMM ’13, 2013,
pp. 541–542.
mla: Wette, Philip, and Holger Karl. “Which Flows Are Hiding Behind My Wildcard
Rule? Adding Packet Sampling to OpenFlow.” Proceedings of the ACM SIGCOMM ’13,
2013, pp. 541–42, doi:10.1145/2486001.2491710.
short: 'P. Wette, H. Karl, in: Proceedings of the ACM SIGCOMM ’13, 2013, pp. 541–542.'
date_created: 2017-10-17T12:42:23Z
date_updated: 2022-01-06T07:01:19Z
ddc:
- '040'
department:
- _id: '75'
doi: 10.1145/2486001.2491710
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:18:01Z
date_updated: 2018-03-16T11:18:01Z
file_id: '1331'
file_name: 470-p541-wette_01.pdf
file_size: 446835
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:18:01Z
has_accepted_license: '1'
page: 541-542
project:
- _id: '1'
name: SFB 901
- _id: '6'
name: SFB 901 - Subprojekt A2
- _id: '2'
name: SFB 901 - Project Area A
publication: Proceedings of the ACM SIGCOMM '13
series_title: Digital Library
status: public
title: Which Flows Are Hiding Behind My Wildcard Rule? Adding Packet Sampling to OpenFlow
type: conference
user_id: '15572'
year: '2013'
...
---
_id: '471'
author:
- first_name: Alina
full_name: Tezer, Alina
last_name: Tezer
citation:
ama: Tezer A. Verteilte Erstellung und Aktualisierung von Schlüsselservern in
identitätsbasierten Verschlüsselungssystemen. Universität Paderborn; 2013.
apa: Tezer, A. (2013). Verteilte Erstellung und Aktualisierung von Schlüsselservern
in identitätsbasierten Verschlüsselungssystemen. Universität Paderborn.
bibtex: '@book{Tezer_2013, title={Verteilte Erstellung und Aktualisierung von Schlüsselservern
in identitätsbasierten Verschlüsselungssystemen}, publisher={Universität Paderborn},
author={Tezer, Alina}, year={2013} }'
chicago: Tezer, Alina. Verteilte Erstellung und Aktualisierung von Schlüsselservern
in identitätsbasierten Verschlüsselungssystemen. Universität Paderborn, 2013.
ieee: A. Tezer, Verteilte Erstellung und Aktualisierung von Schlüsselservern
in identitätsbasierten Verschlüsselungssystemen. Universität Paderborn, 2013.
mla: Tezer, Alina. Verteilte Erstellung und Aktualisierung von Schlüsselservern
in identitätsbasierten Verschlüsselungssystemen. Universität Paderborn, 2013.
short: A. Tezer, Verteilte Erstellung und Aktualisierung von Schlüsselservern in
identitätsbasierten Verschlüsselungssystemen, Universität Paderborn, 2013.
date_created: 2017-10-17T12:42:23Z
date_updated: 2022-01-06T07:01:19Z
department:
- _id: '64'
language:
- iso: ger
project:
- _id: '1'
name: SFB 901
- _id: '13'
name: SFB 901 - Subprojekt C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '43'
name: Securing the Financial Cloud
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Johannes
full_name: Blömer, Johannes
id: '23'
last_name: Blömer
title: Verteilte Erstellung und Aktualisierung von Schlüsselservern in identitätsbasierten
Verschlüsselungssystemen
type: bachelorsthesis
user_id: '477'
year: '2013'
...