--- _id: '28199' author: - first_name: Felix full_name: Pauck, Felix id: '22398' last_name: Pauck - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Pauck F, Wehrheim H. Jicer: Simplifying Cooperative Android App Analysis Tasks. In: 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM). ; 2021. doi:10.1109/scam52516.2021.00031' apa: 'Pauck, F., & Wehrheim, H. (2021). Jicer: Simplifying Cooperative Android App Analysis Tasks. 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM). https://doi.org/10.1109/scam52516.2021.00031' bibtex: '@inproceedings{Pauck_Wehrheim_2021, title={Jicer: Simplifying Cooperative Android App Analysis Tasks}, DOI={10.1109/scam52516.2021.00031}, booktitle={2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM)}, author={Pauck, Felix and Wehrheim, Heike}, year={2021} }' chicago: 'Pauck, Felix, and Heike Wehrheim. “Jicer: Simplifying Cooperative Android App Analysis Tasks.” In 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM), 2021. https://doi.org/10.1109/scam52516.2021.00031.' ieee: 'F. Pauck and H. Wehrheim, “Jicer: Simplifying Cooperative Android App Analysis Tasks,” 2021, doi: 10.1109/scam52516.2021.00031.' mla: 'Pauck, Felix, and Heike Wehrheim. “Jicer: Simplifying Cooperative Android App Analysis Tasks.” 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM), 2021, doi:10.1109/scam52516.2021.00031.' short: 'F. Pauck, H. Wehrheim, in: 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM), 2021.' date_created: 2021-12-01T08:53:29Z date_updated: 2022-11-17T14:26:19Z department: - _id: '77' doi: 10.1109/scam52516.2021.00031 language: - iso: eng project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: 'SFB 901: SFB 901' - _id: '3' name: 'SFB 901 - B: SFB 901 - Project Area B' publication: 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM) publication_status: published status: public title: 'Jicer: Simplifying Cooperative Android App Analysis Tasks' type: conference user_id: '477' year: '2021' ... --- _id: '27841' abstract: - lang: eng text: Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques. author: - first_name: Marie-Christine full_name: Jakobs, Marie-Christine last_name: Jakobs - first_name: Felix full_name: Pauck, Felix id: '22398' last_name: Pauck - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema citation: ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. Published online 2021. doi:10.1109/ACCESS.2021.3131213 apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. https://doi.org/10.1109/ACCESS.2021.3131213 bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }' chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213. ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021, doi: 10.1109/ACCESS.2021.3131213.' mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213. short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021). date_created: 2021-11-25T14:12:22Z date_updated: 2023-01-18T08:34:50Z department: - _id: '78' doi: 10.1109/ACCESS.2021.3131213 funded_apc: '1' keyword: - Software Analysis - Abstract Interpretation - Custom Instruction - Hardware Verification language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publication: IEEE Access publication_status: published publisher: IEEE quality_controlled: '1' status: public title: Software/Hardware Co-Verification for Custom Instruction Set Processors type: journal_article user_id: '22398' year: '2021' ... --- _id: '21238' author: - first_name: Felix full_name: Pauck, Felix id: '22398' last_name: Pauck - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Pauck F, Wehrheim H. Cooperative Android App Analysis with CoDiDroid. In: Koziolek A, Schaefer I, Seidl C, eds. Software Engineering 2021. Gesellschaft für Informatik e.V.; 2021:83-84. doi:10.18420/SE2021_30 ' apa: Pauck, F., & Wehrheim, H. (2021). Cooperative Android App Analysis with CoDiDroid. In A. Koziolek, I. Schaefer, & C. Seidl (Eds.), Software Engineering 2021 (pp. 83–84). Gesellschaft für Informatik e.V. https://doi.org/10.18420/SE2021_30 bibtex: '@inproceedings{Pauck_Wehrheim_2021, place={Bonn}, title={Cooperative Android App Analysis with CoDiDroid}, DOI={10.18420/SE2021_30 }, booktitle={Software Engineering 2021}, publisher={Gesellschaft für Informatik e.V.}, author={Pauck, Felix and Wehrheim, Heike}, editor={Koziolek, Anne and Schaefer, Ina and Seidl, Christoph}, year={2021}, pages={83–84} }' chicago: 'Pauck, Felix, and Heike Wehrheim. “Cooperative Android App Analysis with CoDiDroid.” In Software Engineering 2021, edited by Anne Koziolek, Ina Schaefer, and Christoph Seidl, 83–84. Bonn: Gesellschaft für Informatik e.V., 2021. https://doi.org/10.18420/SE2021_30 .' ieee: 'F. Pauck and H. Wehrheim, “Cooperative Android App Analysis with CoDiDroid,” in Software Engineering 2021, 2021, pp. 83–84, doi: 10.18420/SE2021_30 .' mla: Pauck, Felix, and Heike Wehrheim. “Cooperative Android App Analysis with CoDiDroid.” Software Engineering 2021, edited by Anne Koziolek et al., Gesellschaft für Informatik e.V., 2021, pp. 83–84, doi:10.18420/SE2021_30 . short: 'F. Pauck, H. Wehrheim, in: A. Koziolek, I. Schaefer, C. Seidl (Eds.), Software Engineering 2021, Gesellschaft für Informatik e.V., Bonn, 2021, pp. 83–84.' date_created: 2021-02-16T09:28:49Z date_updated: 2023-01-18T08:35:20Z department: - _id: '77' doi: '10.18420/SE2021_30 ' editor: - first_name: Anne full_name: Koziolek, Anne last_name: Koziolek - first_name: Ina full_name: Schaefer, Ina last_name: Schaefer - first_name: Christoph full_name: Seidl, Christoph last_name: Seidl language: - iso: eng page: ' 83-84 ' place: Bonn project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publication: Software Engineering 2021 publication_status: published publisher: Gesellschaft für Informatik e.V. status: public title: Cooperative Android App Analysis with CoDiDroid type: conference user_id: '22398' year: '2021' ... --- _id: '29138' author: - first_name: Qazi Arbab full_name: Ahmed, Qazi Arbab id: '72764' last_name: Ahmed orcid: 0000-0002-1837-2254 citation: ama: 'Ahmed QA. Hardware Trojans in Reconfigurable Computing. In: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). ; 2021. doi:10.1109/vlsi-soc53125.2021.9606974' apa: Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). https://doi.org/10.1109/vlsi-soc53125.2021.9606974 bibtex: '@inproceedings{Ahmed_2021, title={Hardware Trojans in Reconfigurable Computing}, DOI={10.1109/vlsi-soc53125.2021.9606974}, booktitle={2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)}, author={Ahmed, Qazi Arbab}, year={2021} }' chicago: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” In 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021. https://doi.org/10.1109/vlsi-soc53125.2021.9606974. ieee: 'Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.' mla: Ahmed, Qazi Arbab. “Hardware Trojans in Reconfigurable Computing.” 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021, doi:10.1109/vlsi-soc53125.2021.9606974. short: 'Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021.' date_created: 2021-12-30T00:02:24Z date_updated: 2023-04-19T15:03:45Z department: - _id: '78' doi: 10.1109/vlsi-soc53125.2021.9606974 language: - iso: eng project: - _id: '3' name: 'SFB 901 - B: SFB 901 - Project Area B' - _id: '12' name: 'SFB 901 - B4: SFB 901 - Subproject B4' - _id: '1' name: 'SFB 901: SFB 901' publication: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC) publication_status: published status: public title: Hardware Trojans in Reconfigurable Computing type: conference user_id: '72764' year: '2021' ... --- _id: '20681' abstract: - lang: eng text: The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques. author: - first_name: Qazi Arbab full_name: Ahmed, Qazi Arbab id: '72764' last_name: Ahmed orcid: 0000-0002-1837-2254 - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:10.23919/DATE51398.2021.9474026' apa: 'Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026' bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble, France}, title={Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}, DOI={10.23919/DATE51398.2021.9474026}, booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021} }' chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Alpexpo | Grenoble, France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. https://doi.org/10.23919/DATE51398.2021.9474026.' ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.' mla: 'Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), 2021, doi:10.23919/DATE51398.2021.9474026.' short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.' conference: end_date: 2021-02-05 location: Alpexpo | Grenoble, France name: Design, Automation and Test in Europe Conference (DATE'21) start_date: 2021-02-01 date_created: 2020-12-07T14:03:00Z date_updated: 2023-05-11T09:16:34Z ddc: - '006' department: - _id: '78' doi: 10.23919/DATE51398.2021.9474026 file: - access_level: closed content_type: application/pdf creator: qazi date_created: 2023-05-11T09:16:15Z date_updated: 2023-05-11T09:16:15Z file_id: '44752' file_name: 1812.pdf file_size: 394011 relation: main_file success: 1 file_date_updated: 2023-05-11T09:16:15Z has_accepted_license: '1' language: - iso: eng main_file_link: - open_access: '1' oa: '1' place: Alpexpo | Grenoble, France project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publication: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) publication_identifier: eisbn: - 978-3-9819263-5-4 publication_status: published publisher: 2021 Design, Automation and Test in Europe Conference (DATE) status: public title: 'Malicious Routing: Circumventing Bitstream-level Verification for FPGAs' type: conference user_id: '72764' year: '2021' ... --- _id: '26406' author: - first_name: Philipp full_name: Schubert, Philipp id: '60543' last_name: Schubert orcid: 0000-0002-8674-1859 - first_name: Ben full_name: Hermann, Ben id: '66173' last_name: Hermann orcid: 0000-0001-9848-2017 - first_name: Eric full_name: Bodden, Eric id: '59256' last_name: Bodden orcid: 0000-0003-3470-3647 - first_name: Richard full_name: Leer, Richard last_name: Leer citation: ama: 'Schubert P, Hermann B, Bodden E, Leer R. Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++. In: SCAM ’21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track). ; 2021.' apa: 'Schubert, P., Hermann, B., Bodden, E., & Leer, R. (2021). Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++. SCAM ’21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track).' bibtex: '@inproceedings{Schubert_Hermann_Bodden_Leer_2021, title={Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++}, booktitle={SCAM ’21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track)}, author={Schubert, Philipp and Hermann, Ben and Bodden, Eric and Leer, Richard}, year={2021} }' chicago: 'Schubert, Philipp, Ben Hermann, Eric Bodden, and Richard Leer. “Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++.” In SCAM ’21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track), 2021.' ieee: 'P. Schubert, B. Hermann, E. Bodden, and R. Leer, “Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++,” 2021.' mla: 'Schubert, Philipp, et al. “Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++.” SCAM ’21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track), 2021.' short: 'P. Schubert, B. Hermann, E. Bodden, R. Leer, in: SCAM ’21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track), 2021.' date_created: 2021-10-18T12:52:12Z date_updated: 2023-06-15T08:39:55Z department: - _id: '76' language: - iso: eng project: - _id: '3' name: 'SFB 901 - B: SFB 901 - Project Area B' - _id: '12' name: 'SFB 901 - B4: SFB 901 - Subproject B4' - _id: '1' grant_number: '160364472' name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ' publication: 'SCAM ''21: IEEE International Working Conference on Source Code Analysis and Manipulation (Engineering Track)' status: public title: 'Into the Woods: Experiences from Building a Dataflow Analysis Framework for C/C++' type: conference user_id: '15249' year: '2021' ... --- _id: '26405' author: - first_name: Philipp full_name: Schubert, Philipp id: '60543' last_name: Schubert orcid: 0000-0002-8674-1859 - first_name: Florian full_name: Sattler, Florian last_name: Sattler - first_name: Fabian Benedikt full_name: Schiebel, Fabian Benedikt id: '55745' last_name: Schiebel orcid: 0009-0008-6867-9802 - first_name: Ben full_name: Hermann, Ben id: '66173' last_name: Hermann orcid: 0000-0001-9848-2017 - first_name: Eric full_name: Bodden, Eric id: '59256' last_name: Bodden orcid: 0000-0003-3470-3647 citation: ama: 'Schubert P, Sattler F, Schiebel FB, Hermann B, Bodden E. Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++. In: 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM). ; 2021.' apa: Schubert, P., Sattler, F., Schiebel, F. B., Hermann, B., & Bodden, E. (2021). Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++. 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM). bibtex: '@inproceedings{Schubert_Sattler_Schiebel_Hermann_Bodden_2021, title={Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++}, booktitle={2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM)}, author={Schubert, Philipp and Sattler, Florian and Schiebel, Fabian Benedikt and Hermann, Ben and Bodden, Eric}, year={2021} }' chicago: Schubert, Philipp, Florian Sattler, Fabian Benedikt Schiebel, Ben Hermann, and Eric Bodden. “Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++.” In 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM), 2021. ieee: P. Schubert, F. Sattler, F. B. Schiebel, B. Hermann, and E. Bodden, “Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++,” 2021. mla: Schubert, Philipp, et al. “Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++.” 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM), 2021. short: 'P. Schubert, F. Sattler, F.B. Schiebel, B. Hermann, E. Bodden, in: 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM), 2021.' date_created: 2021-10-18T12:50:35Z date_updated: 2025-12-04T10:43:01Z department: - _id: '76' language: - iso: eng project: - _id: '12' name: 'SFB 901 - B4: SFB 901 - Subproject B4' - _id: '3' name: 'SFB 901 - B: SFB 901 - Project Area B' - _id: '1' name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ' publication: 2021 IEEE 21st International Working Conference on Source Code Analysis and Manipulation (SCAM) status: public title: Modeling the Effects of Global Variables in Data-Flow Analysis for C/C++ type: conference user_id: '15249' year: '2021' ... --- _id: '17358' abstract: - lang: eng text: 'Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.' article_type: original author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061 apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061 bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems 28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.' ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020. mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061. short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088. date_created: 2020-07-06T11:21:30Z date_updated: 2022-01-06T06:53:09Z department: - _id: '78' doi: 10.1109/TVLSI.2020.3008061 funded_apc: '1' intvolume: ' 28' issue: '9' keyword: - Approximate circuit synthesis - approximate computing - error metrics - formal verification - proof-carrying hardware language: - iso: eng page: 2084 - 2088 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publication: IEEE Transactions On Very Large Scale Integration Systems publication_identifier: eissn: - 1557-9999 issn: - 1063-8210 publication_status: published publisher: IEEE quality_controlled: '1' status: public title: Proof-carrying Approximate Circuits type: journal_article user_id: '49051' volume: 28 year: '2020' ... --- _id: '20712' author: - first_name: Philipp full_name: Schubert, Philipp id: '60543' last_name: Schubert orcid: 0000-0002-8674-1859 - first_name: Eric full_name: Bodden, Eric id: '59256' last_name: Bodden orcid: 0000-0003-3470-3647 - first_name: Ben full_name: Hermann, Ben id: '66173' last_name: Hermann orcid: 0000-0001-9848-2017 citation: ama: Schubert P, Bodden E, Hermann B. Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries.; 2020. apa: Schubert, P., Bodden, E., & Hermann, B. (2020). Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries. bibtex: '@book{Schubert_Bodden_Hermann_2020, title={Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries}, author={Schubert, Philipp and Bodden, Eric and Hermann, Ben}, year={2020} }' chicago: Schubert, Philipp, Eric Bodden, and Ben Hermann. Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries, 2020. ieee: P. Schubert, E. Bodden, and B. Hermann, Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries. 2020. mla: Schubert, Philipp, et al. Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries. 2020. short: P. Schubert, E. Bodden, B. Hermann, Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries, 2020. date_created: 2020-12-14T07:44:11Z date_updated: 2022-01-06T06:54:34Z ddc: - '000' department: - _id: '76' file: - access_level: closed content_type: application/pdf creator: pdschbrt date_created: 2020-12-14T07:39:07Z date_updated: 2020-12-14T07:39:07Z file_id: '20713' file_name: main.pdf file_size: 683576 relation: main_file success: 1 file_date_updated: 2020-12-14T07:39:07Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 status: public title: Accelerating Static Call-Graph, Points-to and Data-Flow Analysis Through Persisted Summaries type: report user_id: '477' year: '2020' ... --- _id: '20748' abstract: - lang: eng text: "On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies.\r\nIn the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. \r\nIn this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification.\r\nIn our experimental results, we present the runtimes of our approach." author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020). apa: Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020). bibtex: '@article{Witschen_Wiersema_Platzner, title={Search Space Characterization for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }' chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020), n.d. ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). . mla: Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020). short: L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing (AxC 2020) (n.d.). date_created: 2020-12-15T15:13:49Z date_updated: 2022-01-06T06:54:35Z ddc: - '000' department: - _id: '78' file: - access_level: closed content_type: application/pdf creator: witschen date_created: 2020-12-15T15:11:06Z date_updated: 2020-12-15T15:11:06Z file_id: '20749' file_name: witschen20_axc.pdf file_size: 250870 relation: main_file success: 1 file_date_updated: 2020-12-15T15:11:06Z has_accepted_license: '1' language: - iso: eng page: '2' project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publication: Fifth Workshop on Approximate Computing (AxC 2020) publication_status: accepted status: public title: Search Space Characterization for AxC Synthesis type: preprint user_id: '3118' year: '2020' ... --- _id: '16725' author: - first_name: Cedric full_name: Richter, Cedric id: '50003' last_name: Richter - first_name: Eyke full_name: Hüllermeier, Eyke id: '48129' last_name: Hüllermeier - first_name: Marie-Christine full_name: Jakobs, Marie-Christine last_name: Jakobs - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: Richter C, Hüllermeier E, Jakobs M-C, Wehrheim H. Algorithm Selection for Software Validation Based on Graph Kernels. Journal of Automated Software Engineering. apa: Richter, C., Hüllermeier, E., Jakobs, M.-C., & Wehrheim, H. (n.d.). Algorithm Selection for Software Validation Based on Graph Kernels. Journal of Automated Software Engineering. bibtex: '@article{Richter_Hüllermeier_Jakobs_Wehrheim, title={Algorithm Selection for Software Validation Based on Graph Kernels}, journal={Journal of Automated Software Engineering}, publisher={Springer}, author={Richter, Cedric and Hüllermeier, Eyke and Jakobs, Marie-Christine and Wehrheim, Heike} }' chicago: Richter, Cedric, Eyke Hüllermeier, Marie-Christine Jakobs, and Heike Wehrheim. “Algorithm Selection for Software Validation Based on Graph Kernels.” Journal of Automated Software Engineering, n.d. ieee: C. Richter, E. Hüllermeier, M.-C. Jakobs, and H. Wehrheim, “Algorithm Selection for Software Validation Based on Graph Kernels,” Journal of Automated Software Engineering. mla: Richter, Cedric, et al. “Algorithm Selection for Software Validation Based on Graph Kernels.” Journal of Automated Software Engineering, Springer. short: C. Richter, E. Hüllermeier, M.-C. Jakobs, H. Wehrheim, Journal of Automated Software Engineering (n.d.). date_created: 2020-04-19T14:08:06Z date_updated: 2022-01-06T06:52:55Z department: - _id: '7' - _id: '77' - _id: '355' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '11' name: SFB 901 - Subproject B3 - _id: '12' name: SFB 901 - Subproject B4 publication: Journal of Automated Software Engineering publication_status: accepted publisher: Springer status: public title: Algorithm Selection for Software Validation Based on Graph Kernels type: journal_article user_id: '477' year: '2020' ... --- _id: '13770' author: - first_name: Holger full_name: Karl, Holger id: '126' last_name: Karl - first_name: Dennis full_name: Kundisch, Dennis id: '21117' last_name: Kundisch - first_name: Friedhelm full_name: Meyer auf der Heide, Friedhelm id: '15523' last_name: Meyer auf der Heide - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Karl H, Kundisch D, Meyer auf der Heide F, Wehrheim H. A Case for a New IT Ecosystem: On-The-Fly Computing. Business & Information Systems Engineering. 2020;62(6):467-481. doi:10.1007/s12599-019-00627-x' apa: 'Karl, H., Kundisch, D., Meyer auf der Heide, F., & Wehrheim, H. (2020). A Case for a New IT Ecosystem: On-The-Fly Computing. Business & Information Systems Engineering, 62(6), 467–481. https://doi.org/10.1007/s12599-019-00627-x' bibtex: '@article{Karl_Kundisch_Meyer auf der Heide_Wehrheim_2020, title={A Case for a New IT Ecosystem: On-The-Fly Computing}, volume={62}, DOI={10.1007/s12599-019-00627-x}, number={6}, journal={Business & Information Systems Engineering}, publisher={Springer}, author={Karl, Holger and Kundisch, Dennis and Meyer auf der Heide, Friedhelm and Wehrheim, Heike}, year={2020}, pages={467–481} }' chicago: 'Karl, Holger, Dennis Kundisch, Friedhelm Meyer auf der Heide, and Heike Wehrheim. “A Case for a New IT Ecosystem: On-The-Fly Computing.” Business & Information Systems Engineering 62, no. 6 (2020): 467–81. https://doi.org/10.1007/s12599-019-00627-x.' ieee: 'H. Karl, D. Kundisch, F. Meyer auf der Heide, and H. Wehrheim, “A Case for a New IT Ecosystem: On-The-Fly Computing,” Business & Information Systems Engineering, vol. 62, no. 6, pp. 467–481, 2020, doi: 10.1007/s12599-019-00627-x.' mla: 'Karl, Holger, et al. “A Case for a New IT Ecosystem: On-The-Fly Computing.” Business & Information Systems Engineering, vol. 62, no. 6, Springer, 2020, pp. 467–81, doi:10.1007/s12599-019-00627-x.' short: H. Karl, D. Kundisch, F. Meyer auf der Heide, H. Wehrheim, Business & Information Systems Engineering 62 (2020) 467–481. date_created: 2019-10-10T13:41:06Z date_updated: 2022-12-02T09:27:17Z ddc: - '004' department: - _id: '276' - _id: '75' - _id: '63' - _id: '77' doi: 10.1007/s12599-019-00627-x file: - access_level: closed content_type: application/pdf creator: ups date_created: 2019-12-12T10:24:47Z date_updated: 2019-12-12T10:24:47Z file_id: '15311' file_name: Karl2019_Article_ACaseForANewITEcosystemOn-The-.pdf file_size: 454532 relation: main_file success: 1 file_date_updated: 2019-12-12T10:24:47Z has_accepted_license: '1' intvolume: ' 62' issue: '6' language: - iso: eng page: 467-481 project: - _id: '1' name: SFB 901 - _id: '2' name: SFB 901 - Project Area A - _id: '3' name: SFB 901 - Project Area B - _id: '4' name: SFB 901 - Project Area C - _id: '82' name: SFB 901 - Project Area T - _id: '5' name: SFB 901 - Subproject A1 - _id: '6' name: SFB 901 - Subproject A2 - _id: '7' name: SFB 901 - Subproject A3 - _id: '8' name: SFB 901 - Subproject A4 - _id: '9' name: SFB 901 - Subproject B1 - _id: '10' name: SFB 901 - Subproject B2 - _id: '11' name: SFB 901 - Subproject B3 - _id: '12' name: SFB 901 - Subproject B4 - _id: '13' name: SFB 901 - Subproject C1 - _id: '14' name: SFB 901 - Subproject C2 - _id: '15' name: SFB 901 - Subproject C3 - _id: '16' name: SFB 901 - Subproject C4 - _id: '17' name: SFB 901 - Subproject C5 - _id: '83' name: SFB 901 -Subproject T1 - _id: '84' name: SFB 901 -Subproject T2 - _id: '107' name: SFB 901 -Subproject T3 - _id: '158' name: 'SFB 901 - T4: SFB 901 -Subproject T4' publication: Business & Information Systems Engineering publication_status: published publisher: Springer status: public title: 'A Case for a New IT Ecosystem: On-The-Fly Computing' type: journal_article user_id: '477' volume: 62 year: '2020' ... --- _id: '3585' abstract: - lang: eng text: Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Muhammad full_name: Awais, Muhammad id: '64665' last_name: Awais orcid: https://orcid.org/0000-0003-4148-2969 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003' apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003' bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, volume={99}, DOI={10.1016/j.microrel.2019.04.003}, journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019): 277–90. https://doi.org/10.1016/j.microrel.2019.04.003.' ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.' mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.' short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability 99 (2019) 277–290. date_created: 2018-07-20T14:08:49Z date_updated: 2022-01-06T06:59:25Z department: - _id: '78' doi: 10.1016/j.microrel.2019.04.003 intvolume: ' 99' keyword: - Approximate Computing - Framework - Pareto Front - Accuracy language: - iso: eng page: 277-290 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Microelectronics Reliability publication_identifier: issn: - 0026-2714 publication_status: published publisher: Elsevier status: public title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation' type: journal_article user_id: '49051' volume: 99 year: '2019' ... --- _id: '7623' author: - first_name: Shikun full_name: Zhang, Shikun last_name: Zhang citation: ama: Zhang S. Combining Android Apps for Analysis Purposes. Universität Paderborn; 2019. apa: Zhang, S. (2019). Combining Android Apps for Analysis Purposes. Universität Paderborn. bibtex: '@book{Zhang_2019, title={Combining Android Apps for Analysis Purposes}, publisher={Universität Paderborn}, author={Zhang, Shikun}, year={2019} }' chicago: Zhang, Shikun. Combining Android Apps for Analysis Purposes. Universität Paderborn, 2019. ieee: S. Zhang, Combining Android Apps for Analysis Purposes. Universität Paderborn, 2019. mla: Zhang, Shikun. Combining Android Apps for Analysis Purposes. Universität Paderborn, 2019. short: S. Zhang, Combining Android Apps for Analysis Purposes, Universität Paderborn, 2019. date_created: 2019-02-12T06:13:43Z date_updated: 2022-01-06T07:03:41Z department: - _id: '77' language: - iso: eng page: '64' project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publisher: Universität Paderborn status: public supervisor: - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim title: Combining Android Apps for Analysis Purposes type: mastersthesis user_id: '477' year: '2019' ... --- _id: '7628' author: - first_name: Nils full_name: Selbach, Nils last_name: Selbach citation: ama: Selbach N. Modeling Crypto API Usages in OpenSSL’s EVP Library. Universität Paderborn; 2019. apa: Selbach, N. (2019). Modeling Crypto API usages in OpenSSL’s EVP library. Universität Paderborn. bibtex: '@book{Selbach_2019, title={Modeling Crypto API usages in OpenSSL’s EVP library}, publisher={Universität Paderborn}, author={Selbach, Nils}, year={2019} }' chicago: Selbach, Nils. Modeling Crypto API Usages in OpenSSL’s EVP Library. Universität Paderborn, 2019. ieee: N. Selbach, Modeling Crypto API usages in OpenSSL’s EVP library. Universität Paderborn, 2019. mla: Selbach, Nils. Modeling Crypto API Usages in OpenSSL’s EVP Library. Universität Paderborn, 2019. short: N. Selbach, Modeling Crypto API Usages in OpenSSL’s EVP Library, Universität Paderborn, 2019. date_created: 2019-02-12T07:28:12Z date_updated: 2022-01-06T07:03:41Z department: - _id: '76' language: - iso: eng project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publisher: Universität Paderborn status: public supervisor: - first_name: Philipp full_name: Schubert, Philipp id: '60543' last_name: Schubert orcid: 0000-0002-8674-1859 title: Modeling Crypto API usages in OpenSSL's EVP library type: bachelorsthesis user_id: '477' year: '2019' ... --- _id: '15838' abstract: - lang: eng text: In the field of software analysis a trade-off between scalability and accuracy always exists. In this respect, Android app analysis is no exception, in particular, analyzing large or many apps can be challenging. Dealing with many small apps is a typical challenge when facing micro-benchmarks such as DROIDBENCH or ICC-BENCH. These particular benchmarks are not only used for the evaluation of novel tools but also in continuous integration pipelines of existing mature tools to maintain and guarantee a certain quality-level. Considering this latter usage it becomes very important to be able to achieve benchmark results as fast as possible. Hence, benchmarks have to be optimized for this purpose. One approach to do so is app merging. We implemented the Android Merge Tool (AMT) following this approach and show that its novel aspects can be used to produce scaled up and accurate benchmarks. For such benchmarks Android app analysis tools do not suffer from the scalability-accuracy trade-off anymore. We show this throughout detailed experiments on DROIDBENCH employing three different analysis tools (AMANDROID, ICCTA, FLOWDROID). Benchmark execution times are largely reduced without losing benchmark accuracy. Moreover, we argue why AMT is an advantageous successor of the state-of-the-art app merging tool (APKCOMBINER) in analysis lift-up scenarios. author: - first_name: Felix full_name: Pauck, Felix id: '22398' last_name: Pauck - first_name: Shikun full_name: Zhang, Shikun last_name: Zhang citation: ama: 'Pauck F, Zhang S. Android App Merging for Benchmark Speed-Up and Analysis Lift-Up. In: 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW). ; 2019. doi:10.1109/asew.2019.00019' apa: Pauck, F., & Zhang, S. (2019). Android App Merging for Benchmark Speed-Up and Analysis Lift-Up. In 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW). https://doi.org/10.1109/asew.2019.00019 bibtex: '@inproceedings{Pauck_Zhang_2019, title={Android App Merging for Benchmark Speed-Up and Analysis Lift-Up}, DOI={10.1109/asew.2019.00019}, booktitle={2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW)}, author={Pauck, Felix and Zhang, Shikun}, year={2019} }' chicago: Pauck, Felix, and Shikun Zhang. “Android App Merging for Benchmark Speed-Up and Analysis Lift-Up.” In 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW), 2019. https://doi.org/10.1109/asew.2019.00019. ieee: F. Pauck and S. Zhang, “Android App Merging for Benchmark Speed-Up and Analysis Lift-Up,” in 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW), 2019. mla: Pauck, Felix, and Shikun Zhang. “Android App Merging for Benchmark Speed-Up and Analysis Lift-Up.” 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW), 2019, doi:10.1109/asew.2019.00019. short: 'F. Pauck, S. Zhang, in: 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW), 2019.' date_created: 2020-02-06T17:06:51Z date_updated: 2022-01-06T06:52:38Z ddc: - '004' department: - _id: '77' doi: 10.1109/asew.2019.00019 file: - access_level: closed content_type: application/pdf creator: fpauck date_created: 2020-02-06T17:09:45Z date_updated: 2020-02-06T17:09:45Z file_id: '15839' file_name: AMT_final.pdf file_size: 644517 relation: main_file file_date_updated: 2020-02-06T17:09:45Z has_accepted_license: '1' keyword: - Program Analysis - Android App Analysis - Taint Analysis - App Merging - Benchmark language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publication: 2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW) publication_identifier: isbn: - '9781728141367' publication_status: published status: public title: Android App Merging for Benchmark Speed-Up and Analysis Lift-Up type: conference user_id: '477' year: '2019' ... --- _id: '15920' abstract: - lang: eng text: "Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs.\r\nThis master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis." author: - first_name: Monica full_name: Keerthipati, Monica last_name: Keerthipati citation: ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn; 2019. apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn. bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati, Monica}, year={2019} }' chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019. ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019. mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019. short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking, Universität Paderborn, 2019. date_created: 2020-02-17T12:03:40Z date_updated: 2022-01-06T06:52:41Z department: - _id: '78' language: - iso: eng project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publisher: Universität Paderborn status: public supervisor: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking type: mastersthesis user_id: '477' year: '2019' ... --- _id: '14896' author: - first_name: Andreas full_name: Dann, Andreas last_name: Dann - first_name: Ben full_name: Hermann, Ben id: '66173' last_name: Hermann orcid: 0000-0001-9848-2017 - first_name: Eric full_name: Bodden, Eric id: '59256' last_name: Bodden orcid: 0000-0003-3470-3647 citation: ama: 'Dann A, Hermann B, Bodden E. ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules. IEEE Transactions on Software Engineering. Published online 2019:1-1. doi:10.1109/tse.2019.2931331' apa: 'Dann, A., Hermann, B., & Bodden, E. (2019). ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules. IEEE Transactions on Software Engineering, 1–1. https://doi.org/10.1109/tse.2019.2931331' bibtex: '@article{Dann_Hermann_Bodden_2019, title={ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules}, DOI={10.1109/tse.2019.2931331}, journal={IEEE Transactions on Software Engineering}, author={Dann, Andreas and Hermann, Ben and Bodden, Eric}, year={2019}, pages={1–1} }' chicago: 'Dann, Andreas, Ben Hermann, and Eric Bodden. “ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules.” IEEE Transactions on Software Engineering, 2019, 1–1. https://doi.org/10.1109/tse.2019.2931331.' ieee: 'A. Dann, B. Hermann, and E. Bodden, “ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules,” IEEE Transactions on Software Engineering, pp. 1–1, 2019, doi: 10.1109/tse.2019.2931331.' mla: 'Dann, Andreas, et al. “ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules.” IEEE Transactions on Software Engineering, 2019, pp. 1–1, doi:10.1109/tse.2019.2931331.' short: A. Dann, B. Hermann, E. Bodden, IEEE Transactions on Software Engineering (2019) 1–1. date_created: 2019-11-12T12:20:56Z date_updated: 2022-01-06T06:52:10Z department: - _id: '76' - _id: '34' - _id: '26' doi: 10.1109/tse.2019.2931331 language: - iso: eng page: 1-1 project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publication: IEEE Transactions on Software Engineering publication_identifier: issn: - 0098-5589 - 1939-3520 - 2326-3881 publication_status: published status: public title: 'ModGuard: Identifying Integrity &Confidentiality Violations in Java Modules' type: journal_article user_id: '5786' year: '2019' ... --- _id: '10093' author: - first_name: Dirk full_name: Beyer, Dirk last_name: Beyer - first_name: Marie-Christine full_name: Jakobs, Marie-Christine last_name: Jakobs - first_name: Thomas full_name: Lemberger, Thomas last_name: Lemberger - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Beyer D, Jakobs M-C, Lemberger T, Wehrheim H. Combining Verifiers in Conditional Model Checking via Reducers. In: Becker S, Bogicevic I, Herzwurm G, Wagner S, eds. Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019. Vol P-292. LNI. GI; 2019:151--152. doi:10.18420/se2019-46' apa: Beyer, D., Jakobs, M.-C., Lemberger, T., & Wehrheim, H. (2019). Combining Verifiers in Conditional Model Checking via Reducers. In S. Becker, I. Bogicevic, G. Herzwurm, & S. Wagner (Eds.), Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019 (Vol. P-292, pp. 151--152). GI. https://doi.org/10.18420/se2019-46 bibtex: '@inproceedings{Beyer_Jakobs_Lemberger_Wehrheim_2019, series={LNI}, title={Combining Verifiers in Conditional Model Checking via Reducers}, volume={P-292}, DOI={10.18420/se2019-46}, booktitle={Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019}, publisher={GI}, author={Beyer, Dirk and Jakobs, Marie-Christine and Lemberger, Thomas and Wehrheim, Heike}, editor={Becker, Steffen and Bogicevic, Ivan and Herzwurm, Georg and Wagner, StefanEditors}, year={2019}, pages={151--152}, collection={LNI} }' chicago: Beyer, Dirk, Marie-Christine Jakobs, Thomas Lemberger, and Heike Wehrheim. “Combining Verifiers in Conditional Model Checking via Reducers.” In Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019, edited by Steffen Becker, Ivan Bogicevic, Georg Herzwurm, and Stefan Wagner, P-292:151--152. LNI. GI, 2019. https://doi.org/10.18420/se2019-46. ieee: D. Beyer, M.-C. Jakobs, T. Lemberger, and H. Wehrheim, “Combining Verifiers in Conditional Model Checking via Reducers,” in Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019, 2019, vol. P-292, pp. 151--152. mla: Beyer, Dirk, et al. “Combining Verifiers in Conditional Model Checking via Reducers.” Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019, edited by Steffen Becker et al., vol. P-292, GI, 2019, pp. 151--152, doi:10.18420/se2019-46. short: 'D. Beyer, M.-C. Jakobs, T. Lemberger, H. Wehrheim, in: S. Becker, I. Bogicevic, G. Herzwurm, S. Wagner (Eds.), Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019, GI, 2019, pp. 151--152.' date_created: 2019-06-03T08:08:39Z date_updated: 2022-01-06T06:50:28Z ddc: - '004' department: - _id: '77' doi: 10.18420/se2019-46 editor: - first_name: Steffen full_name: Becker, Steffen last_name: Becker - first_name: Ivan full_name: Bogicevic, Ivan last_name: Bogicevic - first_name: Georg full_name: Herzwurm, Georg last_name: Herzwurm - first_name: Stefan full_name: Wagner, Stefan last_name: Wagner file: - access_level: closed content_type: application/pdf creator: ups date_created: 2019-08-26T09:31:55Z date_updated: 2019-08-26T09:31:55Z file_id: '12956' file_name: 46.pdf file_size: 472426 relation: main_file success: 1 file_date_updated: 2019-08-26T09:31:55Z has_accepted_license: '1' language: - iso: eng page: 151--152 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication: Software Engineering and Software Management (SE/SWM 2019), Stuttgart, Germany, February 18-22, 2019 publisher: GI series_title: LNI status: public title: Combining Verifiers in Conditional Model Checking via Reducers type: conference user_id: '477' volume: P-292 year: '2019' ... --- _id: '10095' author: - first_name: Cedric full_name: Richter, Cedric id: '50003' last_name: Richter - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Richter C, Wehrheim H. PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution). In: Beyer D, Huisman M, Kordon F, Steffen B, eds. Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III}. Vol 11429. Lecture Notes in Computer Science. Springer; 2019:229-233. doi:10.1007/978-3-030-17502-3_19' apa: 'Richter, C., & Wehrheim, H. (2019). PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution). In D. Beyer, M. Huisman, F. Kordon, & B. Steffen (Eds.), Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III} (Vol. 11429, pp. 229–233). Springer. https://doi.org/10.1007/978-3-030-17502-3_19' bibtex: '@inproceedings{Richter_Wehrheim_2019, series={Lecture Notes in Computer Science}, title={PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution)}, volume={11429}, DOI={10.1007/978-3-030-17502-3_19}, booktitle={Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III}}, publisher={Springer}, author={Richter, Cedric and Wehrheim, Heike}, editor={Beyer, Dirk and Huisman, Marieke and Kordon, Fabrice and Steffen, BernhardEditors}, year={2019}, pages={229–233}, collection={Lecture Notes in Computer Science} }' chicago: 'Richter, Cedric, and Heike Wehrheim. “PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution).” In Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III}, edited by Dirk Beyer, Marieke Huisman, Fabrice Kordon, and Bernhard Steffen, 11429:229–33. Lecture Notes in Computer Science. Springer, 2019. https://doi.org/10.1007/978-3-030-17502-3_19.' ieee: 'C. Richter and H. Wehrheim, “PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution),” in Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III}, 2019, vol. 11429, pp. 229–233.' mla: 'Richter, Cedric, and Heike Wehrheim. “PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution).” Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III}, edited by Dirk Beyer et al., vol. 11429, Springer, 2019, pp. 229–33, doi:10.1007/978-3-030-17502-3_19.' short: 'C. Richter, H. Wehrheim, in: D. Beyer, M. Huisman, F. Kordon, B. Steffen (Eds.), Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III}, Springer, 2019, pp. 229–233.' date_created: 2019-06-03T08:12:55Z date_updated: 2022-01-06T06:50:29Z ddc: - '004' department: - _id: '77' doi: 10.1007/978-3-030-17502-3_19 editor: - first_name: Dirk full_name: Beyer, Dirk last_name: Beyer - first_name: Marieke full_name: Huisman, Marieke last_name: Huisman - first_name: Fabrice full_name: Kordon, Fabrice last_name: Kordon - first_name: Bernhard full_name: Steffen, Bernhard last_name: Steffen file: - access_level: closed content_type: application/pdf creator: ups date_created: 2019-08-26T11:01:00Z date_updated: 2019-08-26T11:01:00Z file_id: '12961' file_name: PeSCo.pdf file_size: 254772 relation: main_file success: 1 file_date_updated: 2019-08-26T11:01:00Z has_accepted_license: '1' intvolume: ' 11429' language: - iso: eng page: 229-233 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication: Tools and Algorithms for the Construction and Analysis of Systems - 25 Years of {TACAS:} TOOLympics, Held as Part of {ETAPS} 2019, Prague, Czech Republic, April 6-11, 2019, Proceedings, Part {III} publisher: Springer series_title: Lecture Notes in Computer Science status: public title: 'PeSCo: Predicting Sequential Combinations of Verifiers - (Competition Contribution)' type: conference user_id: '29719' volume: 11429 year: '2019' ...