@phdthesis{47837,
  author       = {{Hansmeier, Tim}},
  title        = {{{XCS for Self-awareness in Autonomous Computing Systems}}},
  year         = {{2023}},
}

@inbook{45893,
  author       = {{Hansmeier, Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco and Plessl, Christian}},
  booktitle    = {{On-The-Fly Computing -- Individualized IT-services in dynamic markets}},
  editor       = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}},
  pages        = {{165--182}},
  publisher    = {{Heinz Nixdorf Institut, Universität Paderborn}},
  title        = {{{Compute Centers I: Heterogeneous Execution Environments}}},
  doi          = {{10.5281/zenodo.8068642}},
  volume       = {{412}},
  year         = {{2023}},
}

@misc{42839,
  author       = {{Mehlich, Florian}},
  publisher    = {{Paderborn University}},
  title        = {{{An Evaluation of XCS on the OpenAI Gym}}},
  year         = {{2023}},
}

@book{45863,
  abstract     = {{In the proposal for our CRC in 2011, we formulated a vision of markets for
IT services that describes an approach to the provision of such services
that was novel at that time and, to a large extent, remains so today:
„Our vision of on-the-fly computing is that of IT services individually and
automatically configured and brought to execution from flexibly combinable
services traded on markets. At the same time, we aim at organizing
markets whose participants maintain a lively market of services through
appropriate entrepreneurial actions.“
Over the last 12 years, we have developed methods and techniques to
address problems critical to the convenient, efficient, and secure use of
on-the-fly computing. Among other things, we have made the description
of services more convenient by allowing natural language input,
increased the quality of configured services through (natural language)
interaction and more efficient configuration processes and analysis
procedures, made the quality of (the products of) providers in the
marketplace transparent through reputation systems, and increased the
resource efficiency of execution through reconfigurable heterogeneous
computing nodes and an integrated treatment of service description and
configuration. We have also developed network infrastructures that have
a high degree of adaptivity, scalability, efficiency, and reliability, and
provide cryptographic guarantees of anonymity and security for market
participants and their products and services.
To demonstrate the pervasiveness of the OTF computing approach, we
have implemented a proof-of-concept for OTF computing that can run
typical scenarios of an OTF market. We illustrated the approach using
a cutting-edge application scenario – automated machine learning (AutoML).
Finally, we have been pushing our work for the perpetuation of
On-The-Fly Computing beyond the SFB and sharing the expertise gained
in the SFB in events with industry partners as well as transfer projects.
This work required a broad spectrum of expertise. Computer scientists
and economists with research interests such as computer networks and
distributed algorithms, security and cryptography, software engineering
and verification, configuration and machine learning, computer engineering
and HPC, microeconomics and game theory, business informatics
and management have successfully collaborated here.}},
  author       = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}},
  pages        = {{247}},
  publisher    = {{Heinz Nixdorf Institut, Universität Paderborn}},
  title        = {{{On-The-Fly Computing -- Individualized IT-services in dynamic markets}}},
  doi          = {{10.17619/UNIPB/1-1797}},
  volume       = {{412}},
  year         = {{2023}},
}

@article{38041,
  abstract     = {{<jats:p>While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, and not least, benchmarks and reference implementations towards sustained HPC usage of these devices. As in the early days of GPUs in HPC, for workloads that can reasonably be decoupled into loosely coupled working sets, multi-accelerator support can be achieved by using standard communication interfaces like MPI on the host side. However, for performance and productivity, some applications can profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities here when extending the dataflow characteristics to their communication interfaces.</jats:p>
          <jats:p>In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA support and three missing benchmarks that particularly characterize or stress inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented for current boards with Intel and Xilinx FPGAs, we established a baseline for multi-FPGA performance. Additionally, for the communication-centric benchmarks, we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched inter-FPGA network that is currently only available for one of the boards. The evaluation with parallel execution on up to 26 FPGA boards makes use of one of the largest academic FPGA installations.</jats:p>}},
  author       = {{Meyer, Marius and Kenter, Tobias and Plessl, Christian}},
  issn         = {{1936-7406}},
  journal      = {{ACM Transactions on Reconfigurable Technology and Systems}},
  keywords     = {{General Computer Science}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks}}},
  doi          = {{10.1145/3576200}},
  year         = {{2023}},
}

@inproceedings{30971,
  author       = {{Hansmeier, Tim and Platzner, Marco}},
  booktitle    = {{Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}},
  isbn         = {{9783031024610}},
  issn         = {{0302-9743}},
  location     = {{Madrid}},
  pages        = {{386--401}},
  publisher    = {{Springer International Publishing}},
  title        = {{{Integrating Safety Guarantees into the Learning Classifier System XCS}}},
  doi          = {{10.1007/978-3-031-02462-7_25}},
  volume       = {{13224}},
  year         = {{2022}},
}

@inproceedings{33253,
  author       = {{Hansmeier, Tim and Brede, Mathis and Platzner, Marco}},
  booktitle    = {{GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  location     = {{Boston, MA, USA}},
  pages        = {{2071--2079}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}}},
  doi          = {{10.1145/3520304.3533977}},
  year         = {{2022}},
}

@phdthesis{29769,
  abstract     = {{Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.}},
  author       = {{Ahmed, Qazi Arbab}},
  keywords     = {{FPGA Security, Hardware Trojans, Bitstream-level Trojans, Bitstream Verification}},
  publisher    = {{ Paderborn University, Paderborn, Germany}},
  title        = {{{Hardware Trojans in Reconfigurable Computing}}},
  doi          = {{10.17619/UNIPB/1-1271}},
  year         = {{2022}},
}

@misc{29151,
  abstract     = {{Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique.}},
  author       = {{Kashikar, Chinmay}},
  publisher    = {{Paderborn University}},
  title        = {{{A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes}}},
  year         = {{2021}},
}

@misc{22483,
  abstract     = {{This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems.}},
  author       = {{Brede, Mathis}},
  publisher    = {{Paderborn University}},
  title        = {{{Implementation and Profiling of XCS in the Context of Embedded Systems}}},
  year         = {{2021}},
}

@inproceedings{29137,
  author       = {{Hansmeier, Tim}},
  booktitle    = {{HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}},
  location     = {{Online}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}}},
  doi          = {{10.1145/3468044.3468055}},
  year         = {{2021}},
}

@inproceedings{21813,
  author       = {{Hansmeier, Tim and Platzner, Marco}},
  booktitle    = {{GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  isbn         = {{978-1-4503-8351-6}},
  location     = {{Lille, France}},
  pages        = {{1639–1647}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS}}},
  doi          = {{10.1145/3449726.3463159}},
  year         = {{2021}},
}

@inproceedings{17063,
  author       = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  isbn         = {{978-1-4503-7127-8}},
  location     = {{Cancún, Mexico}},
  pages        = {{1756--1764}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{An Adaption Mechanism for the Error Threshold of XCSF}}},
  doi          = {{10.1145/3377929.3398106}},
  year         = {{2020}},
}

@inproceedings{16363,
  author       = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  isbn         = {{978-1-4503-7127-8}},
  location     = {{Cancún, Mexico}},
  pages        = {{125--126}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}}},
  doi          = {{10.1145/3377929.3389968}},
  year         = {{2020}},
}

@article{13770,
  author       = {{Karl, Holger and Kundisch, Dennis and Meyer auf der Heide, Friedhelm and Wehrheim, Heike}},
  journal      = {{Business & Information Systems Engineering}},
  number       = {{6}},
  pages        = {{467--481}},
  publisher    = {{Springer}},
  title        = {{{A Case for a New IT Ecosystem: On-The-Fly Computing}}},
  doi          = {{10.1007/s12599-019-00627-x}},
  volume       = {{62}},
  year         = {{2020}},
}

@article{7689,
  author       = {{Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}},
  journal      = {{ACM Trans. Archit. Code Optim. (TACO)}},
  keywords     = {{htrop}},
  number       = {{2}},
  pages        = {{14:1–14:26}},
  publisher    = {{ACM}},
  title        = {{{Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}}},
  doi          = {{10.1145/3319423}},
  volume       = {{16}},
  year         = {{2019}},
}

@phdthesis{14849,
  author       = {{Vaz, Gavin Francis}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems}}},
  year         = {{2019}},
}

@misc{14546,
  author       = {{Hansmeier, Tim}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}}},
  year         = {{2019}},
}

@phdthesis{34167,
  author       = {{Riebler, Heinrich}},
  title        = {{{Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs}}},
  doi          = {{10.17619/UNIPB/1-830}},
  year         = {{2019}},
}

@inproceedings{3362,
  abstract     = {{Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node.}},
  author       = {{Lösch, Achim and Wiens, Alex and Platzner, Marco}},
  booktitle    = {{Proceedings of the International Conference on Architecture of Computing Systems (ARCS)}},
  isbn         = {{9783319776095}},
  issn         = {{0302-9743}},
  pages        = {{73--84}},
  publisher    = {{Springer International Publishing}},
  title        = {{{Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes}}},
  doi          = {{10.1007/978-3-319-77610-1_6}},
  volume       = {{10793}},
  year         = {{2018}},
}