@misc{595, author = {{Mallmann Trenn, Frederik}}, publisher = {{Universität Paderborn}}, title = {{{On scheduling with multi-core and multi-speed processors using power down}}}, year = {{2012}}, } @misc{611, author = {{Hangmann, Hendrik}}, publisher = {{Universität Paderborn}}, title = {{{Generating Adjustable Temperature Gradients on modern FPGAs}}}, year = {{2012}}, } @misc{634, author = {{Kratzmann, Julian}}, publisher = {{Universität Paderborn}}, title = {{{Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen}}}, year = {{2012}}, } @misc{13462, author = {{Lewis, Peter and Platzner, Marco and Yao, Xin}}, publisher = {{Awareness Magazine}}, title = {{{An outlook for self-awareness in computing systems}}}, year = {{2012}}, } @inproceedings{615, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.}}, author = {{Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}}}, doi = {{10.1109/ReConFig.2012.6416745}}, year = {{2012}}, } @inproceedings{591, abstract = {{One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.}}, author = {{Kenter, Tobias and Plessl, Christian and Schmitz, Henning}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Pragma based parallelization - Trading hardware efficiency for ease of use?}}}, doi = {{10.1109/ReConFig.2012.6416773}}, year = {{2012}}, } @inproceedings{609, abstract = {{Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}}, pages = {{8--9}}, title = {{{Hardware/Software Platform for Self-aware Compute Nodes}}}, year = {{2012}}, } @inproceedings{567, abstract = {{Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.}}, author = {{Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}}, pages = {{559--565}}, publisher = {{IEEE}}, title = {{{Turning control flow graphs into function calls: Code generation for heterogeneous architectures}}}, doi = {{10.1109/HPCSim.2012.6266973}}, year = {{2012}}, } @inproceedings{612, abstract = {{While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.}}, author = {{Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, pages = {{559--562}}, publisher = {{IEEE}}, title = {{{Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @misc{643, author = {{Welp, Daniel}}, publisher = {{Universität Paderborn}}, title = {{{User-space Scheduling for Heterogeneous System under Linux}}}, year = {{2011}}, } @inproceedings{664, abstract = {{Web Computing is a variant of parallel computing where the idle times of PCs donated by worldwide distributed users are employed to execute parallel programs. The PUB-Web library developed by us supports this kind of usage of computing resources. A major problem for the efficient execution of such parallel programs is load balancing. In the Web Computing context, this problem becomes more difficult because of the dynamic behavior of the underlying "parallel computer": the set of available processors (donated PCs) as well as their availability (idle times) change over time in an unpredictable fashion.In this paper, we experimentally evaluate and compare load balancing algorithms in this scenario, namely a variant of the well-established Work Stealing algorithm and strategies based on a heterogeneous version of distributed hash-tables (DHHTs) introduced recently. In order to run a meaningful experimental evaluation, we employ, in addition to our Web Computing library PUB-Web, realistic data sets for the job input streams and for the dynamics of the availability of the resources.Our experimental evaluations suggest that Work Stealing is the better strategy if the number of processes ready to run matches the number of available processors. But a suitable variant of DHHTs outperforms Work Stealing if there are significantly more processes ready to run than available processors.}}, author = {{Gehweiler, Joachim and Kling, Peter and Meyer auf der Heide, Friedhelm}}, booktitle = {{Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)}}, pages = {{31----40}}, title = {{{An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment}}}, doi = {{10.1007/978-3-642-31500-8_4}}, year = {{2011}}, } @inproceedings{656, abstract = {{In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{55--60}}, publisher = {{IEEE}}, title = {{{Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}}}, doi = {{10.1109/ReConFig.2011.59}}, year = {{2011}}, }