[{"date_created":"2018-06-26T14:10:18Z","supervisor":[{"first_name":"Achim","last_name":"Lösch","id":"43646","full_name":"Lösch, Achim"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"author":[{"first_name":"Jan-Philip","full_name":"Schnuer, Jan-Philip","last_name":"Schnuer"}],"date_updated":"2022-01-06T06:59:13Z","publisher":"Universität Paderborn","title":"Static Scheduling Algorithms for Heterogeneous Compute Nodes","citation":{"apa":"Schnuer, J.-P. (2018). <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>. Universität Paderborn.","bibtex":"@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip}, year={2018} }","mla":"Schnuer, Jan-Philip. <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>. Universität Paderborn, 2018.","short":"J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes, Universität Paderborn, 2018.","ama":"Schnuer J-P. <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>. Universität Paderborn; 2018.","chicago":"Schnuer, Jan-Philip. <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>. Universität Paderborn, 2018.","ieee":"J.-P. Schnuer, <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>. Universität Paderborn, 2018."},"year":"2018","user_id":"477","department":[{"_id":"78"}],"project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"3365","language":[{"iso":"eng"}],"type":"bachelorsthesis","status":"public"},{"year":"2018","citation":{"apa":"Croce, M. (2018). <i>Evaluation of OpenCL-based Compilation for FPGAs</i>. Universität Paderborn.","bibtex":"@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs}, publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }","short":"M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn, 2018.","mla":"Croce, Marcel. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität Paderborn, 2018.","ieee":"M. Croce, <i>Evaluation of OpenCL-based Compilation for FPGAs</i>. Universität Paderborn, 2018.","chicago":"Croce, Marcel. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität Paderborn, 2018.","ama":"Croce M. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität Paderborn; 2018."},"title":"Evaluation of OpenCL-based Compilation for FPGAs","date_updated":"2022-01-06T06:59:13Z","publisher":"Universität Paderborn","author":[{"full_name":"Croce, Marcel","last_name":"Croce","first_name":"Marcel"}],"date_created":"2018-06-26T14:12:00Z","supervisor":[{"last_name":"Lösch","full_name":"Lösch, Achim","id":"43646","first_name":"Achim"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"status":"public","type":"bachelorsthesis","language":[{"iso":"eng"}],"_id":"3366","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"78"}],"user_id":"477"},{"project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"_id":"5414","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:52Z","date_created":"2018-11-07T15:14:26Z","supervisor":[{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"author":[{"full_name":"Filmwala, Tasneem","last_name":"Filmwala","first_name":"Tasneem"}],"title":"Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform","year":"2018","citation":{"ama":"Filmwala T. <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn; 2018.","chicago":"Filmwala, Tasneem. <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn, 2018.","ieee":"T. Filmwala, <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform</i>. Universität Paderborn, 2018.","apa":"Filmwala, T. (2018). <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform</i>. Universität Paderborn.","mla":"Filmwala, Tasneem. <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn, 2018.","short":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform, Universität Paderborn, 2018.","bibtex":"@book{Filmwala_2018, title={Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform}, publisher={Universität Paderborn}, author={Filmwala, Tasneem}, year={2018} }"}},{"year":"2018","citation":{"bibtex":"@book{Gadewar_2018, title={Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL}, publisher={Universität Paderborn}, author={Gadewar, Onkar}, year={2018} }","short":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL, Universität Paderborn, 2018.","mla":"Gadewar, Onkar. <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn, 2018.","apa":"Gadewar, O. (2018). <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn.","ama":"Gadewar O. <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn; 2018.","chicago":"Gadewar, Onkar. <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn, 2018.","ieee":"O. Gadewar, <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn, 2018."},"title":"Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL","date_updated":"2022-01-06T07:01:53Z","publisher":"Universität Paderborn","supervisor":[{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"author":[{"first_name":"Onkar","full_name":"Gadewar, Onkar","last_name":"Gadewar"}],"date_created":"2018-11-07T16:16:56Z","status":"public","type":"mastersthesis","language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"5421","user_id":"477","department":[{"_id":"27"},{"_id":"518"}]},{"date_created":"2018-11-14T09:26:53Z","publisher":"IEEE","title":"A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes","year":"2018","language":[{"iso":"eng"}],"ddc":["040"],"publication":"2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":2464949,"access_level":"closed","file_name":"loesch_asap2018.pdf","file_id":"5552","date_updated":"2018-11-14T09:40:42Z","date_created":"2018-11-14T09:40:42Z","creator":"aloesch"}],"author":[{"first_name":"Achim","full_name":"Lösch, Achim","id":"43646","last_name":"Lösch"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T07:01:59Z","conference":{"location":"Milan, Italy","end_date":"2018-07-12","start_date":"2018-07-10","name":"The 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors"},"doi":"10.1109/asap.2018.8445098","has_accepted_license":"1","publication_identifier":{"isbn":["9781538674796"]},"publication_status":"published","citation":{"short":"A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018.","mla":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>.","bibtex":"@inproceedings{Lösch_Platzner_2018, title={A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}, DOI={<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>}, booktitle={2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, publisher={IEEE}, author={Lösch, Achim and Platzner, Marco}, year={2018} }","apa":"Lösch, A., &#38; Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In <i>2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. Milan, Italy: IEEE. <a href=\"https://doi.org/10.1109/asap.2018.8445098\">https://doi.org/10.1109/asap.2018.8445098</a>","ieee":"A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in <i>2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, Milan, Italy, 2018.","chicago":"Lösch, Achim, and Marco Platzner. “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.” In <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/asap.2018.8445098\">https://doi.org/10.1109/asap.2018.8445098</a>.","ama":"Lösch A, Platzner M. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In: <i>2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/asap.2018.8445098\">10.1109/asap.2018.8445098</a>"},"department":[{"_id":"78"}],"user_id":"43646","_id":"5547","project":[{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"1","name":"SFB 901"}],"file_date_updated":"2018-11-14T09:40:42Z","type":"conference","status":"public"},{"year":"2018","date_created":"2018-11-07T16:08:32Z","publisher":"Universität Paderborn","title":"Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA","file":[{"file_name":"masterthesis.pdf","file_id":"17093","access_level":"closed","file_size":1297585,"date_created":"2020-06-15T11:29:38Z","creator":"arjunr","date_updated":"2020-06-15T11:29:38Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"abstract":[{"lang":"eng","text":"Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs."}],"language":[{"iso":"eng"}],"keyword":["FFT: FPGA","CP2K","OpenCL"],"ddc":["000"],"has_accepted_license":"1","citation":{"bibtex":"@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn}, author={Ramaswami, Arjun}, year={2018} }","short":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018.","mla":"Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","apa":"Ramaswami, A. (2018). <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn.","ama":"Ramaswami A. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn; 2018.","ieee":"A. Ramaswami, <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","chicago":"Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018."},"author":[{"first_name":"Arjun","orcid":"https://orcid.org/0000-0002-0909-1178","last_name":"Ramaswami","id":"49171","full_name":"Ramaswami, Arjun"}],"supervisor":[{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"date_updated":"2022-01-12T16:32:23Z","oa":"1","main_file_link":[{"open_access":"1"}],"type":"mastersthesis","status":"public","department":[{"_id":"27"},{"_id":"518"}],"user_id":"49171","_id":"5417","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"file_date_updated":"2020-06-15T11:29:38Z"},{"citation":{"ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>","ieee":"T. Kenter <i>et al.</i>, “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: <a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>.","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/FCCM.2018.00037\">https://doi.org/10.1109/FCCM.2018.00037</a>.","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>.","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., &#38; Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). <a href=\"https://doi.org/10.1109/FCCM.2018.00037\">https://doi.org/10.1109/FCCM.2018.00037</a>"},"has_accepted_license":"1","doi":"10.1109/FCCM.2018.00037","conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Mahale","full_name":"Mahale, Gopinath","first_name":"Gopinath"},{"first_name":"Samer","last_name":"Alhaddad","id":"42456","full_name":"Alhaddad, Samer"},{"first_name":"Yevgen","id":"26059","full_name":"Grynko, Yevgen","last_name":"Grynko"},{"full_name":"Schmitt, Christian","last_name":"Schmitt","first_name":"Christian"},{"full_name":"Afzal, Ayesha","last_name":"Afzal","first_name":"Ayesha"},{"first_name":"Frank","last_name":"Hannig","full_name":"Hannig, Frank"},{"id":"158","full_name":"Förstner, Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862","first_name":"Jens"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2023-09-26T11:47:52Z","status":"public","type":"conference","file_date_updated":"2018-11-02T14:45:05Z","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"grant_number":"01|H16005A","_id":"33","name":"HighPerMeshes"},{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"_id":"1588","year":"2018","quality_controlled":"1","title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","date_created":"2018-03-22T10:48:01Z","publisher":"IEEE","file":[{"file_size":269130,"file_name":"08457652.pdf","file_id":"5282","access_level":"closed","date_updated":"2018-11-02T14:45:05Z","date_created":"2018-11-02T14:45:05Z","creator":"ups","success":1,"relation":"main_file","content_type":"application/pdf"}],"abstract":[{"text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.","lang":"eng"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","language":[{"iso":"eng"}],"ddc":["000"],"keyword":["tet_topic_hpc"]},{"publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","file":[{"file_name":"p417-riebler.pdf","access_level":"closed","file_id":"5281","file_size":447769,"date_created":"2018-11-02T14:43:37Z","creator":"ups","date_updated":"2018-11-02T14:43:37Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"keyword":["htrop"],"ddc":["000"],"language":[{"iso":"eng"}],"quality_controlled":"1","year":"2018","publisher":"ACM","date_created":"2018-03-08T14:45:18Z","title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","type":"conference","status":"public","_id":"1204","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subproject C2"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","file_date_updated":"2018-11-02T14:43:37Z","has_accepted_license":"1","publication_identifier":{"isbn":["9781450349826"]},"publication_status":"published","citation":{"ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>. ACM; 2018. doi:<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>. ACM, 2018. <a href=\"https://doi.org/10.1145/3178487.3178534\">https://doi.org/10.1145/3178487.3178534</a>.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: <a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>.","apa":"Riebler, H., Vaz, G. F., Kenter, T., &#38; Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>. <a href=\"https://doi.org/10.1145/3178487.3178534\">https://doi.org/10.1145/3178487.3178534</a>","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>."},"date_updated":"2023-09-26T11:47:23Z","author":[{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz","first_name":"Gavin Francis"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"doi":"10.1145/3178487.3178534"},{"citation":{"apa":"Knorr, C. (2017). <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn.","mla":"Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn, 2017.","short":"C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten, Universität Paderborn, 2017.","bibtex":"@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }","chicago":"Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn, 2017.","ieee":"C. Knorr, <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn, 2017.","ama":"Knorr C. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>. Universität Paderborn; 2017."},"year":"2017","title":"OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten","date_created":"2017-10-17T12:41:05Z","supervisor":[{"id":"43646","full_name":"Lösch, Achim","last_name":"Lösch","first_name":"Achim"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"author":[{"first_name":"Christoph","full_name":"Knorr, Christoph","last_name":"Knorr"}],"publisher":"Universität Paderborn","date_updated":"2022-01-06T07:03:36Z","status":"public","type":"mastersthesis","language":[{"iso":"ger"}],"user_id":"477","department":[{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"74"},{"publication":"Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","type":"conference","status":"public","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":467545,"access_level":"closed","file_name":"loesch_asap2017.pdf","file_id":"5550","date_updated":"2018-11-14T09:37:55Z","creator":"aloesch","date_created":"2018-11-14T09:37:55Z"}],"abstract":[{"text":"Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.","lang":"eng"}],"department":[{"_id":"78"}],"user_id":"477","_id":"65","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"file_date_updated":"2018-11-14T09:37:55Z","language":[{"iso":"eng"}],"ddc":["040"],"has_accepted_license":"1","citation":{"chicago":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” In <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>.","ieee":"A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>, 2017.","ama":"Lösch A, Platzner M. reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In: <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>. ; 2017. doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>","bibtex":"@inproceedings{Lösch_Platzner_2017, title={reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>}, booktitle={Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, author={Lösch, Achim and Platzner, Marco}, year={2017} }","mla":"Lösch, Achim, and Marco Platzner. “ReMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements.” <i>Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)</i>, 2017, doi:<a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">10.1109/ASAP.2017.7995272</a>.","short":"A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.","apa":"Lösch, A., &#38; Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In <i>Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)</i>. <a href=\"https://doi.org/10.1109/ASAP.2017.7995272\">https://doi.org/10.1109/ASAP.2017.7995272</a>"},"year":"2017","date_created":"2017-10-17T12:41:04Z","author":[{"last_name":"Lösch","id":"43646","full_name":"Lösch, Achim","first_name":"Achim"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T07:03:08Z","doi":"10.1109/ASAP.2017.7995272","title":"reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements"},{"ddc":["000"],"keyword":["coldboot"],"language":[{"iso":"eng"}],"abstract":[{"text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.","lang":"eng"}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_name":"a24-riebler.pdf","file_id":"5322","access_level":"closed","file_size":2131617,"date_created":"2018-11-02T16:04:14Z","creator":"ups","date_updated":"2018-11-02T16:04:14Z"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","publisher":"Association for Computing Machinery (ACM)","date_created":"2017-07-25T14:17:32Z","year":"2017","quality_controlled":"1","issue":"3","file_date_updated":"2018-11-02T16:04:14Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subproject C2"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"18","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"status":"public","type":"journal_article","doi":"10.1145/3053687","date_updated":"2023-09-26T13:23:58Z","author":[{"last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961","first_name":"Heinrich"},{"full_name":"Lass, Michael","id":"24135","orcid":"0000-0002-5708-7632","last_name":"Lass","first_name":"Michael"},{"first_name":"Robert","last_name":"Mittendorf","full_name":"Mittendorf, Robert"},{"first_name":"Thomas","last_name":"Löcke","full_name":"Löcke, Thomas"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"volume":10,"citation":{"apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., &#38; Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>10</i>(3), 24:1-24:23. <a href=\"https://doi.org/10.1145/3053687\">https://doi.org/10.1145/3053687</a>","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>.","short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.","bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2017;10(3):24:1-24:23. doi:<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>","chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 10, no. 3 (2017): 24:1-24:23. <a href=\"https://doi.org/10.1145/3053687\">https://doi.org/10.1145/3053687</a>.","ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 10, no. 3, p. 24:1-24:23, 2017, doi: <a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>."},"intvolume":"        10","page":"24:1-24:23","publication_status":"published","publication_identifier":{"issn":["1936-7406"]},"has_accepted_license":"1"},{"status":"public","type":"conference","file_date_updated":"2018-11-02T15:02:28Z","_id":"1592","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"},{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"user_id":"15278","citation":{"ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2017. doi:<a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>","ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: <a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>.","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2017. <a href=\"https://doi.org/10.23919/FPL.2017.8056844\">https://doi.org/10.23919/FPL.2017.8056844</a>.","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2017, doi:<a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={<a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","apa":"Kenter, T., Förstner, J., &#38; Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. <a href=\"https://doi.org/10.23919/FPL.2017.8056844\">https://doi.org/10.23919/FPL.2017.8056844</a>"},"has_accepted_license":"1","doi":"10.23919/FPL.2017.8056844","date_updated":"2023-09-26T13:24:38Z","author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Jens","full_name":"Förstner, Jens","id":"158","last_name":"Förstner","orcid":"0000-0001-7059-9862"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"abstract":[{"text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.","lang":"eng"}],"file":[{"date_updated":"2018-11-02T15:02:28Z","date_created":"2018-11-02T15:02:28Z","creator":"ups","file_size":230235,"file_id":"5291","access_level":"closed","file_name":"08056844.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["tet_topic_hpc"],"ddc":["000"],"language":[{"iso":"eng"}],"year":"2017","quality_controlled":"1","title":"Flexible FPGA design for FDTD using OpenCL","publisher":"IEEE","date_created":"2018-03-22T11:10:23Z"},{"project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"_id":"5418","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:52Z","supervisor":[{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"author":[{"first_name":"Christian","full_name":"Tölke, Christian","last_name":"Tölke"}],"date_created":"2018-11-07T16:10:00Z","title":"Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung","year":"2016","citation":{"apa":"Tölke, C. (2016). <i>Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung</i>. Universität Paderborn.","short":"C. Tölke, Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung, Universität Paderborn, 2016.","bibtex":"@book{Tölke_2016, title={Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung}, publisher={Universität Paderborn}, author={Tölke, Christian}, year={2016} }","mla":"Tölke, Christian. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn, 2016.","ama":"Tölke C. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn; 2016.","chicago":"Tölke, Christian. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn, 2016.","ieee":"C. Tölke, <i>Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung</i>. Universität Paderborn, 2016."}},{"year":"2016","citation":{"ama":"Wüllrich G. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn; 2016.","chicago":"Wüllrich, Gunnar. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn, 2016.","ieee":"G. Wüllrich, <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn, 2016.","bibtex":"@book{Wüllrich_2016, title={Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment}, publisher={Universität Paderborn}, author={Wüllrich, Gunnar}, year={2016} }","short":"G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment, Universität Paderborn, 2016.","mla":"Wüllrich, Gunnar. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn, 2016.","apa":"Wüllrich, G. (2016). <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn."},"publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:53Z","supervisor":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2018-11-07T16:15:51Z","author":[{"last_name":"Wüllrich","full_name":"Wüllrich, Gunnar","first_name":"Gunnar"}],"title":"Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment","type":"mastersthesis","status":"public","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"5420","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"language":[{"iso":"eng"}]},{"title":"Reconfigurable Accelerators in the World of General-Purpose Computing","date_created":"2017-10-17T12:41:23Z","supervisor":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"}],"date_updated":"2022-01-06T06:52:43Z","publisher":"Universität Paderborn","citation":{"apa":"Kenter, T. (2016). <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn.","bibtex":"@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016} }","short":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing, Universität Paderborn, 2016.","mla":"Kenter, Tobias. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn, 2016.","ieee":"T. Kenter, <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn, 2016.","chicago":"Kenter, Tobias. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn, 2016.","ama":"Kenter T. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn; 2016."},"year":"2016","has_accepted_license":"1","file_date_updated":"2018-03-21T12:46:48Z","ddc":["040"],"user_id":"3145","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"_id":"161","file":[{"creator":"florida","date_created":"2018-03-21T12:46:48Z","date_updated":"2018-03-21T12:46:48Z","file_name":"161kenter16_diss_submission_print_16-08-26.pdf","file_id":"1545","access_level":"closed","file_size":5039555,"content_type":"application/pdf","relation":"main_file","success":1}],"status":"public","type":"dissertation"},{"type":"conference","publication":"Proc. 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Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>. ; 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>."},"date_updated":"2023-09-26T13:25:59Z","author":[{"last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961","first_name":"Heinrich"},{"last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G.","first_name":"Ettore M. G."},{"full_name":"Durelli, Gianluca C.","last_name":"Durelli","first_name":"Gianluca C."},{"last_name":"Bolchini","full_name":"Bolchini, Cristiana","first_name":"Cristiana"}],"date_created":"2017-07-26T15:16:31Z","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems"},{"file_date_updated":"2018-11-14T12:38:45Z","language":[{"iso":"eng"}],"ddc":["004"],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"_id":"24","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":129552,"file_name":"paper_26.pdf","access_level":"closed","file_id":"5602","date_updated":"2018-11-14T12:38:45Z","creator":"kenter","date_created":"2018-11-14T12:38:45Z"}],"status":"public","type":"conference","publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","author":[{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2017-07-26T15:00:43Z","date_updated":"2023-09-26T13:26:17Z","citation":{"chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2016.","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. ; 2016.","apa":"Kenter, T., &#38; Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>.","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }"},"year":"2016","has_accepted_license":"1","quality_controlled":"1"},{"year":"2016","citation":{"apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, IEEE, 2016, pp. 1–5, doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G.  and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D.  and Bolchini, Christina}, year={2016}, pages={1–5} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","ieee":"H. Riebler <i>et al.</i>, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 2016, pp. 1–5, doi: <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G.  Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D.  Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. IEEE, 2016. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>.","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>. IEEE; 2016:1-5. doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>"},"page":"1-5","quality_controlled":"1","has_accepted_license":"1","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","doi":"10.1109/RTSI.2016.7740545","date_updated":"2023-09-26T13:28:11Z","publisher":"IEEE","author":[{"first_name":"Heinrich","id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler"},{"first_name":"Gavin Francis","last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Trainiti, Ettore M. G. ","last_name":"Trainiti","first_name":"Ettore M. G. "},{"first_name":"Gianluca C.","full_name":"Durelli, Gianluca C.","last_name":"Durelli"},{"full_name":"Del Sozzo, Emanuele","last_name":"Del Sozzo","first_name":"Emanuele"},{"first_name":"Marco D. ","full_name":"Santambrogio, Marco D. ","last_name":"Santambrogio"},{"last_name":"Bolchini","full_name":"Bolchini, Christina","first_name":"Christina"}],"date_created":"2017-10-17T12:41:18Z","abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_name":"138-07740545.pdf","access_level":"closed","file_id":"1560","file_size":184334,"creator":"florida","date_created":"2018-03-21T13:01:09Z","date_updated":"2018-03-21T13:01:09Z"}],"status":"public","type":"conference","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-21T13:01:09Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"138","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}]},{"quality_controlled":"1","year":"2016","publisher":"Springer International Publishing","date_created":"2017-10-17T12:41:22Z","title":"Self-aware Compute Nodes","publication":"Self-aware Computing Systems","abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"file":[{"access_level":"closed","file_id":"5613","file_name":"chapter8.pdf","file_size":833054,"creator":"aloesch","date_created":"2018-11-14T13:20:32Z","date_updated":"2018-11-14T13:20:32Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"ddc":["040"],"language":[{"iso":"eng"}],"has_accepted_license":"1","place":"Cham","page":"145-165","citation":{"ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: <i>Self-Aware Computing Systems</i>. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In <i>Self-Aware Computing Systems</i>, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in <i>Self-aware Computing Systems</i>, Cham: Springer International Publishing, 2016, pp. 145–165.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” <i>Self-Aware Computing Systems</i>, Springer International Publishing, 2016, pp. 145–65, doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2016). Self-aware Compute Nodes. In <i>Self-aware Computing Systems</i> (pp. 145–165). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>"},"date_updated":"2023-09-26T13:27:44Z","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Achim","last_name":"Lösch","id":"43646","full_name":"Lösch, Achim"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"doi":"10.1007/978-3-319-39675-0_8","type":"book_chapter","status":"public","_id":"156","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"series_title":"Natural Computing Series (NCS)","user_id":"15278","file_date_updated":"2018-11-14T13:20:32Z"},{"type":"journal_article","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"165","file_date_updated":"2018-03-21T12:45:47Z","publication_identifier":{"issn":["0045-7906"]},"has_accepted_license":"1","citation":{"chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i> 55 (2016): 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” <i>Computers and Electrical Engineering</i>, vol. 55, pp. 91–111, 2016, doi: <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>. 2016;55:91-111. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i>, vol. 55, Elsevier, 2016, pp. 91–111, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>, <i>55</i>, 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>"},"intvolume":"        55","page":"91-111","author":[{"first_name":"Gavin Francis","id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz"},{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"volume":55,"date_updated":"2023-09-26T13:26:38Z","doi":"10.1016/j.compeleceng.2016.04.021","publication":"Computers and Electrical Engineering","file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"florida","date_created":"2018-03-21T12:45:47Z","date_updated":"2018-03-21T12:45:47Z","access_level":"closed","file_name":"165-1-s2.0-S0045790616301021-main.pdf","file_id":"1544","file_size":3037854}],"abstract":[{"text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["040"],"quality_controlled":"1","year":"2016","date_created":"2017-10-17T12:41:24Z","publisher":"Elsevier","title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code"}]