[{"date_created":"2017-10-17T12:42:16Z","user_id":"15504","author":[{"full_name":"Damschen, Marvin","last_name":"Damschen","first_name":"Marvin"}],"_id":"436","date_updated":"2022-01-06T07:00:58Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"publisher":"Universität Paderborn","title":"Easy-to-use on-the-fly binary program acceleration on many-cores","type":"mastersthesis","status":"public","citation":{"apa":"Damschen, M. (2014). <i>Easy-to-use on-the-fly binary program acceleration on many-cores</i>. Universität Paderborn.","bibtex":"@book{Damschen_2014, title={Easy-to-use on-the-fly binary program acceleration on many-cores}, publisher={Universität Paderborn}, author={Damschen, Marvin}, year={2014} }","short":"M. Damschen, Easy-to-Use on-the-Fly Binary Program Acceleration on Many-Cores, Universität Paderborn, 2014.","mla":"Damschen, Marvin. <i>Easy-to-Use on-the-Fly Binary Program Acceleration on Many-Cores</i>. Universität Paderborn, 2014.","ama":"Damschen M. <i>Easy-to-Use on-the-Fly Binary Program Acceleration on Many-Cores</i>. Universität Paderborn; 2014.","chicago":"Damschen, Marvin. <i>Easy-to-Use on-the-Fly Binary Program Acceleration on Many-Cores</i>. Universität Paderborn, 2014.","ieee":"M. Damschen, <i>Easy-to-use on-the-fly binary program acceleration on many-cores</i>. Universität Paderborn, 2014."},"year":"2014"},{"author":[{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_updated":"2023-09-26T13:32:49Z","citation":{"chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in <i>Logiken strukturbildender Prozesse: Automatismen</i>, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. <i>Logiken strukturbildender Prozesse: Automatismen</i>. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","apa":"Platzner, M., &#38; Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, &#38; T. Kaerlein (Eds.), <i>Logiken strukturbildender Prozesse: Automatismen</i> (pp. 123–144). Wilhelm Fink.","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144."},"page":"123-144","place":"Paderborn","publication_status":"published","has_accepted_license":"1","publication_identifier":{"isbn":["978-3-7705-5730-1"]},"file_date_updated":"2018-03-20T07:29:58Z","series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","user_id":"15278","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"335","status":"public","editor":[{"first_name":"Jörn","last_name":"Künsemöller","full_name":"Künsemöller, Jörn"},{"first_name":"Norber Otto","full_name":"Eke, Norber Otto","last_name":"Eke"},{"first_name":"Lioba","full_name":"Foit, Lioba","last_name":"Foit"},{"full_name":"Kaerlein, Timo","last_name":"Kaerlein","first_name":"Timo"}],"type":"book_chapter","title":"Verschiebungen an der Grenze zwischen Hardware und Software","date_created":"2017-10-17T12:41:57Z","publisher":"Wilhelm Fink","year":"2014","quality_controlled":"1","language":[{"iso":"ger"}],"ddc":["040"],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"florida","date_created":"2018-03-20T07:29:58Z","date_updated":"2018-03-20T07:29:58Z","file_id":"1424","file_name":"335-2014_plessl_automatismen.pdf","access_level":"closed","file_size":2848154}],"abstract":[{"lang":"eng","text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf."}],"publication":"Logiken strukturbildender Prozesse: Automatismen"},{"series_title":"Lecture Notes in Computer Science (LNCS)","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"388","file_date_updated":"2018-03-20T07:02:02Z","type":"conference","status":"public","author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332","first_name":"Gavin Francis"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"volume":8405,"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","has_accepted_license":"1","citation":{"ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>.","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>"},"page":"144-155","intvolume":"      8405","place":"Cham","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":330193,"file_id":"1387","file_name":"388-plessl14_arc.pdf","access_level":"closed","date_updated":"2018-03-20T07:02:02Z","date_created":"2018-03-20T07:02:02Z","creator":"florida"}],"abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"date_created":"2017-10-17T12:42:07Z","publisher":"Springer International Publishing","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","quality_controlled":"1","year":"2014"},{"issue":"8, Part B","has_accepted_license":"1","quality_controlled":"1","citation":{"apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>."},"page":"911-919","intvolume":"        38","year":"2014","date_created":"2017-10-17T12:42:02Z","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"volume":38,"publisher":"Elsevier","date_updated":"2023-09-26T13:33:06Z","doi":"10.1016/j.micpro.2013.12.001","title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","type":"journal_article","publication":"Microprocessors and Microsystems","file":[{"file_size":1499996,"file_name":"363-plessl13_micpro.pdf","file_id":"1408","access_level":"closed","date_updated":"2018-03-20T07:20:31Z","creator":"florida","date_created":"2018-03-20T07:20:31Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"status":"public","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.","lang":"eng"}],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"363","file_date_updated":"2018-03-20T07:20:31Z","language":[{"iso":"eng"}],"ddc":["040"]},{"keyword":["coldboot"],"ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_name":"377-FCCM14.pdf","access_level":"closed","file_id":"1397","file_size":1003907,"date_created":"2018-03-20T07:14:20Z","creator":"florida","date_updated":"2018-03-20T07:14:20Z"}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","publisher":"IEEE","date_created":"2017-10-17T12:42:05Z","year":"2014","quality_controlled":"1","file_date_updated":"2018-03-20T07:14:20Z","_id":"377","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","type":"conference","doi":"10.1109/FCCM.2014.67","date_updated":"2023-09-26T13:33:50Z","author":[{"first_name":"Heinrich","last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Christoph","last_name":"Sorge","full_name":"Sorge, Christoph"}],"page":"222-229","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2014, pp. 222–29, doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","apa":"Riebler, H., Kenter, T., Plessl, C., &#38; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–229. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–29. IEEE, 2014. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 2014, pp. 222–229, doi: <a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2014:222-229. doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>"},"has_accepted_license":"1"},{"type":"journal_article","status":"public","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"365","user_id":"15278","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"article_number":"13","file_date_updated":"2018-03-20T07:19:19Z","has_accepted_license":"1","citation":{"ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>"},"intvolume":"         7","date_updated":"2023-09-26T13:33:31Z","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim","id":"43646"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"volume":7,"doi":"10.1145/2617596","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","abstract":[{"lang":"eng","text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems."}],"file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-20T07:19:19Z","creator":"florida","date_created":"2018-03-20T07:19:19Z","file_size":916052,"access_level":"closed","file_name":"365-plessl14_trets_01.pdf","file_id":"1406"}],"ddc":["040"],"language":[{"iso":"eng"}],"quality_controlled":"1","issue":"2","year":"2014","publisher":"ACM","date_created":"2017-10-17T12:42:03Z","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores"},{"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","publisher":"IEEE","date_created":"2017-10-17T12:41:55Z","year":"2014","quality_controlled":"1","issue":"1","ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"file":[{"date_updated":"2018-03-20T07:31:40Z","creator":"florida","date_created":"2018-03-20T07:31:40Z","file_size":1877185,"file_name":"328-plessl14_micro_01.pdf","access_level":"closed","file_id":"1426","content_type":"application/pdf","success":1,"relation":"main_file"}],"publication":"IEEE Micro","doi":"10.1109/MM.2013.110","date_updated":"2023-09-26T13:32:31Z","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Keller","full_name":"Keller, Ariane","first_name":"Ariane"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"first_name":"Bernhard","last_name":"Plattner","full_name":"Plattner, Bernhard"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"volume":34,"citation":{"ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>. 2014;34(1):60-71. doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i> 34, no. 1 (2014): 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>.","ieee":"A. Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i>, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &#38; Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>, <i>34</i>(1), 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>"},"page":"60-71","intvolume":"        34","has_accepted_license":"1","file_date_updated":"2018-03-20T07:31:40Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"328","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"journal_article"},{"doi":"10.1109/ReConFig.2014.7032509","author":[{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"date_updated":"2023-09-26T13:37:02Z","citation":{"mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>"},"page":"1-8","has_accepted_license":"1","file_date_updated":"2018-03-16T11:29:52Z","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"439","status":"public","type":"conference","title":"Deferring Accelerator Offloading Decisions to Application Runtime","date_created":"2017-10-17T12:42:17Z","publisher":"IEEE","year":"2014","quality_controlled":"1","language":[{"iso":"eng"}],"ddc":["040"],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"florida","date_created":"2018-03-16T11:29:52Z","date_updated":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","access_level":"closed","file_id":"1353","file_size":557362}],"abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)"},{"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","date_created":"2017-10-17T12:42:11Z","publisher":"IEEE","year":"2014","quality_controlled":"1","language":[{"iso":"eng"}],"ddc":["040"],"file":[{"file_size":932852,"access_level":"closed","file_id":"1366","file_name":"406-ReConFig14.pdf","date_updated":"2018-03-16T11:37:42Z","creator":"florida","date_created":"2018-03-16T11:37:42Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2014.7032535","author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_updated":"2023-09-26T13:36:40Z","page":"1-8","citation":{"chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"has_accepted_license":"1","file_date_updated":"2018-03-16T11:37:42Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"406","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"status":"public","type":"conference"},{"_id":"489","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"user_id":"15504","type":"mastersthesis","status":"public","date_updated":"2022-01-06T07:01:28Z","publisher":"Universität Paderborn","date_created":"2017-10-17T12:42:27Z","author":[{"full_name":"Knopf, Michael","last_name":"Knopf","first_name":"Michael"}],"title":"Scheduling Variants with Speed-Scaling via the Primal-Dual Approach","year":"2013","citation":{"ama":"Knopf M. <i>Scheduling Variants with Speed-Scaling via the Primal-Dual Approach</i>. Universität Paderborn; 2013.","chicago":"Knopf, Michael. <i>Scheduling Variants with Speed-Scaling via the Primal-Dual Approach</i>. Universität Paderborn, 2013.","ieee":"M. Knopf, <i>Scheduling Variants with Speed-Scaling via the Primal-Dual Approach</i>. Universität Paderborn, 2013.","bibtex":"@book{Knopf_2013, title={Scheduling Variants with Speed-Scaling via the Primal-Dual Approach}, publisher={Universität Paderborn}, author={Knopf, Michael}, year={2013} }","mla":"Knopf, Michael. <i>Scheduling Variants with Speed-Scaling via the Primal-Dual Approach</i>. Universität Paderborn, 2013.","short":"M. Knopf, Scheduling Variants with Speed-Scaling via the Primal-Dual Approach, Universität Paderborn, 2013.","apa":"Knopf, M. (2013). <i>Scheduling Variants with Speed-Scaling via the Primal-Dual Approach</i>. Universität Paderborn."}},{"has_accepted_license":"1","year":"2013","citation":{"ama":"Kling P, Pietrzyk P. Profitable Scheduling on Multiple Speed-Scalable Processors. In: <i>Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)</i>. ; 2013:251-260. doi:<a href=\"https://doi.org/10.1145/2486159.2486183\">10.1145/2486159.2486183</a>","ieee":"P. Kling and P. Pietrzyk, “Profitable Scheduling on Multiple Speed-Scalable Processors,” in <i>Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)</i>, 2013, pp. 251–260.","chicago":"Kling, Peter, and Peter Pietrzyk. “Profitable Scheduling on Multiple Speed-Scalable Processors.” In <i>Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)</i>, 251–60, 2013. <a href=\"https://doi.org/10.1145/2486159.2486183\">https://doi.org/10.1145/2486159.2486183</a>.","short":"P. Kling, P. Pietrzyk, in: Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), 2013, pp. 251–260.","bibtex":"@inproceedings{Kling_Pietrzyk_2013, title={Profitable Scheduling on Multiple Speed-Scalable Processors}, DOI={<a href=\"https://doi.org/10.1145/2486159.2486183\">10.1145/2486159.2486183</a>}, booktitle={Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)}, author={Kling, Peter and Pietrzyk, Peter}, year={2013}, pages={251–260} }","mla":"Kling, Peter, and Peter Pietrzyk. “Profitable Scheduling on Multiple Speed-Scalable Processors.” <i>Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)</i>, 2013, pp. 251–60, doi:<a href=\"https://doi.org/10.1145/2486159.2486183\">10.1145/2486159.2486183</a>.","apa":"Kling, P., &#38; Pietrzyk, P. (2013). Profitable Scheduling on Multiple Speed-Scalable Processors. In <i>Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)</i> (pp. 251–260). <a href=\"https://doi.org/10.1145/2486159.2486183\">https://doi.org/10.1145/2486159.2486183</a>"},"page":"251-260 ","date_updated":"2022-01-06T07:01:34Z","date_created":"2017-10-17T12:42:29Z","author":[{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"full_name":"Pietrzyk, Peter","last_name":"Pietrzyk","first_name":"Peter"}],"title":"Profitable Scheduling on Multiple Speed-Scalable Processors","doi":"10.1145/2486159.2486183","type":"conference","publication":"Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)","abstract":[{"text":"We present a new online algorithm for profit-oriented scheduling on multiple speed-scalable processors.Moreover, we provide a tight analysis of the algorithm's competitiveness.Our results generalize and improve upon work by \\citet{Chan:2010}, which considers a single speed-scalable processor.Using significantly different techniques, we can not only extend their model to multiprocessors but also prove an enhanced and tight competitive ratio for our algorithm.In our scheduling problem, jobs arrive over time and are preemptable.They have different workloads, values, and deadlines.The scheduler may decide not to finish a job but instead to suffer a loss equaling the job's value.However, to process a job's workload until its deadline the scheduler must invest a certain amount of energy.The cost of a schedule is the sum of lost values and invested energy.In order to finish a job the scheduler has to determine which processors to use and set their speeds accordingly.A processor's energy consumption is power $\\Power{s}$ integrated over time, where $\\Power{s}=s^{\\alpha}$ is the power consumption when running at speed $s$.Since we consider the online variant of the problem, the scheduler has no knowledge about future jobs.This problem was introduced by~\\citet{Chan:2010} for the case of a single processor.They presented an online algorithm which is $\\alpha^{\\alpha}+2e\\alpha$-competitive.We provide an online algorithm for the case of multiple processors with an improved competitive ratio of $\\alpha^{\\alpha}$.","lang":"eng"}],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"florida","date_created":"2018-03-15T13:40:02Z","date_updated":"2018-03-15T13:40:02Z","file_name":"499-P._Kling__P._Pietryzk_-_Profitable_Scheduling_on_Multiple_Speed-scalable_Processors__2013_.pdf","access_level":"closed","file_id":"1310","file_size":558661}],"status":"public","project":[{"name":"SFB 901","_id":"1"},{"_id":"16","name":"SFB 901 - Subproject C4"},{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"499","user_id":"477","department":[{"_id":"63"}],"ddc":["040"],"file_date_updated":"2018-03-15T13:40:02Z","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"477","_id":"501","project":[{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"}],"status":"public","abstract":[{"lang":"eng","text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. "}],"type":"dissertation","title":"Performance and thermal management on self-adaptive hybrid multi-cores","date_created":"2017-10-17T12:42:30Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"}],"supervisor":[{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"publisher":"Logos Verlag Berlin GmbH","date_updated":"2022-01-06T07:01:34Z","page":"220","citation":{"ama":"Happe M. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2013.","ieee":"M. Happe, <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","chicago":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","apa":"Happe, M. (2013). <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH.","short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","mla":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Logos Verlag Berlin GmbH, 2013."},"place":"Berlin","year":"2013","related_material":{"link":[{"relation":"confirmation","url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id="}]},"publication_identifier":{"isbn":["978-3-8325-3425-7"]},"publication_status":"published"},{"title":"Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"}],"date_created":"2017-10-17T12:42:34Z","date_updated":"2022-01-06T07:01:46Z","publisher":"Universität Paderborn","citation":{"apa":"Riebler, H. (2013). <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn.","mla":"Riebler, Heinrich. <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn, 2013.","short":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs, Universität Paderborn, 2013.","bibtex":"@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Universität Paderborn}, author={Riebler, Heinrich}, year={2013} }","ama":"Riebler H. <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn; 2013.","chicago":"Riebler, Heinrich. <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn, 2013.","ieee":"H. Riebler, <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn, 2013."},"year":"2013","language":[{"iso":"ger"}],"keyword":["coldboot"],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"477","_id":"521","project":[{"name":"SFB 901","_id":"1"},{"_id":"13","name":"SFB 901 - Subprojekt C1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"status":"public","type":"mastersthesis"},{"language":[{"iso":"ger"}],"user_id":"477","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"_id":"549","status":"public","type":"bachelorsthesis","title":"Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner","date_created":"2017-10-17T12:42:39Z","author":[{"first_name":"Christian","full_name":"Bick, Christian","last_name":"Bick"}],"publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:56Z","citation":{"ieee":"C. Bick, <i>Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Universität Paderborn, 2013.","chicago":"Bick, Christian. <i>Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Universität Paderborn, 2013.","ama":"Bick C. <i>Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Universität Paderborn; 2013.","apa":"Bick, C. (2013). <i>Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Universität Paderborn.","mla":"Bick, Christian. <i>Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner</i>. Universität Paderborn, 2013.","short":"C. Bick, Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner, Universität Paderborn, 2013.","bibtex":"@book{Bick_2013, title={Beschleunigung von Tiefenberechung aus Stereobildern durch FPGA-basierte Datenflussrechner}, publisher={Universität Paderborn}, author={Bick, Christian}, year={2013} }"},"year":"2013"},{"language":[{"iso":"ger"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"550","user_id":"477","status":"public","type":"bachelorsthesis","title":"Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen","publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:56Z","author":[{"first_name":"Julian","last_name":"Meschede","full_name":"Meschede, Julian"}],"date_created":"2017-10-17T12:42:39Z","year":"2013","citation":{"bibtex":"@book{Meschede_2013, title={Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen}, publisher={Universität Paderborn}, author={Meschede, Julian}, year={2013} }","short":"J. Meschede, Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen, Universität Paderborn, 2013.","mla":"Meschede, Julian. <i>Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen</i>. Universität Paderborn, 2013.","apa":"Meschede, J. (2013). <i>Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen</i>. Universität Paderborn.","chicago":"Meschede, Julian. <i>Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen</i>. Universität Paderborn, 2013.","ieee":"J. Meschede, <i>Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen</i>. Universität Paderborn, 2013.","ama":"Meschede J. <i>Bandbreiten-beschränktes Scheduling mit skalierbaren Jobanforderungen in Multiprozessor-Umgebungen</i>. Universität Paderborn; 2013."}},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"528","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"file_date_updated":"2018-03-15T10:36:08Z","language":[{"iso":"eng"}],"keyword":["coldboot"],"ddc":["040"],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","type":"conference","status":"public","file":[{"creator":"florida","date_created":"2018-03-15T10:36:08Z","date_updated":"2018-03-15T10:36:08Z","access_level":"closed","file_id":"1294","file_name":"528-plessl13_fpt.pdf","file_size":822680,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"date_created":"2017-10-17T12:42:35Z","author":[{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2023-09-26T13:37:35Z","publisher":"IEEE","doi":"10.1109/FPT.2013.6718394","title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","quality_controlled":"1","has_accepted_license":"1","page":"386-389","citation":{"chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–89. IEEE, 2013. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2013, pp. 386–389, doi: <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2013:386-389. doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2013, pp. 386–89, doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","apa":"Riebler, H., Kenter, T., Sorge, C., &#38; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–389. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>"},"year":"2013"},{"year":"2013","citation":{"ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., &#38; Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>, IEEE, 2013, doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }"},"quality_controlled":"1","has_accepted_license":"1","title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","doi":"10.1109/ISORC.2013.6913232","publisher":"IEEE","date_updated":"2023-09-26T13:38:20Z","date_created":"2017-10-17T12:42:30Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Kling","full_name":"Kling, Peter","first_name":"Peter"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Friedhelm","last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm","id":"15523"}],"abstract":[{"lang":"eng","text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas."}],"status":"public","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","access_level":"closed","file_id":"1308","file_name":"505-Plessl13_seus.pdf","file_size":1040834,"creator":"florida","date_created":"2018-03-15T13:38:56Z","date_updated":"2018-03-15T13:38:56Z"}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","type":"conference","ddc":["040"],"file_date_updated":"2018-03-15T13:38:56Z","language":[{"iso":"eng"}],"_id":"505","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278"},{"type":"bachelorsthesis","year":"2012","citation":{"apa":"Schmitz, H. (2012). <i>Stereo Matching on a Convey HC-1 Hybrid Core Computer</i>. Universität Paderborn.","mla":"Schmitz, Henning. <i>Stereo Matching on a Convey HC-1 Hybrid Core Computer</i>. Universität Paderborn, 2012.","bibtex":"@book{Schmitz_2012, title={Stereo Matching on a Convey HC-1 Hybrid Core Computer}, publisher={Universität Paderborn}, author={Schmitz, Henning}, year={2012} }","short":"H. Schmitz, Stereo Matching on a Convey HC-1 Hybrid Core Computer, Universität Paderborn, 2012.","ieee":"H. Schmitz, <i>Stereo Matching on a Convey HC-1 Hybrid Core Computer</i>. Universität Paderborn, 2012.","chicago":"Schmitz, Henning. <i>Stereo Matching on a Convey HC-1 Hybrid Core Computer</i>. Universität Paderborn, 2012.","ama":"Schmitz H. <i>Stereo Matching on a Convey HC-1 Hybrid Core Computer</i>. Universität Paderborn; 2012."},"status":"public","project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_updated":"2022-01-06T07:02:38Z","publisher":"Universität Paderborn","_id":"576","date_created":"2017-10-17T12:42:44Z","author":[{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"}],"user_id":"15504","title":"Stereo Matching on a Convey HC-1 Hybrid Core Computer"},{"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T09:03:39Z","ddc":["040"],"department":[{"_id":"63"}],"series_title":"LNCS","user_id":"477","_id":"580","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Subproject C4","_id":"16"},{"_id":"4","name":"SFB 901 - Project Area C"}],"status":"public","file":[{"date_updated":"2018-03-15T09:03:39Z","date_created":"2018-03-15T09:03:39Z","creator":"florida","file_size":325939,"access_level":"closed","file_id":"1265","file_name":"580-P._Kling__F._Mallmann-Trenn__A._Cord-Landwehr_-_Slow_Down___Sleep_for_Profit_in_Online_Deadline_Scheduling.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"text":"We present and study a new model for energy-aware and profit-oriented scheduling on a single processor.The processor features dynamic speed scaling as well as suspension to a sleep mode.Jobs arrive over time, are preemptable, and have different sizes, values, and deadlines.On the arrival of a new job, the scheduler may either accept or reject the job.Accepted jobs need a certain energy investment to be finished in time, while rejected jobs cause costs equal to their values.Here, power consumption at speed $s$ is given by $P(s)=s^{\\alpha}+\\beta$ and the energy investment is power integrated over time.Additionally, the scheduler may decide to suspend the processor to a sleep mode in which no energy is consumed, though awaking entails fixed transition costs $\\gamma$.The objective is to minimize the total value of rejected jobs plus the total energy.Our model combines aspects from advanced energy conservation techniques (namely speed scaling and sleep states) and profit-oriented scheduling models.We show that \\emph{rejection-oblivious} schedulers (whose rejection decisions are not based on former decisions) have – in contrast to the model without sleep states – an unbounded competitive ratio.It turns out that the jobs' value densities (the ratio between a job's value and its work) are crucial for the performance of such schedulers.We give an algorithm whose competitiveness nearly matches the lower bound w.r.t\\text{.} the maximum value density.If the maximum value density is not too large, the competitiveness becomes $\\alpha^{\\alpha}+2e\\alpha$.Also, we show that it suffices to restrict the value density of low-value jobs only.Using a technique from \\cite{Chan:2010} we transfer our results to processors with a fixed maximum speed.","lang":"eng"}],"editor":[{"first_name":"Guy","last_name":"Even","full_name":"Even, Guy"},{"first_name":"Dror","full_name":"Rawitz, Dror","last_name":"Rawitz"}],"publication":"Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)","type":"conference","doi":"10.1007/978-3-642-34862-4_17","title":"Slow Down & Sleep for Profit in Online Deadline Scheduling","date_created":"2017-10-17T12:42:45Z","author":[{"last_name":"Cord-Landwehr","full_name":"Cord-Landwehr, Andreas","first_name":"Andreas"},{"last_name":"Kling","full_name":"Kling, Peter","first_name":"Peter"},{"full_name":"Mallmann Trenn, Fredrik","last_name":"Mallmann Trenn","first_name":"Fredrik"}],"date_updated":"2022-01-06T07:02:42Z","page":"218-231","citation":{"mla":"Cord-Landwehr, Andreas, et al. “Slow Down &#38; Sleep for Profit in Online Deadline Scheduling.” <i>Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)</i>, edited by Guy Even and Dror Rawitz, 2012, pp. 218–31, doi:<a href=\"https://doi.org/10.1007/978-3-642-34862-4_17\">10.1007/978-3-642-34862-4_17</a>.","bibtex":"@inproceedings{Cord-Landwehr_Kling_Mallmann Trenn_2012, series={LNCS}, title={Slow Down &#38; Sleep for Profit in Online Deadline Scheduling}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-34862-4_17\">10.1007/978-3-642-34862-4_17</a>}, booktitle={Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)}, author={Cord-Landwehr, Andreas and Kling, Peter and Mallmann Trenn, Fredrik}, editor={Even, Guy and Rawitz, DrorEditors}, year={2012}, pages={218–231}, collection={LNCS} }","short":"A. Cord-Landwehr, P. Kling, F. Mallmann Trenn, in: G. Even, D. Rawitz (Eds.), Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg), 2012, pp. 218–231.","apa":"Cord-Landwehr, A., Kling, P., &#38; Mallmann Trenn, F. (2012). Slow Down &#38; Sleep for Profit in Online Deadline Scheduling. In G. Even &#38; D. Rawitz (Eds.), <i>Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)</i> (pp. 218–231). <a href=\"https://doi.org/10.1007/978-3-642-34862-4_17\">https://doi.org/10.1007/978-3-642-34862-4_17</a>","ama":"Cord-Landwehr A, Kling P, Mallmann Trenn F. Slow Down &#38; Sleep for Profit in Online Deadline Scheduling. In: Even G, Rawitz D, eds. <i>Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)</i>. LNCS. ; 2012:218-231. doi:<a href=\"https://doi.org/10.1007/978-3-642-34862-4_17\">10.1007/978-3-642-34862-4_17</a>","ieee":"A. Cord-Landwehr, P. Kling, and F. Mallmann Trenn, “Slow Down &#38; Sleep for Profit in Online Deadline Scheduling,” in <i>Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)</i>, 2012, pp. 218–231.","chicago":"Cord-Landwehr, Andreas, Peter Kling, and Fredrik Mallmann Trenn. “Slow Down &#38; Sleep for Profit in Online Deadline Scheduling.” In <i>Proceedings of the 1st Mediterranean Conference on Algorithms (MedAlg)</i>, edited by Guy Even and Dror Rawitz, 218–31. LNCS, 2012. <a href=\"https://doi.org/10.1007/978-3-642-34862-4_17\">https://doi.org/10.1007/978-3-642-34862-4_17</a>."},"year":"2012","has_accepted_license":"1"},{"year":"2012","citation":{"ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine; 2012.","chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine, 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., &#38; Lübbers, E. (2012). <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","mla":"Plessl, Christian, et al. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012."},"has_accepted_license":"1","title":"Programming models for reconfigurable heterogeneous multi-cores","date_updated":"2022-01-06T07:02:44Z","publisher":"Awareness Magazine","date_created":"2017-10-17T12:42:46Z","author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"}],"status":"public","file":[{"date_updated":"2018-03-15T08:37:02Z","date_created":"2018-03-15T08:37:02Z","creator":"florida","file_size":353057,"access_level":"closed","file_name":"587-2012_plessl_awareness_magazine.pdf","file_id":"1260","content_type":"application/pdf","success":1,"relation":"main_file"}],"type":"misc","ddc":["040"],"file_date_updated":"2018-03-15T08:37:02Z","language":[{"iso":"eng"}],"_id":"587","project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"398"}]