[{"publisher":"Universität Paderborn","date_updated":"2022-01-06T07:02:48Z","author":[{"full_name":"Mallmann Trenn, Frederik","last_name":"Mallmann Trenn","first_name":"Frederik"}],"date_created":"2017-10-17T12:42:48Z","title":"On scheduling with multi-core and multi-speed processors using power down","year":"2012","citation":{"bibtex":"@book{Mallmann Trenn_2012, title={On scheduling with multi-core and multi-speed processors using power down}, publisher={Universität Paderborn}, author={Mallmann Trenn, Frederik}, year={2012} }","mla":"Mallmann Trenn, Frederik. <i>On Scheduling with Multi-Core and Multi-Speed Processors Using Power Down</i>. Universität Paderborn, 2012.","short":"F. Mallmann Trenn, On Scheduling with Multi-Core and Multi-Speed Processors Using Power Down, Universität Paderborn, 2012.","apa":"Mallmann Trenn, F. (2012). <i>On scheduling with multi-core and multi-speed processors using power down</i>. Universität Paderborn.","chicago":"Mallmann Trenn, Frederik. <i>On Scheduling with Multi-Core and Multi-Speed Processors Using Power Down</i>. Universität Paderborn, 2012.","ieee":"F. Mallmann Trenn, <i>On scheduling with multi-core and multi-speed processors using power down</i>. Universität Paderborn, 2012.","ama":"Mallmann Trenn F. <i>On Scheduling with Multi-Core and Multi-Speed Processors Using Power Down</i>. Universität Paderborn; 2012."},"_id":"595","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"user_id":"15504","type":"bachelorsthesis","status":"public"},{"year":"2012","citation":{"bibtex":"@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Universität Paderborn}, author={Hangmann, Hendrik}, year={2012} }","mla":"Hangmann, Hendrik. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Universität Paderborn, 2012.","short":"H. Hangmann, Generating Adjustable Temperature Gradients on Modern FPGAs, Universität Paderborn, 2012.","apa":"Hangmann, H. (2012). <i>Generating Adjustable Temperature Gradients on modern FPGAs</i>. Universität Paderborn.","ieee":"H. Hangmann, <i>Generating Adjustable Temperature Gradients on modern FPGAs</i>. Universität Paderborn, 2012.","chicago":"Hangmann, Hendrik. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Universität Paderborn, 2012.","ama":"Hangmann H. <i>Generating Adjustable Temperature Gradients on Modern FPGAs</i>. Universität Paderborn; 2012."},"date_updated":"2022-01-06T07:02:53Z","publisher":"Universität Paderborn","author":[{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"}],"date_created":"2017-10-17T12:42:51Z","title":"Generating Adjustable Temperature Gradients on modern FPGAs","type":"bachelorsthesis","status":"public","_id":"611","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"user_id":"15504"},{"user_id":"477","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"634","language":[{"iso":"ger"}],"type":"bachelorsthesis","status":"public","author":[{"first_name":"Julian","full_name":"Kratzmann, Julian","last_name":"Kratzmann"}],"date_created":"2017-10-17T12:42:55Z","date_updated":"2022-01-06T07:03:01Z","publisher":"Universität Paderborn","title":"Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen","citation":{"apa":"Kratzmann, J. (2012). <i>Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen</i>. Universität Paderborn.","bibtex":"@book{Kratzmann_2012, title={Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen}, publisher={Universität Paderborn}, author={Kratzmann, Julian}, year={2012} }","mla":"Kratzmann, Julian. <i>Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen</i>. Universität Paderborn, 2012.","short":"J. Kratzmann, Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen, Universität Paderborn, 2012.","ieee":"J. Kratzmann, <i>Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen</i>. Universität Paderborn, 2012.","chicago":"Kratzmann, Julian. <i>Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen</i>. Universität Paderborn, 2012.","ama":"Kratzmann J. <i>Analyse und Simulation von energieeffizienten Online-Scheduling Algorithmen</i>. Universität Paderborn; 2012."},"year":"2012"},{"year":"2012","citation":{"mla":"Lewis, Peter, et al. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine, 2012.","short":"P. Lewis, M. Platzner, X. Yao, An Outlook for Self-Awareness in Computing Systems, Awareness Magazine, 2012.","bibtex":"@book{Lewis_Platzner_Yao_2012, title={An outlook for self-awareness in computing systems}, publisher={Awareness Magazine}, author={Lewis, Peter and Platzner, Marco and Yao, Xin}, year={2012} }","apa":"Lewis, P., Platzner, M., &#38; Yao, X. (2012). <i>An outlook for self-awareness in computing systems</i>. Awareness Magazine.","chicago":"Lewis, Peter, Marco Platzner, and Xin Yao. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine, 2012.","ieee":"P. Lewis, M. Platzner, and X. Yao, <i>An outlook for self-awareness in computing systems</i>. Awareness Magazine, 2012.","ama":"Lewis P, Platzner M, Yao X. <i>An Outlook for Self-Awareness in Computing Systems</i>. Awareness Magazine; 2012."},"date_updated":"2022-01-06T06:51:36Z","publisher":"Awareness Magazine","author":[{"full_name":"Lewis, Peter","last_name":"Lewis","first_name":"Peter"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"first_name":"Xin","full_name":"Yao, Xin","last_name":"Yao"}],"date_created":"2019-09-30T09:24:09Z","title":"An outlook for self-awareness in computing systems","type":"misc","status":"public","_id":"13462","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"department":[{"_id":"78"}],"user_id":"398","language":[{"iso":"eng"}]},{"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":730144,"access_level":"closed","file_name":"615-ReConFig12_01.pdf","file_id":"1246","date_updated":"2018-03-15T06:48:32Z","date_created":"2018-03-15T06:48:32Z","creator":"florida"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"language":[{"iso":"eng"}],"ddc":["040"],"quality_controlled":"1","year":"2012","date_created":"2017-10-17T12:42:51Z","publisher":"IEEE","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","type":"conference","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"615","file_date_updated":"2018-03-15T06:48:32Z","has_accepted_license":"1","citation":{"apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>."},"page":"1-8","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745"},{"author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"},{"full_name":"Schmitz, Henning","last_name":"Schmitz","first_name":"Henning"}],"date_updated":"2023-09-26T13:41:08Z","doi":"10.1109/ReConFig.2012.6416773","has_accepted_license":"1","citation":{"short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>."},"page":"1-8","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"591","file_date_updated":"2018-03-15T08:33:18Z","type":"conference","status":"public","date_created":"2017-10-17T12:42:47Z","publisher":"IEEE","title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","quality_controlled":"1","year":"2012","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file":[{"date_updated":"2018-03-15T08:33:18Z","date_created":"2018-03-15T08:33:18Z","creator":"florida","file_size":371235,"file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","file_id":"1257","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"lang":"eng","text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort."}]},{"type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"file":[{"date_updated":"2018-03-15T08:14:17Z","creator":"florida","date_created":"2018-03-15T08:14:17Z","file_size":146789,"access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","file_id":"1249","content_type":"application/pdf","success":1,"relation":"main_file"}],"status":"public","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"ddc":["040"],"file_date_updated":"2018-03-15T08:14:17Z","language":[{"iso":"eng"}],"has_accepted_license":"1","quality_controlled":"1","year":"2012","citation":{"ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9."},"page":"8-9","date_updated":"2023-09-26T13:41:36Z","date_created":"2017-10-17T12:42:50Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes"},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"567","file_date_updated":"2018-03-15T10:20:24Z","type":"conference","status":"public","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"full_name":"Carreras, Carlos","last_name":"Carreras","first_name":"Carlos"},{"full_name":"Sierra, Roberto","last_name":"Sierra","first_name":"Roberto"},{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","has_accepted_license":"1","citation":{"ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }"},"page":"559-565","language":[{"iso":"eng"}],"ddc":["040"],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file":[{"date_updated":"2018-03-15T10:20:24Z","date_created":"2018-03-15T10:20:24Z","creator":"florida","file_size":288508,"file_name":"567-ba-ca-12a.pdf","file_id":"1275","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"date_created":"2017-10-17T12:42:42Z","publisher":"IEEE","title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","quality_controlled":"1","year":"2012"},{"date_created":"2017-10-17T12:42:51Z","author":[{"first_name":"Christoph","full_name":"Rüthing, Christoph","last_name":"Rüthing"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"IEEE","date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","has_accepted_license":"1","quality_controlled":"1","citation":{"short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>."},"page":"559-562","year":"2012","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"612","language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T06:49:03Z","ddc":["040"],"type":"conference","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":202923,"file_name":"612-ruething_fpl12.pdf","access_level":"closed","file_id":"1247","date_updated":"2018-03-15T06:49:03Z","date_created":"2018-03-15T06:49:03Z","creator":"florida"}],"status":"public","abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}]},{"type":"mastersthesis","year":"2011","citation":{"ama":"Welp D. <i>User-Space Scheduling for Heterogeneous System under Linux</i>. Universität Paderborn; 2011.","chicago":"Welp, Daniel. <i>User-Space Scheduling for Heterogeneous System under Linux</i>. Universität Paderborn, 2011.","ieee":"D. Welp, <i>User-space Scheduling for Heterogeneous System under Linux</i>. Universität Paderborn, 2011.","short":"D. Welp, User-Space Scheduling for Heterogeneous System under Linux, Universität Paderborn, 2011.","mla":"Welp, Daniel. <i>User-Space Scheduling for Heterogeneous System under Linux</i>. Universität Paderborn, 2011.","bibtex":"@book{Welp_2011, title={User-space Scheduling for Heterogeneous System under Linux}, publisher={Universität Paderborn}, author={Welp, Daniel}, year={2011} }","apa":"Welp, D. (2011). <i>User-space Scheduling for Heterogeneous System under Linux</i>. Universität Paderborn."},"status":"public","date_updated":"2022-01-06T07:03:04Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"publisher":"Universität Paderborn","_id":"643","author":[{"first_name":"Daniel","full_name":"Welp, Daniel","last_name":"Welp"}],"user_id":"15504","date_created":"2017-10-17T12:42:57Z","title":"User-space Scheduling for Heterogeneous System under Linux"},{"citation":{"apa":"Gehweiler, J., Kling, P., &#38; Meyer auf der Heide, F. (2011). An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment. In <i>Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)</i> (pp. 31--40). <a href=\"https://doi.org/10.1007/978-3-642-31500-8_4\">https://doi.org/10.1007/978-3-642-31500-8_4</a>","bibtex":"@inproceedings{Gehweiler_Kling_Meyer auf der Heide_2011, series={LNCS}, title={An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-31500-8_4\">10.1007/978-3-642-31500-8_4</a>}, booktitle={Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)}, author={Gehweiler, Joachim and Kling, Peter and Meyer auf der Heide, Friedhelm}, year={2011}, pages={31--40}, collection={LNCS} }","mla":"Gehweiler, Joachim, et al. “An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment.” <i>Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)</i>, 2011, pp. 31--40, doi:<a href=\"https://doi.org/10.1007/978-3-642-31500-8_4\">10.1007/978-3-642-31500-8_4</a>.","short":"J. Gehweiler, P. Kling, F. Meyer auf der Heide, in: Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM), 2011, pp. 31--40.","ieee":"J. Gehweiler, P. Kling, and F. Meyer auf der Heide, “An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment,” in <i>Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)</i>, 2011, pp. 31--40.","chicago":"Gehweiler, Joachim, Peter Kling, and Friedhelm Meyer auf der Heide. “An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment.” In <i>Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)</i>, 31--40. LNCS, 2011. <a href=\"https://doi.org/10.1007/978-3-642-31500-8_4\">https://doi.org/10.1007/978-3-642-31500-8_4</a>.","ama":"Gehweiler J, Kling P, Meyer auf der Heide F. An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment. In: <i>Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)</i>. LNCS. ; 2011:31--40. doi:<a href=\"https://doi.org/10.1007/978-3-642-31500-8_4\">10.1007/978-3-642-31500-8_4</a>"},"page":"31--40","year":"2011","has_accepted_license":"1","doi":"10.1007/978-3-642-31500-8_4","title":"An Experimental Comparison of Load Balancing Strategies in a Web Computing Environment","author":[{"first_name":"Joachim","last_name":"Gehweiler","full_name":"Gehweiler, Joachim"},{"first_name":"Peter","last_name":"Kling","full_name":"Kling, Peter"},{"first_name":"Friedhelm","id":"15523","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide"}],"date_created":"2017-10-17T12:43:01Z","date_updated":"2022-01-06T07:03:14Z","file":[{"file_size":333335,"access_level":"closed","file_id":"1216","file_name":"664-PPAM11GKM_01.pdf","date_updated":"2018-03-14T13:45:57Z","creator":"florida","date_created":"2018-03-14T13:45:57Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"status":"public","abstract":[{"text":"Web Computing is a variant of parallel computing where the idle times of PCs donated by worldwide distributed users are employed to execute parallel programs. The PUB-Web library developed by us supports this kind of usage of computing resources. A major problem for the efficient execution of such parallel programs is load balancing. In the Web Computing context, this problem becomes more difficult because of the dynamic behavior of the underlying \"parallel computer\": the set of available processors (donated PCs) as well as their availability (idle times) change over time in an unpredictable fashion.In this paper, we experimentally evaluate and compare load balancing algorithms in this scenario, namely a variant of the well-established Work Stealing algorithm and strategies based on a heterogeneous version of distributed hash-tables (DHHTs) introduced recently. In order to run a meaningful experimental evaluation, we employ, in addition to our Web Computing library PUB-Web, realistic data sets for the job input streams and for the dynamics of the availability of the resources.Our experimental evaluations suggest that Work Stealing is the better strategy if the number of processes ready to run matches the number of available processors. But a suitable variant of DHHTs outperforms Work Stealing if there are significantly more processes ready to run than available processors.","lang":"eng"}],"type":"conference","publication":"Proceedings of the 9th International Conference on Parallel Processing and Applied Mathematics (PPAM)","file_date_updated":"2018-03-14T13:45:57Z","ddc":["040"],"series_title":"LNCS","user_id":"15504","department":[{"_id":"63"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"16","name":"SFB 901 - Subprojekt C4"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"664"},{"has_accepted_license":"1","quality_controlled":"1","citation":{"bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2011, pp. 55–60, doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","apa":"Happe, M., Agne, A., &#38; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. IEEE, 2011. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2011, pp. 55–60, doi: <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2011:55-60. doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>"},"page":"55-60","year":"2011","date_created":"2017-10-17T12:42:59Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2023-09-26T13:46:08Z","publisher":"IEEE","doi":"10.1109/ReConFig.2011.59","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","type":"conference","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-14T13:49:39Z","date_created":"2018-03-14T13:49:39Z","creator":"florida","file_size":502244,"access_level":"closed","file_name":"656-2011_happe_reconfig.pdf","file_id":"1220"}],"status":"public","abstract":[{"text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"656","file_date_updated":"2018-03-14T13:49:39Z","language":[{"iso":"eng"}],"ddc":["040"]}]