---
_id: '168'
abstract:
- lang: eng
text: The use of heterogeneous computing resources, such as Graphic Processing Units
or other specialized coprocessors, has become widespread in recent years because
of their per- formance and energy efficiency advantages. Approaches for managing
and scheduling tasks to heterogeneous resources are still subject to research.
Although queuing systems have recently been extended to support accelerator resources,
a general solution that manages heterogeneous resources at the operating system-
level to exploit a global view of the system state is still missing.In this paper
we present a user space scheduler that enables task scheduling and migration on
heterogeneous processing resources in Linux. Using run queues for available resources
we perform scheduling decisions based on the system state and on task characterization
from earlier measurements. With a pro- gramming pattern that supports the integration
of checkpoints into applications, we preempt tasks and migrate them between three
very different compute resources. Considering static and dynamic workload scenarios,
we show that this approach can gain up to 17% performance, on average 7%, by effectively
avoiding idle resources. We demonstrate that a work-conserving strategy without
migration is no suitable alternative.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling
with task migration for a heterogeneous compute node in the data center. In: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE). EDA Consortium / IEEE; 2016:912-917.'
apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center.
Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 912–917.
bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center},
booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim
and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco},
year={2016}, pages={912–917} }'
chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco
Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous
Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation
& Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium
/ IEEE, 2016.
ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center,”
in Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2016, pp. 912–917.
mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for
a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design,
Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium
/ IEEE, 2016, pp. 912–17.
short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE), EDA Consortium / IEEE, 2016, pp. 912–917.'
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:27:00Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:41:55Z
date_updated: 2018-03-21T12:41:55Z
file_id: '1541'
file_name: 168-07459438.pdf
file_size: 261356
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:41:55Z
has_accepted_license: '1'
language:
- iso: eng
page: 912-917
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Performance-centric scheduling with task migration for a heterogeneous compute
node in the data center
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '171'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application
partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop
on Reconfigurable Computing (WRC). ; 2016.'
apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities
for deferring application partitioning and accelerator synthesis to runtime (extended
abstract). Workshop on Reconfigurable Computing (WRC).
bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for
deferring application partitioning and accelerator synthesis to runtime (extended
abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter,
Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016}
}'
chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl.
“Opportunities for Deferring Application Partitioning and Accelerator Synthesis
to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC),
2016.
ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring
application partitioning and accelerator synthesis to runtime (extended abstract),”
2016.
mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning
and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable
Computing (WRC), 2016.
short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable
Computing (WRC), 2016.'
date_created: 2017-10-17T12:41:25Z
date_updated: 2023-09-26T13:27:21Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:39:46Z
date_updated: 2018-03-21T12:39:46Z
file_id: '1538'
file_name: 171-plessl16_fpl_wrc.pdf
file_size: 54421
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:39:46Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Workshop on Reconfigurable Computing (WRC)
quality_controlled: '1'
status: public
title: Opportunities for deferring application partitioning and accelerator synthesis
to runtime (extended abstract)
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '3364'
author:
- first_name: Christoph
full_name: Knorr, Christoph
last_name: Knorr
citation:
ama: Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten.
Universität Paderborn; 2015.
apa: Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn.
bibtex: '@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in
heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph},
year={2015} }'
chicago: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn, 2015.
ieee: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten.
Universität Paderborn, 2015.
mla: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn, 2015.
short: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten,
Universität Paderborn, 2015.
date_created: 2018-06-26T14:06:07Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten
type: bachelorsthesis
user_id: '477'
year: '2015'
...
---
_id: '1772'
author:
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Xin
full_name: Yao, Xin
last_name: Yao
citation:
ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest
Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20.
https://doi.org/10.1109/MC.2015.205
bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205},
number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen,
Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }'
chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015):
18–20. https://doi.org/10.1109/MC.2015.205.'
ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems
– Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20,
2015.
mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s
Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015,
pp. 18–20, doi:10.1109/MC.2015.205.
short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.
date_created: 2018-03-23T14:06:12Z
date_updated: 2022-01-06T06:53:19Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MC.2015.205
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T15:47:45Z
date_updated: 2018-11-02T15:47:45Z
file_id: '5313'
file_name: 07163237.pdf
file_size: 5605009
relation: main_file
success: 1
file_date_updated: 2018-11-02T15:47:45Z
has_accepted_license: '1'
intvolume: ' 48'
issue: '7'
keyword:
- self-awareness
- self-expression
language:
- iso: eng
page: 18-20
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: IEEE Computer
publisher: IEEE Computer Society
status: public
title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction
type: journal_article
user_id: '16153'
volume: 48
year: '2015'
...
---
_id: '5413'
author:
- first_name: Lukas
full_name: Funke, Lukas
last_name: Funke
citation:
ama: Funke L. An LLVM Based Toolchain for Transparent Acceleration of Digital
Image Processing Applications Using FPGA Overlay Architectures. Universität
Paderborn; 2015.
apa: Funke, L. (2015). An LLVM Based Toolchain for Transparent Acceleration of
Digital Image Processing Applications using FPGA Overlay Architectures. Universität
Paderborn.
bibtex: '@book{Funke_2015, title={An LLVM Based Toolchain for Transparent Acceleration
of Digital Image Processing Applications using FPGA Overlay Architectures}, publisher={Universität
Paderborn}, author={Funke, Lukas}, year={2015} }'
chicago: Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of
Digital Image Processing Applications Using FPGA Overlay Architectures. Universität
Paderborn, 2015.
ieee: L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital
Image Processing Applications using FPGA Overlay Architectures. Universität
Paderborn, 2015.
mla: Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital
Image Processing Applications Using FPGA Overlay Architectures. Universität
Paderborn, 2015.
short: L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital
Image Processing Applications Using FPGA Overlay Architectures, Universität Paderborn,
2015.
date_created: 2018-11-07T15:10:35Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing
Applications using FPGA Overlay Architectures
type: mastersthesis
user_id: '477'
year: '2015'
...
---
_id: '5416'
author:
- first_name: Thomas
full_name: Löcke, Thomas
last_name: Löcke
citation:
ama: Löcke T. Instance-Specific Computing in Hard- and Software for Faster Solving
of Complex Problems. Universität Paderborn; 2015.
apa: Löcke, T. (2015). Instance-Specific Computing in Hard- and Software for
Faster Solving of Complex Problems. Universität Paderborn.
bibtex: '@book{Löcke_2015, title={Instance-Specific Computing in Hard- and Software
for Faster Solving of Complex Problems}, publisher={Universität Paderborn}, author={Löcke,
Thomas}, year={2015} }'
chicago: Löcke, Thomas. Instance-Specific Computing in Hard- and Software for
Faster Solving of Complex Problems. Universität Paderborn, 2015.
ieee: T. Löcke, Instance-Specific Computing in Hard- and Software for Faster
Solving of Complex Problems. Universität Paderborn, 2015.
mla: Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster
Solving of Complex Problems. Universität Paderborn, 2015.
short: T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving
of Complex Problems, Universität Paderborn, 2015.
date_created: 2018-11-07T16:06:53Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Instance-Specific Computing in Hard- and Software for Faster Solving of Complex
Problems
type: mastersthesis
user_id: '477'
year: '2015'
...
---
_id: '5419'
author:
- first_name: Felix
full_name: Wallaschek, Felix
last_name: Wallaschek
citation:
ama: Wallaschek F. Accelerating Programmable Logic Controllers with the Use of
FPGAs. Universität Paderborn; 2015.
apa: Wallaschek, F. (2015). Accelerating Programmable Logic Controllers with
the use of FPGAs. Universität Paderborn.
bibtex: '@book{Wallaschek_2015, title={Accelerating Programmable Logic Controllers
with the use of FPGAs}, publisher={Universität Paderborn}, author={Wallaschek,
Felix}, year={2015} }'
chicago: Wallaschek, Felix. Accelerating Programmable Logic Controllers with
the Use of FPGAs. Universität Paderborn, 2015.
ieee: F. Wallaschek, Accelerating Programmable Logic Controllers with the use
of FPGAs. Universität Paderborn, 2015.
mla: Wallaschek, Felix. Accelerating Programmable Logic Controllers with the
Use of FPGAs. Universität Paderborn, 2015.
short: F. Wallaschek, Accelerating Programmable Logic Controllers with the Use of
FPGAs, Universität Paderborn, 2015.
date_created: 2018-11-07T16:14:30Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Accelerating Programmable Logic Controllers with the use of FPGAs
type: mastersthesis
user_id: '477'
year: '2015'
...
---
_id: '296'
abstract:
- lang: eng
text: FPGAs are known to permit huge gains in performance and efficiency for suitable
applications but still require reduced design efforts and shorter development
cycles for wider adoption. In this work, we compare the resulting performance
of two design concepts that in different ways promise such increased productivity.
As common starting point, we employ a kernel-centric design approach, where computational
hotspots in an application are identified and individually accelerated on FPGA.
By means of a complex stereo matching application, we evaluate two fundamentally
different design philosophies and approaches for implementing the required kernels
on FPGAs. In the first implementation approach, we designed individually specialized
data flow kernels in a spatial programming language for a Maxeler FPGA platform;
in the alternative design approach, we target a vector coprocessor with large
vector lengths, which is implemented as a form of programmable overlay on the
application FPGAs of a Convey HC-1. We assess both approaches in terms of overall
system performance, raw kernel performance, and performance relative to invested
resources. After compensating for the effects of the underlying hardware platforms,
the specialized dataflow kernels on the Maxeler platform are around 3x faster
than kernels executing on the Convey vector coprocessor. In our concrete scenario,
due to trade-offs between reconfiguration overheads and exposed parallelism, the
advantage of specialized dataflow kernels is reduced to around 2.5x.
article_number: '859425'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels
and a Reusable Overlay in a Stereo-Matching Case Study. International Journal
of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International
Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425
bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015},
DOI={10.1155/2015/859425}, number={859425},
journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi},
author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015}
}'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs
between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”
International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized
Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International
Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015,
doi: 10.1155/2015/859425.'
mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and
a Reusable Overlay in a Stereo-Matching Case Study.” International Journal
of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable
Computing (IJRC) 2015 (2015).
date_created: 2017-10-17T12:41:49Z
date_updated: 2023-09-26T13:29:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2015/859425
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:47:56Z
date_updated: 2018-03-20T07:47:56Z
file_id: '1444'
file_name: 296-859425.pdf
file_size: 2993898
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:47:56Z
has_accepted_license: '1'
intvolume: ' 2015'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: International Journal of Reconfigurable Computing (IJRC)
publisher: Hindawi
quality_controlled: '1'
status: public
title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a
Stereo-Matching Case Study
type: journal_article
user_id: '15278'
volume: 2015
year: '2015'
...
---
_id: '303'
abstract:
- lang: eng
text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use
on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling
existentsoftware to automatically utilize accelerators at runtime. BAARis based
on the LLVM Compiler Infrastructure and has aclient-server architecture. The client
runs the program to beaccelerated in an environment which allows program analysisand
profiling. Program parts which are identified as suitable forthe available accelerator
are exported and sent to the server.The server optimizes these program parts for
the acceleratorand provides RPC execution for the client. The client transformsits
program to utilize accelerated execution on the server foroffloaded program parts.
We evaluate our work with a proofof-concept implementation of BAAR that uses an
Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading,
parallelization and vectorization of suitable programparts. The practicality of
BAAR for real-world examples is shownbased on a study of stencil codes. Our results
show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints
over the same code compiled with the Intel Compiler atoptimization level O2 and
running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand
evaluation we outline future directions of research, e.g.,offloading more fine-granular
program parts than functions, amore sophisticated communication mechanism or introducing
onstack-replacement.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on
Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning
Computing Systems (ADAPT). ; 2015.'
apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores. Proceedings of the 5th International Workshop on
Adaptive Self-Tuning Computing Systems (ADAPT).
bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International
Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen,
Marvin and Plessl, Christian}, year={2015} }'
chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores.” In Proceedings of the 5th International
Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration
on Many-Cores,” 2015.
mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores.” Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.'
date_created: 2017-10-17T12:41:51Z
date_updated: 2023-09-26T13:29:59Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
external_id:
arxiv:
- '1412.3906'
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:46:46Z
date_updated: 2019-08-01T09:10:44Z
file_id: '1442'
file_name: 303-plessl15_adapt.pdf
file_size: 1176620
relation: main_file
file_date_updated: 2019-08-01T09:10:44Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning
Computing Systems (ADAPT)
quality_controlled: '1'
status: public
title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '238'
abstract:
- lang: eng
text: In this paper, we study how binary applications can be transparently accelerated
with novel heterogeneous computing resources without requiring any manual porting
or developer-provided hints. Our work is based on Binary Acceleration At Runtime
(BAAR), our previously introduced binary acceleration mechanism that uses the
LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture.
The client runs the program to be accelerated in an environment, which allows
program analysis and profiling and identifies and extracts suitable program parts
to be offloaded. The server compiles and optimizes these offloaded program parts
for the accelerator and offers access to these functions to the client with a
remote procedure call (RPC) interface. Our previous work proved the feasibility
of our approach, but also showed that communication time and overheads limit the
granularity of functions that can be meaningfully offloaded. In this work, we
motivate the importance of a lightweight, high-performance communication between
server and client and present a communication mechanism based on the Message Passing
Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as
the acceleration target and show that the communication overhead can be reduced
from 40% to 10%, thus enabling even small hotspots to benefit from offloading
to an accelerator.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational
hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference
on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083.
doi:10.7873/DATE.2015.1124'
apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent
offloading of computational hotspots from binary code to Xeon Phi. Proceedings
of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.
https://doi.org/10.7873/DATE.2015.1124
bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading
of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124},
booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and
Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015},
pages={1078–1083} }'
chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl.
“Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”
In Proceedings of the 2015 Conference on Design, Automation and Test in Europe
(DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.
ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading
of computational hotspots from binary code to Xeon Phi,” in Proceedings of
the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015,
pp. 1078–1083, doi: 10.7873/DATE.2015.1124.'
mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots
from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design,
Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83,
doi:10.7873/DATE.2015.1124.
short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015
Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE,
2015, pp. 1078–1083.'
date_created: 2017-10-17T12:41:38Z
date_updated: 2023-09-26T13:31:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.7873/DATE.2015.1124
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:29:49Z
date_updated: 2018-03-21T10:29:49Z
file_id: '1500'
file_name: 238-plessl15_date.pdf
file_size: 380552
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:29:49Z
has_accepted_license: '1'
language:
- iso: eng
page: 1078-1083
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Transparent offloading of computational hotspots from binary code to Xeon Phi
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '334'
author:
- first_name: Peter
full_name: Wagener, Peter
last_name: Wagener
citation:
ama: Wagener P. Vertical Thread Migration in FPGA Based Sound Localization.
Universität Paderborn; 2014.
apa: Wagener, P. (2014). Vertical Thread Migration in FPGA based Sound Localization.
Universität Paderborn.
bibtex: '@book{Wagener_2014, title={Vertical Thread Migration in FPGA based Sound
Localization}, publisher={Universität Paderborn}, author={Wagener, Peter}, year={2014}
}'
chicago: Wagener, Peter. Vertical Thread Migration in FPGA Based Sound Localization.
Universität Paderborn, 2014.
ieee: P. Wagener, Vertical Thread Migration in FPGA based Sound Localization.
Universität Paderborn, 2014.
mla: Wagener, Peter. Vertical Thread Migration in FPGA Based Sound Localization.
Universität Paderborn, 2014.
short: P. Wagener, Vertical Thread Migration in FPGA Based Sound Localization, Universität
Paderborn, 2014.
date_created: 2017-10-17T12:41:57Z
date_updated: 2022-01-06T06:59:10Z
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
title: Vertical Thread Migration in FPGA based Sound Localization
type: bachelorsthesis
user_id: '477'
year: '2014'
...
---
_id: '347'
abstract:
- lang: eng
text: Dynamic thread duplication is a known redundancy technique for multi-cores.
The approach duplicates a thread under observation for some time period and compares
the signatures of the two threads to detect errors. Hybrid multi-cores, typically
implemented on platform FPGAs, enable the unique option of running the thread
under observation and its copy in different modalities, i.e., software and hardware.
We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing.
In this paper we present the concept of thread shadowing and an implementation
on a multi-threaded hybrid multi-core architecture. We report on experiments with
a block-processing application and demonstrate the overheads, detection latencies
and coverage for a range of thread shadowing modes. The results show that trans-modal
thread shadowing, although bearing long detection latencies, offers attractive
coverage at a low overhead.
author:
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid
Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP,
Bertels K, eds. Proceedings of the 10th International Symposium on Applied
Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer;
2014:283-290. doi:10.1007/978-3-319-05960-0_30'
apa: 'Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy
on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio,
J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer.
https://doi.org/10.1007/978-3-319-05960-0_30'
bibtex: '@inproceedings{Meisner_Platzner_2014, series={Lecture Notes in Computer
Science}, title={Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores
for Error Detection}, DOI={10.1007/978-3-319-05960-0_30},
booktitle={Proceedings of the 10th International Symposium on Applied Reconfigurable
Computing (ARC)}, publisher={Springer}, author={Meisner, Sebastian and Platzner,
Marco}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso,
JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={283–290}, collection={Lecture
Notes in Computer Science} }'
chicago: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic
Redundancy on Hybrid Multi-Cores for Error Detection.” In Proceedings of the
10th International Symposium on Applied Reconfigurable Computing (ARC), edited
by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and Koen Bertels,
283–90. Lecture Notes in Computer Science. Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_30.'
ieee: 'S. Meisner and M. Platzner, “Thread Shadowing: Using Dynamic Redundancy on
Hybrid Multi-cores for Error Detection,” in Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC), 2014, pp. 283–290.'
mla: 'Meisner, Sebastian, and Marco Platzner. “Thread Shadowing: Using Dynamic Redundancy
on Hybrid Multi-Cores for Error Detection.” Proceedings of the 10th International
Symposium on Applied Reconfigurable Computing (ARC), edited by Diana Goehringer
et al., Springer, 2014, pp. 283–90, doi:10.1007/978-3-319-05960-0_30.'
short: 'S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso,
K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied
Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.'
date_created: 2017-10-17T12:41:59Z
date_updated: 2022-01-06T06:59:18Z
ddc:
- '040'
department:
- _id: '78'
doi: 10.1007/978-3-319-05960-0_30
editor:
- first_name: Diana
full_name: Goehringer, Diana
last_name: Goehringer
- first_name: MarcoDomenico
full_name: Santambrogio, MarcoDomenico
last_name: Santambrogio
- first_name: JoãoM.P.
full_name: Cardoso, JoãoM.P.
last_name: Cardoso
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:26:16Z
date_updated: 2018-03-20T07:26:16Z
file_id: '1417'
file_name: 347-meisner13_xx_SFB1__1_.pdf
file_size: 1168877
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:26:16Z
has_accepted_license: '1'
language:
- iso: eng
page: 283-290
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 10th International Symposium on Applied Reconfigurable
Computing (ARC)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: 'Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error
Detection'
type: conference
user_id: '398'
year: '2014'
...
---
_id: '348'
author:
- first_name: Christoph
full_name: Rüthing, Christoph
last_name: Rüthing
citation:
ama: Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Universität Paderborn; 2014.
apa: Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Universität Paderborn.
bibtex: '@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for
Reconfigurable Heterogeneous Multi-Cores}, publisher={Universität Paderborn},
author={Rüthing, Christoph}, year={2014} }'
chicago: Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Universität Paderborn, 2014.
ieee: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Universität Paderborn, 2014.
mla: Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores. Universität Paderborn, 2014.
short: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
Heterogeneous Multi-Cores, Universität Paderborn, 2014.
date_created: 2017-10-17T12:41:59Z
date_updated: 2022-01-06T06:59:18Z
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
title: The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous
Multi-Cores
type: bachelorsthesis
user_id: '477'
year: '2014'
...
---
_id: '368'
abstract:
- lang: eng
text: We consider the problem of scheduling a number of jobs on $m$ identical processors
sharing a continuously divisible resource. Each job j comes with a resource requirement
r_j \in {0,1}. The job can be processed at full speed if granted its full resource
requirement. If receiving only an x-portion of r_j, it is processed at an x-fraction
of the full speed. Our goal is to find a resource assignment that minimizes the
makespan (i.e., the latest completion time). Variants of such problems, relating
the resource assignment of jobs to their \emph{processing speeds}, have been studied
under the term discrete-continuous scheduling. Known results are either very pessimistic
or heuristic in nature.In this paper, we suggest and analyze a slightly simplified
model. It focuses on the assignment of shared continuous resources to the processors.
The job assignment to processors and the ordering of the jobs have already been
fixed. It is shown that, even for unit size jobs, finding an optimal solution
is NP-hard if the number of processors is part of the input. Positive results
for unit size jobs include an efficient optimal algorithm for 2 processors. Moreover,
we prove that balanced schedules yield a 2-1/m-approximation for a fixed number
of processors. Such schedules are computed by our GreedyBalance algorithm, for
which the bound is tight.
author:
- first_name: Andre
full_name: Brinkmann, Andre
last_name: Brinkmann
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
- first_name: Lars
full_name: Nagel, Lars
last_name: Nagel
- first_name: Sören
full_name: Riechers, Sören
last_name: Riechers
- first_name: 'Tim '
full_name: 'Suess, Tim '
last_name: Suess
citation:
ama: 'Brinkmann A, Kling P, Meyer auf der Heide F, Nagel L, Riechers S, Suess T.
Scheduling Shared Continuous Resources on Many-Cores. In: Proceedings of the
26th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA).
; 2014:128-137. doi:10.1145/2612669.2612698'
apa: Brinkmann, A., Kling, P., Meyer auf der Heide, F., Nagel, L., Riechers, S.,
& Suess, T. (2014). Scheduling Shared Continuous Resources on Many-Cores.
Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures
(SPAA), 128–137. https://doi.org/10.1145/2612669.2612698
bibtex: '@inproceedings{Brinkmann_Kling_Meyer auf der Heide_Nagel_Riechers_Suess_2014,
title={Scheduling Shared Continuous Resources on Many-Cores}, DOI={10.1145/2612669.2612698},
booktitle={Proceedings of the 26th ACM Symposium on Parallelism in Algorithms
and Architectures (SPAA)}, author={Brinkmann, Andre and Kling, Peter and Meyer
auf der Heide, Friedhelm and Nagel, Lars and Riechers, Sören and Suess, Tim },
year={2014}, pages={128–137} }'
chicago: Brinkmann, Andre, Peter Kling, Friedhelm Meyer auf der Heide, Lars Nagel,
Sören Riechers, and Tim Suess. “Scheduling Shared Continuous Resources on Many-Cores.”
In Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures
(SPAA), 128–37, 2014. https://doi.org/10.1145/2612669.2612698.
ieee: 'A. Brinkmann, P. Kling, F. Meyer auf der Heide, L. Nagel, S. Riechers, and
T. Suess, “Scheduling Shared Continuous Resources on Many-Cores,” in Proceedings
of the 26th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA),
2014, pp. 128–137, doi: 10.1145/2612669.2612698.'
mla: Brinkmann, Andre, et al. “Scheduling Shared Continuous Resources on Many-Cores.”
Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures
(SPAA), 2014, pp. 128–37, doi:10.1145/2612669.2612698.
short: 'A. Brinkmann, P. Kling, F. Meyer auf der Heide, L. Nagel, S. Riechers, T.
Suess, in: Proceedings of the 26th ACM Symposium on Parallelism in Algorithms
and Architectures (SPAA), 2014, pp. 128–137.'
date_created: 2017-10-17T12:42:03Z
date_updated: 2022-01-06T06:59:30Z
ddc:
- '040'
department:
- _id: '63'
doi: 10.1145/2612669.2612698
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:17:38Z
date_updated: 2018-03-20T07:17:38Z
file_id: '1403'
file_name: 368-BKMNRS14.pdf
file_size: 485767
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:17:38Z
has_accepted_license: '1'
language:
- iso: eng
page: 128-137
project:
- _id: '1'
name: SFB 901
- _id: '16'
name: SFB 901 - Subprojekt C4
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and
Architectures (SPAA)
status: public
title: Scheduling Shared Continuous Resources on Many-Cores
type: conference
user_id: '15415'
year: '2014'
...
---
_id: '374'
abstract:
- lang: eng
text: Run-time reconfiguration provides an opportunity to increase performance,
reduce cost and improve energy efficiency in FPGA-based systems. However, run-time
reconfigurable systems are more complex to implement than static only systems.
This increases time to market, and introduces run-time overhead into the system.
Our research aims to raise the abstraction level to develop run-time reconfigurable
systems. We present operating system extensions which enable seamless integration
of run-time reconfigurable hardware threads into applications. To improve resource
utilization, the hardware threads are placed on a fine granularity tile grid.
We take advantage of a relocatable module placer targeting modern FPGA to manage
the reconfigurable area. The module placer accurately models the FPGA resources
to compute feasible placement locations for the hardware threads at run-time.
Finally, we evaluate our work by means of a case study that consists of a synthetic
application to validate the functionality and performance of the implementation.
The results show a reduction in reconfiguration time of up to 42% and more than
double resource utilization.
author:
- first_name: Alexander
full_name: Wold, Alexander
last_name: Wold
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
citation:
ama: 'Wold A, Agne A, Torresen J. Relocatable Hardware Threads in Run-Time Reconfigurable
Systems. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings
of the 10th International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications. LNCS. ; 2014:61-72. doi:10.1007/978-3-319-05960-0_6'
apa: 'Wold, A., Agne, A., & Torresen, J. (2014). Relocatable Hardware Threads
in Run-Time Reconfigurable Systems. In D. Goehringer, M. Santambrogio, J. P. Cardoso,
& K. Bertels (Eds.), Proceedings of the 10th International Symposium on
Reconfigurable Computing: Architectures, Tools, and Applications (pp. 61–72).
https://doi.org/10.1007/978-3-319-05960-0_6'
bibtex: '@inproceedings{Wold_Agne_Torresen_2014, series={LNCS}, title={Relocatable
Hardware Threads in Run-Time Reconfigurable Systems}, DOI={10.1007/978-3-319-05960-0_6},
booktitle={Proceedings of the 10th International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications}, author={Wold, Alexander and Agne, Andreas
and Torresen, Jim}, editor={Goehringer, Diana and Santambrogio, MarcoDomenico
and Cardoso, JoãoM.P. and Bertels, KoenEditors}, year={2014}, pages={61–72}, collection={LNCS}
}'
chicago: 'Wold, Alexander, Andreas Agne, and Jim Torresen. “Relocatable Hardware
Threads in Run-Time Reconfigurable Systems.” In Proceedings of the 10th International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications,
edited by Diana Goehringer, MarcoDomenico Santambrogio, JoãoM.P. Cardoso, and
Koen Bertels, 61–72. LNCS, 2014. https://doi.org/10.1007/978-3-319-05960-0_6.'
ieee: 'A. Wold, A. Agne, and J. Torresen, “Relocatable Hardware Threads in Run-Time
Reconfigurable Systems,” in Proceedings of the 10th International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications, 2014,
pp. 61–72.'
mla: 'Wold, Alexander, et al. “Relocatable Hardware Threads in Run-Time Reconfigurable
Systems.” Proceedings of the 10th International Symposium on Reconfigurable
Computing: Architectures, Tools, and Applications, edited by Diana Goehringer
et al., 2014, pp. 61–72, doi:10.1007/978-3-319-05960-0_6.'
short: 'A. Wold, A. Agne, J. Torresen, in: D. Goehringer, M. Santambrogio, J.P.
Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on
Reconfigurable Computing: Architectures, Tools, and Applications, 2014, pp. 61–72.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2022-01-06T06:59:32Z
ddc:
- '040'
doi: 10.1007/978-3-319-05960-0_6
editor:
- first_name: Diana
full_name: Goehringer, Diana
last_name: Goehringer
- first_name: MarcoDomenico
full_name: Santambrogio, MarcoDomenico
last_name: Santambrogio
- first_name: JoãoM.P.
full_name: Cardoso, JoãoM.P.
last_name: Cardoso
- first_name: Koen
full_name: Bertels, Koen
last_name: Bertels
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:15:59Z
date_updated: 2018-03-20T07:15:59Z
file_id: '1400'
file_name: 374-2014_wold_arc.pdf
file_size: 818625
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:15:59Z
has_accepted_license: '1'
page: 61-72
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: 'Proceedings of the 10th International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications'
series_title: LNCS
status: public
title: Relocatable Hardware Threads in Run-Time Reconfigurable Systems
type: conference
user_id: '15504'
year: '2014'
...
---
_id: '451'
abstract:
- lang: eng
text: We introduce the concept of budget games. Players choose a set of tasks and
each task has a certain demand on every resource in the game. Each resource has
a budget. If the budget is not enough to satisfy the sum of all demands, it has
to be shared between the tasks. We study strategic budget games, where the budget
is shared proportionally. We also consider a variant in which the order of the
strategic decisions influences the distribution of the budgets. The complexity
of the optimal solution as well as existence, complexity and quality of equilibria
are analysed. Finally, we show that the time an ordered budget game needs to convergence
towards an equilibrium may be exponential.
author:
- first_name: Maximilian
full_name: Drees, Maximilian
last_name: Drees
- first_name: Sören
full_name: Riechers, Sören
last_name: Riechers
- first_name: Alexander
full_name: Skopalik, Alexander
id: '40384'
last_name: Skopalik
citation:
ama: 'Drees M, Riechers S, Skopalik A. Budget-restricted utility games with ordered
strategic decisions. In: Lavi R, ed. Proceedings of the 7th International Symposium
on Algorithmic Game Theory (SAGT). Lecture Notes in Computer Science. ; 2014:110-121.
doi:10.1007/978-3-662-44803-8_10'
apa: Drees, M., Riechers, S., & Skopalik, A. (2014). Budget-restricted utility
games with ordered strategic decisions. In R. Lavi (Ed.), Proceedings of the
7th International Symposium on Algorithmic Game Theory (SAGT) (pp. 110–121).
https://doi.org/10.1007/978-3-662-44803-8_10
bibtex: '@inproceedings{Drees_Riechers_Skopalik_2014, series={Lecture Notes in Computer
Science}, title={Budget-restricted utility games with ordered strategic decisions},
DOI={10.1007/978-3-662-44803-8_10},
booktitle={Proceedings of the 7th International Symposium on Algorithmic Game
Theory (SAGT)}, author={Drees, Maximilian and Riechers, Sören and Skopalik, Alexander},
editor={Lavi, RonEditor}, year={2014}, pages={110–121}, collection={Lecture Notes
in Computer Science} }'
chicago: Drees, Maximilian, Sören Riechers, and Alexander Skopalik. “Budget-Restricted
Utility Games with Ordered Strategic Decisions.” In Proceedings of the 7th
International Symposium on Algorithmic Game Theory (SAGT), edited by Ron Lavi,
110–21. Lecture Notes in Computer Science, 2014. https://doi.org/10.1007/978-3-662-44803-8_10.
ieee: M. Drees, S. Riechers, and A. Skopalik, “Budget-restricted utility games with
ordered strategic decisions,” in Proceedings of the 7th International Symposium
on Algorithmic Game Theory (SAGT), 2014, pp. 110–121.
mla: Drees, Maximilian, et al. “Budget-Restricted Utility Games with Ordered Strategic
Decisions.” Proceedings of the 7th International Symposium on Algorithmic Game
Theory (SAGT), edited by Ron Lavi, 2014, pp. 110–21, doi:10.1007/978-3-662-44803-8_10.
short: 'M. Drees, S. Riechers, A. Skopalik, in: R. Lavi (Ed.), Proceedings of the
7th International Symposium on Algorithmic Game Theory (SAGT), 2014, pp. 110–121.'
date_created: 2017-10-17T12:42:20Z
date_updated: 2022-01-06T07:01:07Z
ddc:
- '040'
department:
- _id: '63'
- _id: '541'
doi: 10.1007/978-3-662-44803-8_10
editor:
- first_name: Ron
full_name: Lavi, Ron
last_name: Lavi
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:25:10Z
date_updated: 2018-03-16T11:25:10Z
file_id: '1344'
file_name: 451-DRS14.pdf
file_size: 283266
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:25:10Z
has_accepted_license: '1'
language:
- iso: eng
page: 110-121
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '16'
name: SFB 901 - Subproject C4
- _id: '7'
name: SFB 901 - Subproject A3
- _id: '2'
name: SFB 901 - Project Area A
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 7th International Symposium on Algorithmic Game Theory
(SAGT)
series_title: Lecture Notes in Computer Science
status: public
title: Budget-restricted utility games with ordered strategic decisions
type: conference
user_id: '477'
year: '2014'
...
---
_id: '460'
author:
- first_name: Robert
full_name: Mittendorf, Robert
last_name: Mittendorf
citation:
ama: Mittendorf R. Advanced AES-Key Recovery from Decayed RAM-Dumps Using Multi-Threading
and FPGAs. Universität Paderborn; 2014.
apa: Mittendorf, R. (2014). Advanced AES-key recovery from decayed RAM-dumps
using multi-threading and FPGAs. Universität Paderborn.
bibtex: '@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM-dumps
using multi-threading and FPGAs}, publisher={Universität Paderborn}, author={Mittendorf,
Robert}, year={2014} }'
chicago: Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM-Dumps
Using Multi-Threading and FPGAs. Universität Paderborn, 2014.
ieee: R. Mittendorf, Advanced AES-key recovery from decayed RAM-dumps using multi-threading
and FPGAs. Universität Paderborn, 2014.
mla: Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM-Dumps Using
Multi-Threading and FPGAs. Universität Paderborn, 2014.
short: R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM-Dumps Using Multi-Threading
and FPGAs, Universität Paderborn, 2014.
date_created: 2017-10-17T12:42:21Z
date_updated: 2022-01-06T07:01:14Z
project:
- _id: '1'
name: SFB 901
- _id: '13'
name: SFB 901 - Subprojekt C1
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
title: Advanced AES-key recovery from decayed RAM-dumps using multi-threading and
FPGAs
type: mastersthesis
user_id: '15504'
year: '2014'
...
---
_id: '466'
author:
- first_name: Marcel
full_name: Brand, Marcel
last_name: Brand
citation:
ama: Brand M. A Generalized Loop Accelerator Implemented as a Coarse Grained
Array. Universität Paderborn; 2014.
apa: Brand, M. (2014). A generalized loop accelerator implemented as a coarse
grained array. Universität Paderborn.
bibtex: '@book{Brand_2014, title={A generalized loop accelerator implemented as
a coarse grained array}, publisher={Universität Paderborn}, author={Brand, Marcel},
year={2014} }'
chicago: Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse
Grained Array. Universität Paderborn, 2014.
ieee: M. Brand, A generalized loop accelerator implemented as a coarse grained
array. Universität Paderborn, 2014.
mla: Brand, Marcel. A Generalized Loop Accelerator Implemented as a Coarse Grained
Array. Universität Paderborn, 2014.
short: M. Brand, A Generalized Loop Accelerator Implemented as a Coarse Grained
Array, Universität Paderborn, 2014.
date_created: 2017-10-17T12:42:22Z
date_updated: 2022-01-06T07:01:17Z
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
title: A generalized loop accelerator implemented as a coarse grained array
type: mastersthesis
user_id: '477'
year: '2014'
...
---
_id: '431'
abstract:
- lang: eng
text: In meiner Dissertation besch{\"a}ftige ich mich mit dem Entwurf und der Analyse
energieeffizienter Schedulingalgorithmen, insbesondere f{\"u}r sogenannte Speed-Scaling
Modelle. Diese stellen das theoretische Pendant von Techniken wie AMDs PowerNOW!
und Intels SpeedStep dar, welche es erlauben die Geschwindigkeit von Prozessoren
zur Laufzeit an die derzeitigen Bedingungen anzupassen. Theoretische Untersuchungen
solcher Modelle sind auf eine Arbeit von Yao, Demers und Shenker (FOCS'95) zur{\"u}ckzuf{\"u}hren.
Hier kombinieren die Autoren klassisches Deadline-Scheduling mit einem Prozessor
der Speed-Scaling beherrscht. Es gilt Jobs verschiedener Gr{\"o}ße fristgerecht
abzuarbeiten und die dabei verwendete Energie zu minimieren. Der Energieverbrauch
des Prozessors wird durch eine konvexe Funktion $\POW\colon\R_{\geq0}\to\R_{\geq0}$
modelliert, welche die Geschwindigkeit auf den Energieverbrauch abbildet.Meine
Dissertation betrachtet verschiedene Varianten des urspr{\"u}nglichen Speed-Scaling
Modells. Forschungsrelevante Ergebnisse sind in den Kapiteln 3 bis 6 zu finden
und erstrecken sich {\"u}ber die im Folgenden beschriebenen Aspekte:- Kapitel
3 und 4 betrachten verschiedene \emph{Price-Collecting} Varianten des Originalproblems.
Hier d{\"u}rfen einzelne Deadlines verfehlt werden, sofern eine jobabh{\"a}ngige
Strafe gezahlt wird. Ich entwerfe insbesondere Online-Algorithmen mit einer beweisbar
guten Competitiveness. Dabei liefern meine Ergebnisse substantielle Verbesserungen
bestehender Arbeiten und erweitern diese unter Anderem auf Szenarien mit mehreren
Prozessoren.- In Kapitel 5 wird statt des klassischen Deadline-Schedulings eine
Linearkombination der durchschnittlichen Antwortzeit und des Energieverbrauchs
betrachtet. Die Frage, ob dieses Problem NP-schwer ist, stellt eine der zentralen
Forschungsfragen in diesem Gebiet dar. F{\"u}r eine relaxierte Form dieser Frage
entwerfe ich einen effizienter Algorithmus und beweise seine Optimalit{\"a}t.-
Das letzte Kapitel betrachtet ein Modell, welches – auf den ersten Blick – nicht
direkt zur Speed-Scaling Literatur z{\"a}hlt. Hier geht es stattdessen um ein
allgemeines Resource-Constrained Scheduling, in dem sich die Prozessoren zusammen
eine gemeinsame, beliebig aufteilbare Ressource teilen. Ich untersuche die Komplexit{\"a}t
des Problems und entwerfe verschiedene Approximationsalgorithmen.
author:
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
citation:
ama: Kling P. Energy-Efficient Scheduling Algorithms. Universität Paderborn;
2014.
apa: Kling, P. (2014). Energy-efficient Scheduling Algorithms. Universität
Paderborn.
bibtex: '@book{Kling_2014, title={Energy-efficient Scheduling Algorithms}, publisher={Universität
Paderborn}, author={Kling, Peter}, year={2014} }'
chicago: Kling, Peter. Energy-Efficient Scheduling Algorithms. Universität
Paderborn, 2014.
ieee: P. Kling, Energy-efficient Scheduling Algorithms. Universität Paderborn,
2014.
mla: Kling, Peter. Energy-Efficient Scheduling Algorithms. Universität Paderborn,
2014.
short: P. Kling, Energy-Efficient Scheduling Algorithms, Universität Paderborn,
2014.
date_created: 2017-10-17T12:42:15Z
date_updated: 2022-01-06T07:00:52Z
ddc:
- '040'
department:
- _id: '63'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:31:29Z
date_updated: 2018-03-16T11:31:29Z
file_id: '1356'
file_name: 431-Peter_Kling_PhDThesis_01.pdf
file_size: 792106
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:31:29Z
has_accepted_license: '1'
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
title: Energy-efficient Scheduling Algorithms
type: dissertation
user_id: '477'
year: '2014'
...
---
_id: '435'
abstract:
- lang: eng
text: We give a polynomial time algorithm to compute an optimal energy and fractional
weighted flow trade-off schedule for a speed-scalable processor with discrete
speeds.Our algorithm uses a geometric approach that is based on structural properties
obtained from a primal-dual formulation of the problem.
author:
- first_name: Antonios
full_name: Antoniadis, Antonios
last_name: Antoniadis
- first_name: Neal
full_name: Barcelo, Neal
last_name: Barcelo
- first_name: Mario
full_name: Consuegra, Mario
last_name: Consuegra
- first_name: Peer
full_name: Kling, Peer
last_name: Kling
- first_name: Michael
full_name: Nugent, Michael
last_name: Nugent
- first_name: Kirk
full_name: Pruhs, Kirk
last_name: Pruhs
- first_name: Michele
full_name: Scquizzato, Michele
last_name: Scquizzato
citation:
ama: 'Antoniadis A, Barcelo N, Consuegra M, et al. Efficient Computation of Optimal
Energy and Fractional Weighted Flow Trade-off Schedules. In: Proceedings of
the 31st Symposium on Theoretical Aspects of Computer Science (STACS). LIPIcs.
; 2014:63--74. doi:10.4230/LIPIcs.STACS.2014.63'
apa: Antoniadis, A., Barcelo, N., Consuegra, M., Kling, P., Nugent, M., Pruhs, K.,
& Scquizzato, M. (2014). Efficient Computation of Optimal Energy and Fractional
Weighted Flow Trade-off Schedules. In Proceedings of the 31st Symposium on
Theoretical Aspects of Computer Science (STACS) (pp. 63--74). https://doi.org/10.4230/LIPIcs.STACS.2014.63
bibtex: '@inproceedings{Antoniadis_Barcelo_Consuegra_Kling_Nugent_Pruhs_Scquizzato_2014,
series={LIPIcs}, title={Efficient Computation of Optimal Energy and Fractional
Weighted Flow Trade-off Schedules}, DOI={10.4230/LIPIcs.STACS.2014.63},
booktitle={Proceedings of the 31st Symposium on Theoretical Aspects of Computer
Science (STACS)}, author={Antoniadis, Antonios and Barcelo, Neal and Consuegra,
Mario and Kling, Peer and Nugent, Michael and Pruhs, Kirk and Scquizzato, Michele},
year={2014}, pages={63--74}, collection={LIPIcs} }'
chicago: Antoniadis, Antonios, Neal Barcelo, Mario Consuegra, Peer Kling, Michael
Nugent, Kirk Pruhs, and Michele Scquizzato. “Efficient Computation of Optimal
Energy and Fractional Weighted Flow Trade-off Schedules.” In Proceedings of
the 31st Symposium on Theoretical Aspects of Computer Science (STACS), 63--74.
LIPIcs, 2014. https://doi.org/10.4230/LIPIcs.STACS.2014.63.
ieee: A. Antoniadis et al., “Efficient Computation of Optimal Energy and
Fractional Weighted Flow Trade-off Schedules,” in Proceedings of the 31st Symposium
on Theoretical Aspects of Computer Science (STACS), 2014, pp. 63--74.
mla: Antoniadis, Antonios, et al. “Efficient Computation of Optimal Energy and Fractional
Weighted Flow Trade-off Schedules.” Proceedings of the 31st Symposium on Theoretical
Aspects of Computer Science (STACS), 2014, pp. 63--74, doi:10.4230/LIPIcs.STACS.2014.63.
short: 'A. Antoniadis, N. Barcelo, M. Consuegra, P. Kling, M. Nugent, K. Pruhs,
M. Scquizzato, in: Proceedings of the 31st Symposium on Theoretical Aspects of
Computer Science (STACS), 2014, pp. 63--74.'
date_created: 2017-10-17T12:42:16Z
date_updated: 2022-01-06T07:00:58Z
ddc:
- '040'
department:
- _id: '63'
doi: 10.4230/LIPIcs.STACS.2014.63
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:30:23Z
date_updated: 2018-03-16T11:30:23Z
file_id: '1354'
file_name: 435-Kling_C2_STACS2014.pdf
file_size: 525851
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:30:23Z
has_accepted_license: '1'
language:
- iso: eng
page: 63--74
project:
- _id: '1'
name: SFB 901
- _id: '16'
name: SFB 901 - Subprojekt C4
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 31st Symposium on Theoretical Aspects of Computer
Science (STACS)
series_title: LIPIcs
status: public
title: Efficient Computation of Optimal Energy and Fractional Weighted Flow Trade-off
Schedules
type: conference
user_id: '477'
year: '2014'
...