@inproceedings{9913, abstract = {{Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.}}, author = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Applied Reconfigurable Computing}}, editor = {{Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}}, isbn = {{978-3-030-17227-5}}, location = {{Darmstadt, Germany}}, pages = {{127--136}}, publisher = {{Springer International Publishing}}, title = {{{Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}}}, doi = {{10.1007/978-3-030-17227-5_10}}, volume = {{11444}}, year = {{2019}}, } @inproceedings{14898, author = {{Schubert, Philipp and Leer, Richard and Hermann, Ben and Bodden, Eric}}, booktitle = {{Proceedings of the 8th ACM SIGPLAN International Workshop on State Of the Art in Program Analysis - SOAP 2019}}, isbn = {{9781450367202}}, title = {{{Know your analysis: how instrumentation aids understanding static analysis}}}, doi = {{10.1145/3315568.3329965}}, year = {{2019}}, } @inproceedings{2479, author = {{Mohr, Felix and Wever, Marcel Dominik and Hüllermeier, Eyke and Faez, Amin}}, booktitle = {{SCC}}, location = {{San Francisco, CA, USA}}, publisher = {{IEEE}}, title = {{{(WIP) Towards the Automated Composition of Machine Learning Services}}}, doi = {{10.1109/SCC.2018.00039}}, year = {{2018}}, } @inproceedings{2857, author = {{Mohr, Felix and Lettmann, Theodor and Hüllermeier, Eyke and Wever, Marcel Dominik}}, booktitle = {{Proceedings of the 1st ICAPS Workshop on Hierarchical Planning}}, location = {{Delft, Netherlands}}, pages = {{31--39}}, publisher = {{AAAI}}, title = {{{Programmatic Task Network Planning}}}, year = {{2018}}, } @inproceedings{2471, author = {{Mohr, Felix and Wever, Marcel Dominik and Hüllermeier, Eyke}}, booktitle = {{SCC}}, location = {{San Francisco, CA, USA}}, publisher = {{IEEE Computer Society}}, title = {{{On-The-Fly Service Construction with Prototypes}}}, doi = {{10.1109/SCC.2018.00036}}, year = {{2018}}, } @misc{3320, author = {{Rautenberg, Kai}}, publisher = {{Universität Paderborn}}, title = {{{Korrektheitsbeweise für Muster von Servicekompositionen}}}, year = {{2018}}, } @inproceedings{3373, abstract = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}}, author = {{Hansmeier, Tim and Platzner, Marco and Andrews, David}}, booktitle = {{ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}}, isbn = {{9783319788890}}, issn = {{0302-9743}}, location = {{Santorini, Greece}}, pages = {{153--165}}, publisher = {{Springer International Publishing}}, title = {{{An FPGA/HMC-Based Accelerator for Resolution Proof Checking}}}, doi = {{10.1007/978-3-319-78890-6_13}}, volume = {{10824}}, year = {{2018}}, } @article{3402, abstract = {{In machine learning, so-called nested dichotomies are utilized as a reduction technique, i.e., to decompose a multi-class classification problem into a set of binary problems, which are solved using a simple binary classifier as a base learner. The performance of the (multi-class) classifier thus produced strongly depends on the structure of the decomposition. In this paper, we conduct an empirical study, in which we compare existing heuristics for selecting a suitable structure in the form of a nested dichotomy. Moreover, we propose two additional heuristics as natural completions. One of them is the Best-of-K heuristic, which picks the (presumably) best among K randomly generated nested dichotomies. Surprisingly, and in spite of its simplicity, it turns out to outperform the state of the art.}}, author = {{Melnikov, Vitalik and Hüllermeier, Eyke}}, issn = {{1573-0565}}, journal = {{Machine Learning}}, title = {{{On the effectiveness of heuristics for learning nested dichotomies: an empirical analysis}}}, doi = {{10.1007/s10994-018-5733-1}}, year = {{2018}}, } @inproceedings{3414, abstract = {{Over the years, Design by Contract (DbC) has evolved as a powerful concept for program documentation, testing, and verification. Contracts formally specify assertions on (mostly) object-oriented programs: pre- and postconditions of methods, class invariants, allowed call orders, etc. Missing in the long list of properties specifiable by contracts are, however, method correlations: DbC languages fall short on stating assertions relating methods. In this paper, we propose the novel concept of inter-method contract, allowing precisely for expressing method correlations.We present JMC as a language for specifying and JMCTest as a tool for dynamically checking inter-method contracts on Java programs. JMCTest fully automatically generates objects on which the contracted methods are called and the validity of the contract is checked. Using JMCTest, we detected that large Java code bases (e.g. JBoss, Java RT) frequently violate standard inter-method contracts. In comparison to other verification tools inspecting (some) inter-method contracts, JMCTest can find bugs that remain undetected by those tools.}}, author = {{Börding, Paul and Haltermann, Jan Frederik and Jakobs, Marie-Christine and Wehrheim, Heike}}, booktitle = {{Proceedings of the IFIP International Conference on Testing Software and Systems (ICTSS 2018)}}, location = {{Cádiz, Spain}}, pages = {{39----55}}, publisher = {{Springer}}, title = {{{JMCTest: Automatically Testing Inter-Method Contracts in Java}}}, volume = {{11146}}, year = {{2018}}, } @article{3510, abstract = {{Automated machine learning (AutoML) seeks to automatically select, compose, and parametrize machine learning algorithms, so as to achieve optimal performance on a given task (dataset). Although current approaches to AutoML have already produced impressive results, the field is still far from mature, and new techniques are still being developed. In this paper, we present ML-Plan, a new approach to AutoML based on hierarchical planning. To highlight the potential of this approach, we compare ML-Plan to the state-of-the-art frameworks Auto-WEKA, auto-sklearn, and TPOT. In an extensive series of experiments, we show that ML-Plan is highly competitive and often outperforms existing approaches.}}, author = {{Mohr, Felix and Wever, Marcel Dominik and Hüllermeier, Eyke}}, issn = {{1573-0565}}, journal = {{Machine Learning}}, keywords = {{AutoML, Hierarchical Planning, HTN planning, ML-Plan}}, location = {{Dublin, Ireland}}, pages = {{1495--1515}}, publisher = {{Springer}}, title = {{{ML-Plan: Automated Machine Learning via Hierarchical Planning}}}, doi = {{10.1007/s10994-018-5735-z}}, year = {{2018}}, } @inproceedings{3552, author = {{Mohr, Felix and Wever, Marcel Dominik and Hüllermeier, Eyke}}, booktitle = {{Proceedings of the Symposium on Intelligent Data Analysis}}, location = {{‘s-Hertogenbosch, the Netherlands}}, title = {{{Reduction Stumps for Multi-Class Classification}}}, doi = {{10.1007/978-3-030-01768-2_19}}, year = {{2018}}, } @unpublished{3586, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, booktitle = {{Third Workshop on Approximate Computing (AxC 2018)}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{6}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, year = {{2018}}, } @phdthesis{3720, abstract = {{Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.}}, author = {{Ho, Nam}}, pages = {{139}}, publisher = {{Universität Paderborn}}, title = {{{FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}}}, doi = {{10.17619/UNIPB/1-376}}, year = {{2018}}, } @inproceedings{3852, abstract = {{In automated machine learning (AutoML), the process of engineering machine learning applications with respect to a specific problem is (partially) automated. Various AutoML tools have already been introduced to provide out-of-the-box machine learning functionality. More specifically, by selecting machine learning algorithms and optimizing their hyperparameters, these tools produce a machine learning pipeline tailored to the problem at hand. Except for TPOT, all of these tools restrict the maximum number of processing steps of such a pipeline. However, as TPOT follows an evolutionary approach, it suffers from performance issues when dealing with larger datasets. In this paper, we present an alternative approach leveraging a hierarchical planning to configure machine learning pipelines that are unlimited in length. We evaluate our approach and find its performance to be competitive with other AutoML tools, including TPOT.}}, author = {{Wever, Marcel Dominik and Mohr, Felix and Hüllermeier, Eyke}}, booktitle = {{ICML 2018 AutoML Workshop}}, keywords = {{automated machine learning, complex pipelines, hierarchical planning}}, location = {{Stockholm, Sweden}}, title = {{{ML-Plan for Unlimited-Length Machine Learning Pipelines}}}, year = {{2018}}, } @unpublished{2711, abstract = {{In recent years, researchers have developed a number of tools to conduct taint analysis of Android applications. While all the respective papers aim at providing a thorough empirical evaluation, comparability is hindered by varying or unclear evaluation targets. Sometimes, the apps used for evaluation are not precisely described. In other cases, authors use an established benchmark but cover it only partially. In yet other cases, the evaluations differ in terms of the data leaks searched for, or lack a ground truth to compare against. All those limitations make it impossible to truly compare the tools based on those published evaluations. We thus present ReproDroid, a framework allowing the accurate comparison of Android taint analysis tools. ReproDroid supports researchers in inferring the ground truth for data leaks in apps, in automatically applying tools to benchmarks, and in evaluating the obtained results. We use ReproDroid to comparatively evaluate on equal grounds the six prominent taint analysis tools Amandroid, DIALDroid, DidFail, DroidSafe, FlowDroid and IccTA. The results are largely positive although four tools violate some promises concerning features and accuracy. Finally, we contribute to the area of unbiased benchmarking with a new and improved version of the open test suite DroidBench.}}, author = {{Pauck, Felix and Bodden, Eric and Wehrheim, Heike}}, booktitle = {{arXiv:1804.02903}}, title = {{{Do Android Taint Analysis Tools Keep their Promises?}}}, year = {{2018}}, } @unpublished{1165, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{4th Workshop On Approximate Computing (WAPCO 2018)}}, title = {{{Making the Case for Proof-carrying Approximate Circuits}}}, year = {{2018}}, } @inproceedings{2109, abstract = {{In multinomial classification, reduction techniques are commonly used to decompose the original learning problem into several simpler problems. For example, by recursively bisecting the original set of classes, so-called nested dichotomies define a set of binary classification problems that are organized in the structure of a binary tree. In contrast to the existing one-shot heuristics for constructing nested dichotomies and motivated by recent work on algorithm configuration, we propose a genetic algorithm for optimizing the structure of such dichotomies. A key component of this approach is the proposed genetic representation that facilitates the application of standard genetic operators, while still supporting the exchange of partial solutions under recombination. We evaluate the approach in an extensive experimental study, showing that it yields classifiers with superior generalization performance.}}, author = {{Wever, Marcel Dominik and Mohr, Felix and Hüllermeier, Eyke}}, booktitle = {{Proceedings of the Genetic and Evolutionary Computation Conference, GECCO 2018, Kyoto, Japan, July 15-19, 2018}}, keywords = {{Classification, Hierarchical Decomposition, Indirect Encoding}}, location = {{Kyoto, Japan}}, publisher = {{ACM}}, title = {{{Ensembles of Evolved Nested Dichotomies for Classification}}}, doi = {{10.1145/3205455.3205562}}, year = {{2018}}, } @unpublished{17713, author = {{Wever, Marcel Dominik and Mohr, Felix and Hüllermeier, Eyke}}, publisher = {{Arxiv}}, title = {{{Automated Multi-Label Classification based on ML-Plan}}}, year = {{2018}}, } @unpublished{17714, author = {{Mohr, Felix and Wever, Marcel Dominik and Hüllermeier, Eyke}}, title = {{{Automated machine learning service composition}}}, year = {{2018}}, } @inbook{2322, abstract = {{The vision of On-The-Fly Computing is an automatic composition of existing software services. Based on natural language software descriptions, end users will receive compositions tailored to their needs. For this reason, the quality of the initial software service description strongly determines whether a software composition really meets the expectations of end users. In this paper, we expose open NLP challenges needed to be faced for service composition in On-The-Fly Computing.}}, author = {{Bäumer, Frederik Simon and Geierhos, Michaela}}, booktitle = {{Proceedings of the 23rd International Conference on Natural Language and Information Systems}}, editor = {{Silberztein, Max and Atigui, Faten and Kornyshova, Elena and Métais, Elisabeth and Meziane, Farid }}, isbn = {{978-3-319-91946-1}}, keywords = {{Requirements Extraction, Temporal Reordering of Software Functions, Inaccuracy Compensation}}, location = {{Paris, France}}, pages = {{509--513}}, publisher = {{Springer}}, title = {{{How to Deal with Inaccurate Service Descriptions in On-The-Fly Computing: Open Challenges}}}, doi = {{10.1007/978-3-319-91947-8_53}}, volume = {{10859}}, year = {{2018}}, }