[{"author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"}],"date_updated":"2023-09-26T13:25:38Z","doi":"10.1007/978-3-319-26408-0_13","publication_status":"published","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"citation":{"apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., &#38; Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, &#38; D. Ziener (Eds.), <i>FPGAs for Software Programmers</i> (pp. 227–244). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>","mla":"Agne, Andreas, et al. “ReconOS.” <i>FPGAs for Software Programmers</i>, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. <i>FPGAs for Software Programmers</i>. Springer International Publishing; 2016:227-244. doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In <i>FPGAs for Software Programmers</i>, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>.","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in <i>FPGAs for Software Programmers</i>, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244."},"page":"227-244","place":"Cham","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"29","type":"book_chapter","status":"public","editor":[{"first_name":"Dirk","full_name":"Koch, Dirk","last_name":"Koch"},{"first_name":"Frank","full_name":"Hannig, Frank","last_name":"Hannig"},{"first_name":"Daniel","last_name":"Ziener","full_name":"Ziener, Daniel"}],"date_created":"2017-07-26T15:07:06Z","publisher":"Springer International Publishing","title":"ReconOS","quality_controlled":"1","year":"2016","language":[{"iso":"eng"}],"publication":"FPGAs for Software Programmers","abstract":[{"text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.","lang":"eng"}]},{"has_accepted_license":"1","citation":{"ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: <i>Self-Aware Computing Systems</i>. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in <i>Self-aware Computing Systems</i>, Cham: Springer International Publishing, 2016, pp. 145–165.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In <i>Self-Aware Computing Systems</i>, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2016). Self-aware Compute Nodes. In <i>Self-aware Computing Systems</i> (pp. 145–165). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">https://doi.org/10.1007/978-3-319-39675-0_8</a>","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” <i>Self-Aware Computing Systems</i>, Springer International Publishing, 2016, pp. 145–65, doi:<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-39675-0_8\">10.1007/978-3-319-39675-0_8</a>}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }"},"page":"145-165","place":"Cham","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Lösch","id":"43646","full_name":"Lösch, Achim","first_name":"Achim"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_updated":"2023-09-26T13:27:44Z","doi":"10.1007/978-3-319-39675-0_8","type":"book_chapter","status":"public","user_id":"15278","series_title":"Natural Computing Series (NCS)","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"156","file_date_updated":"2018-11-14T13:20:32Z","quality_controlled":"1","year":"2016","date_created":"2017-10-17T12:41:22Z","publisher":"Springer International Publishing","title":"Self-aware Compute Nodes","publication":"Self-aware Computing Systems","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_id":"5613","access_level":"closed","file_name":"chapter8.pdf","file_size":833054,"date_created":"2018-11-14T13:20:32Z","creator":"aloesch","date_updated":"2018-11-14T13:20:32Z"}],"abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["040"]},{"year":"2015","citation":{"ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>.","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>","short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7, doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>."},"page":"1-7","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","doi":"10.1109/AHS.2015.7231178","date_updated":"2022-01-06T06:50:49Z","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"full_name":"Ahmed, Abdullah Fathi","last_name":"Ahmed","first_name":"Abdullah Fathi"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_created":"2019-07-10T11:18:00Z","status":"public","type":"conference","publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"language":[{"iso":"eng"}],"project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"10673","user_id":"3118","department":[{"_id":"78"}]},{"keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"],"language":[{"iso":"eng"}],"_id":"10674","project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"department":[{"_id":"78"}],"user_id":"3118","status":"public","publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","type":"conference","title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms","doi":"10.1109/FPL.2014.6927437","date_updated":"2022-01-06T06:50:49Z","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:18:01Z","year":"2014","page":"1-4","citation":{"ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>.","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>","short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>"}},{"has_accepted_license":"1","quality_controlled":"1","issue":"8, Part B","year":"2014","citation":{"apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>"},"intvolume":"        38","page":"911-919","publisher":"Elsevier","date_updated":"2023-09-26T13:33:06Z","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Hendrik","last_name":"Hangmann","full_name":"Hangmann, Hendrik"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2017-10-17T12:42:02Z","volume":38,"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","doi":"10.1016/j.micpro.2013.12.001","type":"journal_article","publication":"Microprocessors and Microsystems","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","access_level":"closed","file_id":"1408","file_name":"363-plessl13_micpro.pdf","file_size":1499996,"creator":"florida","date_created":"2018-03-20T07:20:31Z","date_updated":"2018-03-20T07:20:31Z"}],"status":"public","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"363","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"ddc":["040"],"file_date_updated":"2018-03-20T07:20:31Z","language":[{"iso":"eng"}]},{"volume":7,"author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"first_name":"Achim","last_name":"Lösch","full_name":"Lösch, Achim","id":"43646"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_updated":"2023-09-26T13:33:31Z","doi":"10.1145/2617596","has_accepted_license":"1","intvolume":"         7","citation":{"mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>"},"department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"user_id":"15278","_id":"365","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"file_date_updated":"2018-03-20T07:19:19Z","article_number":"13","type":"journal_article","status":"public","date_created":"2017-10-17T12:42:03Z","publisher":"ACM","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","issue":"2","quality_controlled":"1","year":"2014","language":[{"iso":"eng"}],"ddc":["040"],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","file":[{"date_created":"2018-03-20T07:19:19Z","creator":"florida","date_updated":"2018-03-20T07:19:19Z","file_id":"1406","file_name":"365-plessl14_trets_01.pdf","access_level":"closed","file_size":916052,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}]},{"status":"public","type":"journal_article","file_date_updated":"2018-03-20T07:31:40Z","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"328","citation":{"ieee":"A. Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i> 34, no. 1 (2014): 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>.","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>. 2014;34(1):60-71. doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i>, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &#38; Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>, <i>34</i>(1), 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>"},"page":"60-71","intvolume":"        34","has_accepted_license":"1","doi":"10.1109/MM.2013.110","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Ariane","last_name":"Keller","full_name":"Keller, Ariane"},{"full_name":"Lübbers, Enno","last_name":"Lübbers","first_name":"Enno"},{"first_name":"Bernhard","last_name":"Plattner","full_name":"Plattner, Bernhard"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"}],"volume":34,"date_updated":"2023-09-26T13:32:31Z","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-20T07:31:40Z","date_created":"2018-03-20T07:31:40Z","creator":"florida","file_size":1877185,"access_level":"closed","file_id":"1426","file_name":"328-plessl14_micro_01.pdf"}],"abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"publication":"IEEE Micro","language":[{"iso":"eng"}],"ddc":["040"],"year":"2014","issue":"1","quality_controlled":"1","title":"ReconOS - An Operating System Approach for Reconfigurable Computing","date_created":"2017-10-17T12:41:55Z","publisher":"IEEE"},{"status":"public","type":"conference","file_date_updated":"2018-03-15T06:48:32Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"615","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"page":"1-8","citation":{"ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"has_accepted_license":"1","doi":"10.1109/ReConFig.2012.6416745","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Hangmann, Hendrik","last_name":"Hangmann","first_name":"Hendrik"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:42:26Z","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_id":"1246","access_level":"closed","file_name":"615-ReConFig12_01.pdf","file_size":730144,"date_created":"2018-03-15T06:48:32Z","creator":"florida","date_updated":"2018-03-15T06:48:32Z"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","language":[{"iso":"eng"}],"ddc":["040"],"year":"2012","quality_controlled":"1","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","date_created":"2017-10-17T12:42:51Z","publisher":"IEEE"},{"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","publisher":"IEEE","date_created":"2017-10-17T12:42:47Z","year":"2012","quality_controlled":"1","ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort."}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_id":"1257","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed","file_size":371235,"date_created":"2018-03-15T08:33:18Z","creator":"florida","date_updated":"2018-03-15T08:33:18Z"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","author":[{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Schmitz, Henning","last_name":"Schmitz","first_name":"Henning"}],"page":"1-8","citation":{"bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>"},"has_accepted_license":"1","file_date_updated":"2018-03-15T08:33:18Z","_id":"591","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","type":"conference"},{"ddc":["040"],"file_date_updated":"2018-03-15T08:14:17Z","language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-03-15T08:14:17Z","creator":"florida","date_updated":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed","file_id":"1249","file_size":146789}],"status":"public","type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","title":"Hardware/Software Platform for Self-aware Compute Nodes","date_updated":"2023-09-26T13:41:36Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_created":"2017-10-17T12:42:50Z","year":"2012","citation":{"ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9."},"page":"8-9","has_accepted_license":"1","quality_controlled":"1"},{"date_created":"2017-10-17T12:42:51Z","author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"publisher":"IEEE","date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","has_accepted_license":"1","quality_controlled":"1","page":"559-562","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>"},"year":"2012","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"612","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T06:49:03Z","ddc":["040"],"publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","type":"conference","status":"public","file":[{"date_created":"2018-03-15T06:49:03Z","creator":"florida","date_updated":"2018-03-15T06:49:03Z","access_level":"closed","file_name":"612-ruething_fpl12.pdf","file_id":"1247","file_size":202923,"content_type":"application/pdf","relation":"main_file","success":1}],"abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}]},{"title":"Hardware Virtualization on Dynamically Reconfigurable Embedded Processors","doi":"10.4018/978-1-60960-086-0","date_updated":"2022-01-06T06:55:22Z","publisher":"IGI Global","author":[{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2018-04-03T15:11:16Z","year":"2011","place":"Hershey, PA, USA","citation":{"apa":"Plessl, C., &#38; Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui &#38; H.-M. Hanisch (Eds.), <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>","bibtex":"@inbook{Plessl_Platzner_2011, place={Hershey, PA, USA}, title={Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}, DOI={<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>}, booktitle={Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}, publisher={IGI Global}, author={Plessl, Christian and Platzner, Marco}, editor={Khalgui, Mohamed and Hanisch, Hans-MichaelEditors}, year={2011} }","short":"C. Plessl, M. Platzner, in: M. Khalgui, H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, Hershey, PA, USA, 2011.","mla":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>.","chicago":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. <a href=\"https://doi.org/10.4018/978-1-60960-086-0\">https://doi.org/10.4018/978-1-60960-086-0</a>.","ieee":"C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.","ama":"Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. <i>Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility</i>. Hershey, PA, USA: IGI Global; 2011. doi:<a href=\"https://doi.org/10.4018/978-1-60960-086-0\">10.4018/978-1-60960-086-0</a>"},"publication_identifier":{"isbn":["978-1-60960-086-0"]},"_id":"2202","project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"24135","editor":[{"first_name":"Mohamed","full_name":"Khalgui, Mohamed","last_name":"Khalgui"},{"first_name":"Hans-Michael","full_name":"Hanisch, Hans-Michael","last_name":"Hanisch"}],"status":"public","publication":"Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility","type":"book_chapter"},{"abstract":[{"text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"file":[{"date_created":"2018-03-14T13:49:39Z","creator":"florida","date_updated":"2018-03-14T13:49:39Z","file_name":"656-2011_happe_reconfig.pdf","file_id":"1220","access_level":"closed","file_size":502244,"content_type":"application/pdf","relation":"main_file","success":1}],"status":"public","type":"conference","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","ddc":["040"],"file_date_updated":"2018-03-14T13:49:39Z","language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"656","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"year":"2011","citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2011, pp. 55–60, doi: <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. IEEE, 2011. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2011:55-60. doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2011, pp. 55–60, doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","apa":"Happe, M., Agne, A., &#38; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>"},"page":"55-60","has_accepted_license":"1","quality_controlled":"1","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","doi":"10.1109/ReConFig.2011.59","publisher":"IEEE","date_updated":"2023-09-26T13:46:08Z","date_created":"2017-10-17T12:42:59Z","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}]}]