[{"date_created":"2025-11-10T08:31:47Z","author":[{"first_name":"Babak","full_name":"Sadiye, Babak","id":"93634","last_name":"Sadiye"},{"first_name":"Mohammed","id":"47944","full_name":"Iftekhar, Mohammed","last_name":"Iftekhar"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"J. Christoph","id":"37144","full_name":"Scheytt, J. Christoph","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt"}],"date_updated":"2025-11-10T08:38:07Z","publisher":"IEEE","doi":"10.1109/TVLSI.2025.3625787","title":"60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design","publication_identifier":{"issn":["1063-8210"]},"publication_status":"published","citation":{"ieee":"B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025, doi: <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>.","chicago":"Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, 2025. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>.","ama":"Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. Published online 2025. doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>","apa":"Sadiye, B., Iftekhar, M., Müller, W., &#38; Scheytt, J. C. (2025). 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>. <a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">https://doi.org/10.1109/TVLSI.2025.3625787</a>","bibtex":"@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","short":"B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).","mla":"Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” <i>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/TVLSI.2025.3625787\">10.1109/TVLSI.2025.3625787</a>."},"year":"2025","department":[{"_id":"58"}],"user_id":"93634","_id":"62148","project":[{"_id":"325","name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing"}],"language":[{"iso":"eng"}],"publication":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","type":"journal_article","status":"public"},{"author":[{"last_name":"Iftekhar","full_name":"Iftekhar, Mohammed","id":"47944","first_name":"Mohammed"},{"first_name":"Babak","id":"93634","full_name":"Sadiye, Babak","last_name":"Sadiye"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","id":"37144","full_name":"Scheytt, J. Christoph","first_name":"J. Christoph"}],"date_created":"2025-11-07T10:41:45Z","date_updated":"2025-11-20T10:34:13Z","doi":"10.1109/NorCAS66540.2025.11231203","conference":{"end_date":"2025-10-29","location":"Riga, Latvia","name":"IEEE Nordic Circuits and Systems Conference (NORCAS)","start_date":"2025-10-28"},"title":"A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology","citation":{"short":"M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits and Systems Conference (NORCAS), 2025.","bibtex":"@inproceedings{Iftekhar_Sadiye_Müller_Scheytt_2025, title={A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>}, booktitle={IEEE Nordic Circuits and Systems Conference (NORCAS)}, author={Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","mla":"Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025, doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","apa":"Iftekhar, M., Sadiye, B., Müller, W., &#38; Scheytt, J. C. (2025). A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>","ama":"Iftekhar M, Sadiye B, Müller W, Scheytt JC. A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology. In: <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>. ; 2025. doi:<a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>","ieee":"M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia, 2025, doi: <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">10.1109/NorCAS66540.2025.11231203</a>.","chicago":"Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In <i>IEEE Nordic Circuits and Systems Conference (NORCAS)</i>, 2025. <a href=\"https://doi.org/10.1109/NorCAS66540.2025.11231203\">https://doi.org/10.1109/NorCAS66540.2025.11231203</a>."},"year":"2025","department":[{"_id":"58"}],"user_id":"47944","_id":"62126","project":[{"_id":"325","name":"Scale4Edge: Skalierbare Infrastruktur für Edge-Computing"}],"language":[{"iso":"eng"}],"publication":"IEEE Nordic Circuits and Systems Conference (NORCAS)","type":"conference","status":"public"}]