[{"issue":"3","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","abstract":[{"lang":"eng","text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis."}],"file":[{"date_updated":"2018-11-02T16:04:14Z","relation":"main_file","file_size":2131617,"access_level":"closed","file_name":"a24-riebler.pdf","content_type":"application/pdf","success":1,"file_id":"5322","creator":"ups","date_created":"2018-11-02T16:04:14Z"}],"date_created":"2017-07-25T14:17:32Z","type":"journal_article","keyword":["coldboot"],"department":[{"_id":"27"},{"_id":"518"}],"title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","year":"2017","publication_identifier":{"issn":["1936-7406"]},"author":[{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"id":"24135","full_name":"Lass, Michael","last_name":"Lass","first_name":"Michael","orcid":"0000-0002-5708-7632"},{"full_name":"Mittendorf, Robert","first_name":"Robert","last_name":"Mittendorf"},{"full_name":"Löcke, Thomas","last_name":"Löcke","first_name":"Thomas"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publication_status":"published","date_updated":"2023-09-26T13:23:58Z","intvolume":"        10","language":[{"iso":"eng"}],"doi":"10.1145/3053687","file_date_updated":"2018-11-02T16:04:14Z","citation":{"bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2017;10(3):24:1-24:23. doi:<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>.","short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.","chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 10, no. 3 (2017): 24:1-24:23. <a href=\"https://doi.org/10.1145/3053687\">https://doi.org/10.1145/3053687</a>.","ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 10, no. 3, p. 24:1-24:23, 2017, doi: <a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>.","apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., &#38; Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>10</i>(3), 24:1-24:23. <a href=\"https://doi.org/10.1145/3053687\">https://doi.org/10.1145/3053687</a>"},"quality_controlled":"1","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subproject C2"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","has_accepted_license":"1","page":"24:1-24:23","_id":"18","publisher":"Association for Computing Machinery (ACM)","user_id":"15278","ddc":["000"],"volume":10},{"_id":"31","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"year":"2016","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","status":"public","author":[{"id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","last_name":"Vaz","id":"30332"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl"},{"last_name":"Trainiti","first_name":"Ettore M. G.","full_name":"Trainiti, Ettore M. G."},{"full_name":"Durelli, Gianluca C.","first_name":"Gianluca C.","last_name":"Durelli"},{"full_name":"Bolchini, Cristiana","last_name":"Bolchini","first_name":"Cristiana"}],"date_updated":"2023-09-26T13:25:59Z","has_accepted_license":"1","file":[{"date_created":"2019-01-11T11:56:55Z","creator":"deffel","success":1,"content_type":"application/pdf","file_id":"6626","date_updated":"2019-01-11T11:56:55Z","relation":"main_file","access_level":"closed","file_size":394563,"file_name":"wrc_upb_polimi_final.pdf"}],"date_created":"2017-07-26T15:16:31Z","type":"conference","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2019-01-11T11:56:55Z","publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","citation":{"mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>. ; 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016."},"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14","grant_number":"160364472"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}]},{"date_created":"2017-10-17T12:41:18Z","file":[{"date_updated":"2018-03-21T13:01:09Z","relation":"main_file","access_level":"closed","file_size":184334,"file_name":"138-07740545.pdf","content_type":"application/pdf","success":1,"file_id":"1560","creator":"florida","date_created":"2018-03-21T13:01:09Z"}],"department":[{"_id":"27"},{"_id":"518"}],"type":"conference","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","abstract":[{"text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/RTSI.2016.7740545","author":[{"id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler"},{"id":"30332","last_name":"Vaz","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"},{"full_name":"Trainiti, Ettore M. G. ","last_name":"Trainiti","first_name":"Ettore M. G. "},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"first_name":"Emanuele","last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele"},{"last_name":"Santambrogio","first_name":"Marco D. ","full_name":"Santambrogio, Marco D. "},{"first_name":"Christina","last_name":"Bolchini","full_name":"Bolchini, Christina"}],"year":"2016","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","date_updated":"2023-09-26T13:28:11Z","citation":{"bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G.  and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D.  and Bolchini, Christina}, year={2016}, pages={1–5} }","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>. IEEE; 2016:1-5. doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G.  Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D.  Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. IEEE, 2016. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>.","ieee":"H. Riebler <i>et al.</i>, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 2016, pp. 1–5, doi: <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, IEEE, 2016, pp. 1–5, doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>"},"file_date_updated":"2018-03-21T13:01:09Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"quality_controlled":"1","_id":"138","publisher":"IEEE","page":"1-5","ddc":["040"],"user_id":"15278","status":"public","has_accepted_license":"1"},{"citation":{"apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>, <i>55</i>, 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” <i>Computers and Electrical Engineering</i>, vol. 55, pp. 91–111, 2016, doi: <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i> 55 (2016): 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i>, vol. 55, Elsevier, 2016, pp. 91–111, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>. 2016;55:91-111. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }"},"file_date_updated":"2018-03-21T12:45:47Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"quality_controlled":"1","publisher":"Elsevier","_id":"165","page":"91-111","volume":55,"user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:24Z","file":[{"creator":"florida","date_created":"2018-03-21T12:45:47Z","file_name":"165-1-s2.0-S0045790616301021-main.pdf","file_size":3037854,"access_level":"closed","relation":"main_file","date_updated":"2018-03-21T12:45:47Z","file_id":"1544","success":1,"content_type":"application/pdf"}],"department":[{"_id":"27"},{"_id":"518"}],"type":"journal_article","publication":"Computers and Electrical Engineering","abstract":[{"text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1016/j.compeleceng.2016.04.021","author":[{"id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"id":"16153","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian"}],"publication_identifier":{"issn":["0045-7906"]},"year":"2016","title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code","intvolume":"        55","date_updated":"2023-09-26T13:26:38Z"},{"author":[{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","last_name":"Vaz"},{"id":"8961","last_name":"Riebler","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"id":"16153","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"status":"public","title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","year":"2016","has_accepted_license":"1","date_updated":"2023-09-26T13:27:21Z","language":[{"iso":"eng"}],"_id":"171","user_id":"15278","ddc":["040"],"citation":{"chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In <i>Workshop on Reconfigurable Computing (WRC)</i>, 2016.","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., &#38; Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). <i>Workshop on Reconfigurable Computing (WRC)</i>.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: <i>Workshop on Reconfigurable Computing (WRC)</i>. ; 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” <i>Workshop on Reconfigurable Computing (WRC)</i>, 2016."},"file_date_updated":"2018-03-21T12:39:46Z","publication":"Workshop on Reconfigurable Computing (WRC)","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","date_created":"2017-10-17T12:41:25Z","file":[{"creator":"florida","date_created":"2018-03-21T12:39:46Z","date_updated":"2018-03-21T12:39:46Z","relation":"main_file","file_size":54421,"access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","content_type":"application/pdf","success":1,"file_id":"1538"}],"department":[{"_id":"27"},{"_id":"518"}],"type":"conference"},{"citation":{"ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>. 2015;48(7):18-20. doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i>, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:<a href=\"https://doi.org/10.1109/MC.2015.205\">10.1109/MC.2015.205</a>.","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” <i>IEEE Computer</i> 48, no. 7 (2015): 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","apa":"Torresen, J., Plessl, C., &#38; Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. <i>IEEE Computer</i>, <i>48</i>(7), 18–20. <a href=\"https://doi.org/10.1109/MC.2015.205\">https://doi.org/10.1109/MC.2015.205</a>","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” <i>IEEE Computer</i>, vol. 48, no. 7, pp. 18–20, 2015."},"file_date_updated":"2018-11-02T15:47:45Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"publisher":"IEEE Computer Society","_id":"1772","page":"18-20","volume":48,"ddc":["000"],"user_id":"16153","status":"public","has_accepted_license":"1","date_created":"2018-03-23T14:06:12Z","file":[{"file_id":"5313","content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-11-02T15:47:45Z","file_name":"07163237.pdf","file_size":5605009,"access_level":"closed","date_created":"2018-11-02T15:47:45Z","creator":"ups"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","keyword":["self-awareness","self-expression"],"publication":"IEEE Computer","issue":"7","language":[{"iso":"eng"}],"doi":"10.1109/MC.2015.205","author":[{"full_name":"Torresen, Jim","first_name":"Jim","last_name":"Torresen"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Yao, Xin","last_name":"Yao","first_name":"Xin"}],"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","year":"2015","intvolume":"        48","date_updated":"2022-01-06T06:53:19Z"},{"author":[{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"},{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"year":"2015","title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","intvolume":"      2015","date_updated":"2023-09-26T13:29:08Z","language":[{"iso":"eng"}],"article_number":"859425","doi":"10.1155/2015/859425","publication":"International Journal of Reconfigurable Computing (IJRC)","abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}],"date_created":"2017-10-17T12:41:49Z","file":[{"creator":"florida","date_created":"2018-03-20T07:47:56Z","file_name":"296-859425.pdf","file_size":2993898,"access_level":"closed","relation":"main_file","date_updated":"2018-03-20T07:47:56Z","file_id":"1444","success":1,"content_type":"application/pdf"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","status":"public","has_accepted_license":"1","_id":"296","publisher":"Hindawi","volume":2015,"user_id":"15278","ddc":["040"],"citation":{"ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>. 2015;2015. doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, 859425, Hindawi, 2015, doi:<a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” <i>International Journal of Reconfigurable Computing (IJRC)</i> 2015 (2015). <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. <i>International Journal of Reconfigurable Computing (IJRC)</i>, <i>2015</i>, Article 859425. <a href=\"https://doi.org/10.1155/2015/859425\">https://doi.org/10.1155/2015/859425</a>","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” <i>International Journal of Reconfigurable Computing (IJRC)</i>, vol. 2015, Art. no. 859425, 2015, doi: <a href=\"https://doi.org/10.1155/2015/859425\">10.1155/2015/859425</a>."},"file_date_updated":"2018-03-20T07:47:56Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1"},{"citation":{"bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>. ; 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>, 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","apa":"Damschen, M., &#38; Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. <i>Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT)</i>."},"file_date_updated":"2019-08-01T09:10:44Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","external_id":{"arxiv":["1412.3906"]},"oa":"1","status":"public","has_accepted_license":"1","_id":"303","user_id":"15278","ddc":["040"],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"date_created":"2017-10-17T12:41:51Z","file":[{"creator":"florida","date_created":"2018-03-20T07:46:46Z","file_size":1176620,"access_level":"open_access","file_name":"303-plessl15_adapt.pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file","content_type":"application/pdf","file_id":"1442"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","author":[{"full_name":"Damschen, Marvin","last_name":"Damschen","first_name":"Marvin"},{"id":"16153","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian"}],"year":"2015","title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","date_updated":"2023-09-26T13:29:59Z","language":[{"iso":"eng"}]},{"doi":"10.7873/DATE.2015.1124","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:31:44Z","author":[{"full_name":"Damschen, Marvin","last_name":"Damschen","first_name":"Marvin"},{"id":"8961","first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich"},{"id":"30332","last_name":"Vaz","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","year":"2015","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:41:38Z","file":[{"creator":"florida","date_created":"2018-03-21T10:29:49Z","file_name":"238-plessl15_date.pdf","file_size":380552,"access_level":"closed","relation":"main_file","date_updated":"2018-03-21T10:29:49Z","file_id":"1500","success":1,"content_type":"application/pdf"}],"abstract":[{"lang":"eng","text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator."}],"publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","user_id":"15278","ddc":["040"],"publisher":"EDA Consortium / IEEE","_id":"238","page":"1078-1083","has_accepted_license":"1","status":"public","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"quality_controlled":"1","citation":{"ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 2015, pp. 1078–1083, doi: <a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","apa":"Damschen, M., Riebler, H., Vaz, G. F., &#38; Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–1083. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, EDA Consortium / IEEE, 2015, pp. 1078–83, doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>. EDA Consortium / IEEE; 2015:1078-1083. doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–83. EDA Consortium / IEEE, 2015. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>."},"file_date_updated":"2018-03-21T10:29:49Z"},{"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"date_created":"2017-10-17T12:42:07Z","file":[{"content_type":"application/pdf","success":1,"file_id":"1387","date_updated":"2018-03-20T07:02:02Z","relation":"main_file","access_level":"closed","file_size":330193,"file_name":"388-plessl14_arc.pdf","date_created":"2018-03-20T07:02:02Z","creator":"florida"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","author":[{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"}],"title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","year":"2014","intvolume":"      8405","date_updated":"2023-09-26T13:34:08Z","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"doi":"10.1007/978-3-319-05960-0_13","citation":{"mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>."},"file_date_updated":"2018-03-20T07:02:02Z","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"quality_controlled":"1","place":"Cham","status":"public","has_accepted_license":"1","publisher":"Springer International Publishing","_id":"388","page":"144-155","volume":8405,"user_id":"15278","ddc":["040"]},{"file":[{"date_created":"2018-03-20T07:14:20Z","creator":"florida","file_id":"1397","success":1,"content_type":"application/pdf","file_name":"377-FCCM14.pdf","access_level":"closed","file_size":1003907,"relation":"main_file","date_updated":"2018-03-20T07:14:20Z"}],"date_created":"2017-10-17T12:42:05Z","type":"conference","keyword":["coldboot"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2014.67","year":"2014","title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","author":[{"id":"8961","first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich"},{"full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"}],"date_updated":"2023-09-26T13:33:50Z","file_date_updated":"2018-03-20T07:14:20Z","citation":{"chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–29. IEEE, 2014. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 2014, pp. 222–229, doi: <a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","apa":"Riebler, H., Kenter, T., Plessl, C., &#38; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–229. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2014:222-229. doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2014, pp. 222–29, doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>."},"quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"page":"222-229","_id":"377","publisher":"IEEE","user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1"},{"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","citation":{"ieee":"G. C. Durelli <i>et al.</i>, “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 2014, pp. 142–149, doi: <a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, IEEE, 2014, pp. 142–49, doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &#38; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–149. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>. IEEE; 2014:142-149. doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–49. IEEE, 2014. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>."},"quality_controlled":"1","project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_created":"2018-03-26T13:40:14Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"year":"2014","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","status":"public","author":[{"full_name":"C. Durelli, Gianluca","first_name":"Gianluca","last_name":"C. Durelli"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"full_name":"Miele, Antonio","last_name":"Miele","first_name":"Antonio"},{"last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"D. Santambrogio, Marco","first_name":"Marco","last_name":"D. Santambrogio"},{"first_name":"Cristiana","last_name":"Bolchini","full_name":"Bolchini, Cristiana"}],"date_updated":"2023-09-26T13:35:40Z","page":"142-149","_id":"1778","publisher":"IEEE","language":[{"iso":"eng"}],"doi":"10.1109/ISPA.2014.27","user_id":"15278"},{"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"quality_controlled":"1","citation":{"ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>."},"file_date_updated":"2018-03-16T11:29:52Z","has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","_id":"439","publisher":"IEEE","page":"1-8","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:17Z","file":[{"date_created":"2018-03-16T11:29:52Z","creator":"florida","content_type":"application/pdf","success":1,"file_id":"1353","date_updated":"2018-03-16T11:29:52Z","relation":"main_file","file_size":557362,"access_level":"closed","file_name":"439-plessl14a_reconfig.pdf"}],"date_updated":"2023-09-26T13:37:02Z","author":[{"full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis","id":"30332"},{"id":"8961","first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"}],"year":"2014","title":"Deferring Accelerator Offloading Decisions to Application Runtime","doi":"10.1109/ReConFig.2014.7032509","language":[{"iso":"eng"}]},{"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"file_date_updated":"2018-03-16T11:37:42Z","citation":{"mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }"},"user_id":"15278","ddc":["040"],"page":"1-8","_id":"406","publisher":"IEEE","has_accepted_license":"1","status":"public","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"relation":"main_file","date_updated":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","access_level":"closed","file_size":932852,"file_id":"1366","content_type":"application/pdf","success":1,"creator":"florida","date_created":"2018-03-16T11:37:42Z"}],"date_created":"2017-10-17T12:42:11Z","abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:36:40Z","year":"2014","title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","author":[{"id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"},{"full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}]},{"date_created":"2018-03-26T13:45:35Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","citation":{"ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer; 2014. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>, Springer, 2014, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. Springer, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., &#38; Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. <i>Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)</i>. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">https://doi.org/10.1007/978-3-319-05960-0_38</a>","ieee":"G. C. Durelli <i>et al.</i>, “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_38\">10.1007/978-3-319-05960-0_38</a>."},"quality_controlled":"1","project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"_id":"1780","language":[{"iso":"eng"}],"publisher":"Springer","user_id":"15278","doi":"10.1007/978-3-319-05960-0_38","status":"public","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","year":"2014","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Copolla","first_name":"Marcello","full_name":"Copolla, Marcello"},{"full_name":"Djafarian, Karim","first_name":"Karim","last_name":"Djafarian"},{"first_name":"George","last_name":"Koranaros","full_name":"Koranaros, George"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"full_name":"Paolino, Michele","first_name":"Michele","last_name":"Paolino"},{"full_name":"Pell, Oliver","first_name":"Oliver","last_name":"Pell"},{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"},{"first_name":"Marco","last_name":"D. Santambrogio","full_name":"D. Santambrogio, Marco"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"date_updated":"2023-09-26T13:36:20Z"},{"date_updated":"2023-09-26T13:37:35Z","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Christoph","last_name":"Sorge","full_name":"Sorge, Christoph"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","year":"2013","doi":"10.1109/FPT.2013.6718394","language":[{"iso":"eng"}],"abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["coldboot"],"type":"conference","date_created":"2017-10-17T12:42:35Z","file":[{"date_created":"2018-03-15T10:36:08Z","creator":"florida","file_id":"1294","success":1,"content_type":"application/pdf","relation":"main_file","date_updated":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf","file_size":822680,"access_level":"closed"}],"has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","publisher":"IEEE","_id":"528","page":"386-389","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","citation":{"mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2013, pp. 386–89, doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2013:386-389. doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","apa":"Riebler, H., Kenter, T., Sorge, C., &#38; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–389. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2013, pp. 386–389, doi: <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–89. IEEE, 2013. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>."},"file_date_updated":"2018-03-15T10:36:08Z"}]