[{"external_id":{"arxiv":["2304.03039"]},"abstract":[{"text":"This preprint makes the claim of having computed the $9^{th}$ Dedekind\r\nNumber. This was done by building an efficient FPGA Accelerator for the core\r\noperation of the process, and parallelizing it on the Noctua 2 Supercluster at\r\nPaderborn University. The resulting value is\r\n286386577668298411128469151667598498812366. This value can be verified in two\r\nsteps. We have made the data file containing the 490M results available, each\r\nof which can be verified separately on CPU, and the whole file sums to our\r\nproposed value.","lang":"eng"}],"title":"A computation of D(9) using FPGA Supercomputing","user_id":"3145","author":[{"last_name":"Van Hirtum","first_name":"Lennart","full_name":"Van Hirtum, Lennart"},{"last_name":"De Causmaecker","full_name":"De Causmaecker, Patrick","first_name":"Patrick"},{"last_name":"Goemaere","first_name":"Jens","full_name":"Goemaere, Jens"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publication":"arXiv:2304.03039","department":[{"_id":"27"},{"_id":"518"}],"status":"public","date_created":"2023-04-08T11:05:29Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"_id":"43439","date_updated":"2024-01-22T09:56:42Z","year":"2023","type":"preprint","citation":{"ieee":"L. Van Hirtum et al., “A computation of D(9) using FPGA Supercomputing,” arXiv:2304.03039. 2023.","short":"L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ArXiv:2304.03039 (2023).","bibtex":"@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2023, title={A computation of D(9) using FPGA Supercomputing}, journal={arXiv:2304.03039}, author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian}, year={2023} }","mla":"Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.","chicago":"Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.","apa":"Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Lass, M., & Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing. In arXiv:2304.03039.","ama":"Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using FPGA Supercomputing. arXiv:230403039. Published online 2023."},"language":[{"iso":"eng"}]},{"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_identifier":{"issn":["1094-3420","1741-2846"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}],"title":"Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics","language":[{"iso":"eng"}],"oa":"1","doi":"10.1177/10943420231177631","date_updated":"2023-08-02T15:04:53Z","status":"public","date_created":"2023-05-30T09:19:09Z","publisher":"SAGE Publications","author":[{"last_name":"Schade","id":"75963","first_name":"Robert","full_name":"Schade, Robert","orcid":"0000-0002-6268-539"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"60250","last_name":"Elgabarty","orcid":"0000-0002-4945-1481","full_name":"Elgabarty, Hossam","first_name":"Hossam"},{"id":"24135","last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","keyword":["Hardware and Architecture","Theoretical Computer Science","Software"],"publication":"The International Journal of High Performance Computing Applications","user_id":"75963","article_type":"original","abstract":[{"lang":"eng","text":"
The effect of traces of ethanol in supercritical carbon dioxide on the mixture's thermodynamic properties is studied by molecular simulations and Taylor dispersion measurements.
","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1039/d0cp04985a","date_updated":"2023-09-27T10:24:39Z","publication_status":"published","publication_identifier":{"issn":["1463-9076","1463-9084"]},"department":[{"_id":"27"}],"title":"Diffusion of the carbon dioxide–ethanol mixture in the extended critical region"},{"language":[{"iso":"eng"}],"doi":"10.1103/physrevd.104.094518","date_updated":"2023-07-26T09:23:02Z","publication_identifier":{"issn":["2470-0010","2470-0029"]},"publication_status":"published","department":[{"_id":"27"}],"title":"Eigenvalue spectra of QCD and the fate ofState-of-the-art methods in materials science such as artificial intelligence and data-driven techniques advance the investigation of photovoltaic materials.
","lang":"eng"}],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2022-06-28T08:03:05Z","doi":"10.1039/d0cp04712k","department":[{"_id":"27"}],"publication_status":"published","publication_identifier":{"issn":["1463-9076","1463-9084"]},"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"In silico investigation of Cu(In,Ga)Se2-based solar cells"},{"conference":{"name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","location":"Atlanta, GA, US"},"_id":"16898","page":"1127-1140","type":"conference","citation":{"mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.","bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.","ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.","short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140."},"year":"2020","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"user_id":"75963","abstract":[{"text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs.","lang":"eng"}],"date_created":"2020-04-28T14:44:21Z","status":"public","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","quality_controlled":"1","author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"id":"75963","last_name":"Schade","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"IEEE Computer Society","doi":"10.1109/SC41405.2020.00084","date_updated":"2023-08-02T14:55:59Z","language":[{"iso":"eng"}],"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K","external_id":{"arxiv":["2004.10811"]},"place":"Los Alamitos, CA, USA","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}]},{"oa":"1","doi":"10.3390/computation8020039","date_updated":"2023-09-26T11:43:52Z","language":[{"iso":"eng"}],"title":"Accurate Sampling with Noisy Forces from Approximate Computing","external_id":{"arxiv":["1907.08497"]},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"issue":"2","article_number":"39","_id":"12878","intvolume":" 8","year":"2020","type":"journal_article","citation":{"ieee":"V. Rengaraj, M. Lass, C. Plessl, and T. Kühne, “Accurate Sampling with Noisy Forces from Approximate Computing,” Computation, vol. 8, no. 2, Art. no. 39, 2020, doi: 10.3390/computation8020039.","short":"V. Rengaraj, M. Lass, C. Plessl, T. Kühne, Computation 8 (2020).","bibtex":"@article{Rengaraj_Lass_Plessl_Kühne_2020, title={Accurate Sampling with Noisy Forces from Approximate Computing}, volume={8}, DOI={10.3390/computation8020039}, number={239}, journal={Computation}, publisher={MDPI}, author={Rengaraj, Varadarajan and Lass, Michael and Plessl, Christian and Kühne, Thomas}, year={2020} }","mla":"Rengaraj, Varadarajan, et al. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation, vol. 8, no. 2, 39, MDPI, 2020, doi:10.3390/computation8020039.","ama":"Rengaraj V, Lass M, Plessl C, Kühne T. Accurate Sampling with Noisy Forces from Approximate Computing. Computation. 2020;8(2). doi:10.3390/computation8020039","apa":"Rengaraj, V., Lass, M., Plessl, C., & Kühne, T. (2020). Accurate Sampling with Noisy Forces from Approximate Computing. Computation, 8(2), Article 39. https://doi.org/10.3390/computation8020039","chicago":"Rengaraj, Varadarajan, Michael Lass, Christian Plessl, and Thomas Kühne. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation 8, no. 2 (2020). https://doi.org/10.3390/computation8020039."},"main_file_link":[{"url":"https://www.mdpi.com/2079-3197/8/2/39/pdf","open_access":"1"}],"user_id":"15278","abstract":[{"lang":"eng","text":"In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation."}],"date_created":"2019-07-23T12:03:07Z","status":"public","volume":8,"publication":"Computation","quality_controlled":"1","publisher":"MDPI","author":[{"last_name":"Rengaraj","full_name":"Rengaraj, Varadarajan","first_name":"Varadarajan"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"}]},{"issue":"19","article_number":"194103","intvolume":" 152","_id":"16277","year":"2020","type":"journal_article","citation":{"mla":"Kühne, Thomas, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics, vol. 152, no. 19, 194103, 2020, doi:10.1063/5.0007045.","bibtex":"@article{Kühne_Iannuzzi_Ben_Rybkin_Seewald_Stein_Laino_Khaliullin_Schütt_Schiffmann_et al._2020, title={CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations}, volume={152}, DOI={10.1063/5.0007045}, number={19194103}, journal={The Journal of Chemical Physics}, author={Kühne, Thomas and Iannuzzi, Marcella and Ben, Mauro Del and Rybkin, Vladimir V. and Seewald, Patrick and Stein, Frederick and Laino, Teodoro and Khaliullin, Rustam Z. and Schütt, Ole and Schiffmann, Florian and et al.}, year={2020} }","ieee":"T. Kühne et al., “CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations,” The Journal of Chemical Physics, vol. 152, no. 19, Art. no. 194103, 2020, doi: 10.1063/5.0007045.","chicago":"Kühne, Thomas, Marcella Iannuzzi, Mauro Del Ben, Vladimir V. Rybkin, Patrick Seewald, Frederick Stein, Teodoro Laino, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics 152, no. 19 (2020). https://doi.org/10.1063/5.0007045.","ama":"Kühne T, Iannuzzi M, Ben MD, et al. CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics. 2020;152(19). doi:10.1063/5.0007045","apa":"Kühne, T., Iannuzzi, M., Ben, M. D., Rybkin, V. V., Seewald, P., Stein, F., Laino, T., Khaliullin, R. Z., Schütt, O., Schiffmann, F., Golze, D., Wilhelm, J., Chulkov, S., Mohammad Hossein Bani-Hashemian, M. H. B.-H., Weber, V., Borstnik, U., Taillefumier, M., Jakobovits, A. S., Lazzaro, A., … Hutter, J. (2020). CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics, 152(19), Article 194103. https://doi.org/10.1063/5.0007045","short":"T. Kühne, M. Iannuzzi, M.D. Ben, V.V. Rybkin, P. Seewald, F. Stein, T. Laino, R.Z. Khaliullin, O. Schütt, F. Schiffmann, D. Golze, J. Wilhelm, S. Chulkov, M.H.B.-H. Mohammad Hossein Bani-Hashemian, V. Weber, U. Borstnik, M. Taillefumier, A.S. Jakobovits, A. Lazzaro, H. Pabst, T. Müller, R. Schade, M. Guidon, S. Andermatt, N. Holmberg, G.K. Schenter, A. Hehn, A. Bussy, F. Belleflamme, G. Tabacchi, A. Glöß, M. Lass, I. Bethune, C.J. Mundy, C. Plessl, M. Watkins, J. VandeVondele, M. Krack, J. Hutter, The Journal of Chemical Physics 152 (2020)."},"main_file_link":[{"url":"https://aip.scitation.org/doi/pdf/10.1063/5.0007045?download=true","open_access":"1"}],"user_id":"75963","ddc":["540"],"abstract":[{"text":"CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2020-03-10T15:12:31Z","volume":152,"file":[{"access_level":"closed","date_created":"2020-05-25T15:21:56Z","file_name":"5.0007045.pdf","success":1,"relation":"main_file","date_updated":"2020-05-25T15:21:56Z","content_type":"application/pdf","creator":"lass","file_id":"17061","file_size":4887650}],"quality_controlled":"1","author":[{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"full_name":"Iannuzzi, Marcella","first_name":"Marcella","last_name":"Iannuzzi"},{"last_name":"Ben","first_name":"Mauro Del","full_name":"Ben, Mauro Del"},{"first_name":"Vladimir V.","full_name":"Rybkin, Vladimir V.","last_name":"Rybkin"},{"last_name":"Seewald","full_name":"Seewald, Patrick","first_name":"Patrick"},{"last_name":"Stein","full_name":"Stein, Frederick","first_name":"Frederick"},{"first_name":"Teodoro","full_name":"Laino, Teodoro","last_name":"Laino"},{"last_name":"Khaliullin","first_name":"Rustam Z.","full_name":"Khaliullin, Rustam Z."},{"last_name":"Schütt","full_name":"Schütt, Ole","first_name":"Ole"},{"full_name":"Schiffmann, Florian","first_name":"Florian","last_name":"Schiffmann"},{"full_name":"Golze, Dorothea","first_name":"Dorothea","last_name":"Golze"},{"last_name":"Wilhelm","first_name":"Jan","full_name":"Wilhelm, Jan"},{"last_name":"Chulkov","full_name":"Chulkov, Sergey","first_name":"Sergey"},{"last_name":"Mohammad Hossein Bani-Hashemian","first_name":"Mohammad Hossein Bani-Hashemian","full_name":"Mohammad Hossein Bani-Hashemian, Mohammad Hossein Bani-Hashemian"},{"last_name":"Weber","full_name":"Weber, Valéry","first_name":"Valéry"},{"full_name":"Borstnik, Urban","first_name":"Urban","last_name":"Borstnik"},{"first_name":"Mathieu","full_name":"Taillefumier, Mathieu","last_name":"Taillefumier"},{"last_name":"Jakobovits","first_name":"Alice Shoshana","full_name":"Jakobovits, Alice Shoshana"},{"last_name":"Lazzaro","first_name":"Alfio","full_name":"Lazzaro, Alfio"},{"last_name":"Pabst","first_name":"Hans","full_name":"Pabst, Hans"},{"last_name":"Müller","first_name":"Tiziano","full_name":"Müller, Tiziano"},{"id":"75963","last_name":"Schade","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert"},{"first_name":"Manuel","full_name":"Guidon, Manuel","last_name":"Guidon"},{"last_name":"Andermatt","first_name":"Samuel","full_name":"Andermatt, Samuel"},{"full_name":"Holmberg, Nico","first_name":"Nico","last_name":"Holmberg"},{"last_name":"Schenter","first_name":"Gregory K.","full_name":"Schenter, Gregory K."},{"last_name":"Hehn","first_name":"Anna","full_name":"Hehn, Anna"},{"full_name":"Bussy, Augustin","first_name":"Augustin","last_name":"Bussy"},{"last_name":"Belleflamme","full_name":"Belleflamme, Fabian","first_name":"Fabian"},{"first_name":"Gloria","full_name":"Tabacchi, Gloria","last_name":"Tabacchi"},{"last_name":"Glöß","first_name":"Andreas","full_name":"Glöß, Andreas"},{"id":"24135","last_name":"Lass","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael"},{"last_name":"Bethune","full_name":"Bethune, Iain","first_name":"Iain"},{"full_name":"Mundy, Christopher J.","first_name":"Christopher J.","last_name":"Mundy"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Watkins","first_name":"Matt","full_name":"Watkins, Matt"},{"last_name":"VandeVondele","full_name":"VandeVondele, Joost","first_name":"Joost"},{"full_name":"Krack, Matthias","first_name":"Matthias","last_name":"Krack"},{"last_name":"Hutter","first_name":"Jürg","full_name":"Hutter, Jürg"}],"file_date_updated":"2020-05-25T15:21:56Z","publication":"The Journal of Chemical Physics","oa":"1","doi":"10.1063/5.0007045","date_updated":"2023-08-02T14:56:21Z","language":[{"iso":"eng"}],"title":"CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations","external_id":{"arxiv":["2003.03868"]},"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication_status":"published","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}]},{"abstract":[{"text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.","lang":"eng"}],"user_id":"15278","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","quality_controlled":"1","author":[{"first_name":"Marius","full_name":"Meyer, Marius","last_name":"Meyer","id":"40778"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2021-04-16T10:17:22Z","status":"public","_id":"21632","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"year":"2020","citation":{"apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007."},"type":"conference","related_material":{"link":[{"url":"https://github.com/pc2/HPCC_FPGA","relation":"supplementary_material","description":"Official repository of the benchmark suite on GitHub"}]},"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"date_updated":"2023-09-26T11:42:53Z","doi":"10.1109/h2rc51942.2020.00007","language":[{"iso":"eng"}]},{"abstract":[{"text":"We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms.","lang":"eng"}],"external_id":{"arxiv":["2011.00813"]},"title":"Multi-Armed Bandits with Censored Consumption of Resources","user_id":"15278","publication":"arXiv:2011.00813","department":[{"_id":"27"}],"author":[{"full_name":"Bengs, Viktor","first_name":"Viktor","last_name":"Bengs"},{"full_name":"Hüllermeier, Eyke","first_name":"Eyke","last_name":"Hüllermeier"}],"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2022-06-28T07:26:54Z","status":"public","_id":"32242","date_updated":"2022-06-28T07:27:19Z","citation":{"short":"V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020).","ieee":"V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020.","ama":"Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020.","apa":"Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813.","chicago":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","mla":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","bibtex":"@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }"},"type":"preprint","year":"2020","language":[{"iso":"eng"}]},{"author":[{"last_name":"Nickchen","first_name":"Tobias","full_name":"Nickchen, Tobias"},{"full_name":"Engels, Gregor","first_name":"Gregor","last_name":"Engels"},{"last_name":"Lohn","full_name":"Lohn, Johannes","first_name":"Johannes"}],"publication":"Industrializing Additive Manufacturing","department":[{"_id":"534"},{"_id":"624"},{"_id":"27"},{"_id":"66"},{"_id":"219"}],"publication_identifier":{"isbn":["9783030543334","9783030543341"]},"publication_status":"published","status":"public","date_created":"2020-09-01T13:49:42Z","place":"Cham","ddc":["000"],"title":"Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain","user_id":"27340","type":"book_chapter","citation":{"short":"T. Nickchen, G. Engels, J. Lohn, in: Industrializing Additive Manufacturing, Cham, 2020.","ieee":"T. Nickchen, G. Engels, and J. Lohn, “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain,” in Industrializing Additive Manufacturing, Cham, 2020.","apa":"Nickchen, T., Engels, G., & Lohn, J. (2020). Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain. In Industrializing Additive Manufacturing. Cham. https://doi.org/10.1007/978-3-030-54334-1_4","ama":"Nickchen T, Engels G, Lohn J. Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain. In: Industrializing Additive Manufacturing. Cham; 2020. doi:10.1007/978-3-030-54334-1_4","chicago":"Nickchen, Tobias, Gregor Engels, and Johannes Lohn. “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain.” In Industrializing Additive Manufacturing. Cham, 2020. https://doi.org/10.1007/978-3-030-54334-1_4.","mla":"Nickchen, Tobias, et al. “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain.” Industrializing Additive Manufacturing, 2020, doi:10.1007/978-3-030-54334-1_4.","bibtex":"@inbook{Nickchen_Engels_Lohn_2020, place={Cham}, title={Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain}, DOI={10.1007/978-3-030-54334-1_4}, booktitle={Industrializing Additive Manufacturing}, author={Nickchen, Tobias and Engels, Gregor and Lohn, Johannes}, year={2020} }"},"year":"2020","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:53:52Z","_id":"18789","conference":{"start_date":"2020-09-01","end_date":"2020-09-03"},"doi":"10.1007/978-3-030-54334-1_4"},{"_id":"21","intvolume":" 25","issue":"2","year":"2019","type":"journal_article","citation":{"bibtex":"@article{Richters_Lass_Walther_Plessl_Kühne_2019, title={A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices}, volume={25}, DOI={10.4208/cicp.OA-2018-0053}, number={2}, journal={Communications in Computational Physics}, publisher={Global Science Press}, author={Richters, Dorothee and Lass, Michael and Walther, Andrea and Plessl, Christian and Kühne, Thomas}, year={2019}, pages={564–585} }","mla":"Richters, Dorothee, et al. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics, vol. 25, no. 2, Global Science Press, 2019, pp. 564–85, doi:10.4208/cicp.OA-2018-0053.","chicago":"Richters, Dorothee, Michael Lass, Andrea Walther, Christian Plessl, and Thomas Kühne. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics 25, no. 2 (2019): 564–85. https://doi.org/10.4208/cicp.OA-2018-0053.","ama":"Richters D, Lass M, Walther A, Plessl C, Kühne T. A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics. 2019;25(2):564-585. doi:10.4208/cicp.OA-2018-0053","apa":"Richters, D., Lass, M., Walther, A., Plessl, C., & Kühne, T. (2019). A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics, 25(2), 564–585. https://doi.org/10.4208/cicp.OA-2018-0053","ieee":"D. Richters, M. Lass, A. Walther, C. Plessl, and T. Kühne, “A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices,” Communications in Computational Physics, vol. 25, no. 2, pp. 564–585, 2019, doi: 10.4208/cicp.OA-2018-0053.","short":"D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics 25 (2019) 564–585."},"page":"564-585","abstract":[{"lang":"eng","text":"We address the general mathematical problem of computing the inverse p-th\r\nroot of a given matrix in an efficient way. A new method to construct iteration\r\nfunctions that allow calculating arbitrary p-th roots and their inverses of\r\nsymmetric positive definite matrices is presented. We show that the order of\r\nconvergence is at least quadratic and that adaptively adjusting a parameter q\r\nalways leads to an even faster convergence. In this way, a better performance\r\nthan with previously known iteration schemes is achieved. The efficiency of the\r\niterative functions is demonstrated for various matrices with different\r\ndensities, condition numbers and spectral radii."}],"user_id":"15278","author":[{"last_name":"Richters","first_name":"Dorothee","full_name":"Richters, Dorothee"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"first_name":"Andrea","full_name":"Walther, Andrea","last_name":"Walther"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"}],"quality_controlled":"1","publisher":"Global Science Press","publication":"Communications in Computational Physics","status":"public","date_created":"2017-07-25T14:48:26Z","volume":25,"date_updated":"2023-09-26T11:45:02Z","doi":"10.4208/cicp.OA-2018-0053","language":[{"iso":"eng"}],"external_id":{"arxiv":["1703.02456"]},"title":"A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"},{"_id":"104"}],"project":[{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}]},{"author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"}],"department":[{"_id":"27"}],"status":"public","date_created":"2022-11-30T14:36:04Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"title":"Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs","user_id":"15504","type":"dissertation","year":"2019","citation":{"ieee":"H. Riebler, Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. 2019.","short":"H. Riebler, Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019.","bibtex":"@book{Riebler_2019, title={Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs}, DOI={10.17619/UNIPB/1-830}, author={Riebler, Heinrich}, year={2019} }","mla":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs. 2019, doi:10.17619/UNIPB/1-830.","chicago":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019. https://doi.org/10.17619/UNIPB/1-830.","apa":"Riebler, H. (2019). Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. https://doi.org/10.17619/UNIPB/1-830","ama":"Riebler H. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs.; 2019. doi:10.17619/UNIPB/1-830"},"supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"language":[{"iso":"eng"}],"_id":"34167","date_updated":"2022-11-30T14:44:15Z","doi":"10.17619/UNIPB/1-830"},{"ddc":["004"],"user_id":"15278","date_created":"2019-07-22T12:42:44Z","has_accepted_license":"1","status":"public","file_date_updated":"2019-07-22T12:45:02Z","publication":"Informatik Spektrum","author":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","file":[{"access_level":"open_access","file_name":"plessl19_informatik_spektrum.pdf","date_created":"2019-07-22T12:45:02Z","date_updated":"2019-07-22T12:45:02Z","content_type":"application/pdf","relation":"main_file","file_size":248360,"creator":"plessl","file_id":"12872"}],"_id":"12871","year":"2019","citation":{"mla":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w.","bibtex":"@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }","chicago":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.","apa":"Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik Spektrum. https://doi.org/10.1007/s00287-019-01187-w","ama":"Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w","ieee":"M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.","short":"M. Platzner, C. Plessl, Informatik Spektrum (2019)."},"type":"journal_article","title":"FPGAs im Rechenzentrum","publication_identifier":{"issn":["0170-6012","1432-122X"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1007/s00287-019-01187-w","oa":"1","date_updated":"2023-09-26T11:45:57Z","language":[{"iso":"ger"}]},{"file":[{"file_name":"gorlani19_fpt.pdf","date_created":"2020-01-09T12:53:57Z","access_level":"closed","file_id":"15479","creator":"plessl","file_size":250559,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2020-01-09T12:53:57Z"}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2020-01-09T12:53:57Z","quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Paolo","full_name":"Gorlani, Paolo","last_name":"Gorlani","id":"72045"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"date_created":"2020-01-09T12:54:48Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS."}],"user_id":"3145","ddc":["004"],"citation":{"short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.","bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }"},"year":"2019","type":"conference","conference":{"name":"International Conference on Field-Programmable Technology (FPT)"},"_id":"15478","department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"01|H16005","name":"HighPerMeshes","_id":"33"},{"grant_number":"PL 595/2-1","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"}],"title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:52:26Z","doi":"10.1109/ICFPT47387.2019.00020"},{"issue":"2","_id":"7689","intvolume":" 16","page":"14:1–14:26","year":"2019","type":"journal_article","citation":{"ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019.","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, ACM Trans. Archit. Code Optim. (TACO) 16 (2019) 14:1–14:26.","mla":"Riebler, Heinrich, et al. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:10.1145/3319423.","bibtex":"@article{Riebler_Vaz_Kenter_Plessl_2019, title={Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}, volume={16}, DOI={10.1145/3319423}, number={2}, journal={ACM Trans. Archit. Code Optim. (TACO)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2019}, pages={14:1–14:26} }","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO) 16, no. 2 (2019): 14:1–14:26. https://doi.org/10.1145/3319423.","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2019). Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans. Archit. Code Optim. (TACO), 16(2), 14:1–14:26. https://doi.org/10.1145/3319423","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans Archit Code Optim (TACO). 2019;16(2):14:1–14:26. doi:10.1145/3319423"},"user_id":"16153","ddc":["000"],"article_type":"original","date_created":"2019-02-13T15:01:43Z","status":"public","has_accepted_license":"1","volume":16,"file":[{"date_created":"2019-02-13T14:59:07Z","file_name":"htrop19_taco.pdf","access_level":"closed","file_size":872822,"file_id":"7695","creator":"deffel","content_type":"application/pdf","date_updated":"2019-02-13T14:59:07Z","relation":"main_file"}],"file_date_updated":"2019-02-13T14:59:07Z","keyword":["htrop"],"publication":"ACM Trans. Archit. Code Optim. (TACO)","publisher":"ACM","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","doi":"10.1145/3319423","date_updated":"2022-01-06T07:03:44Z","language":[{"iso":"eng"}],"title":"Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}]},{"editor":[{"first_name":"D.","full_name":"Klusáček, D.","last_name":"Klusáček"},{"full_name":"Cirne, W.","first_name":"W.","last_name":"Cirne"},{"full_name":"Desai, N.","first_name":"N.","last_name":"Desai"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-319-77398-8","978-3-319-77397-1"]},"department":[{"_id":"27"}],"title":"A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-77398-8_8","date_updated":"2022-01-06T06:55:22Z","status":"public","date_created":"2017-07-25T14:54:08Z","volume":10773,"publisher":"Springer","author":[{"last_name":"Keller","id":"15274","first_name":"Axel","full_name":"Keller, Axel"}],"keyword":["Scheduling Planning Mapping Workload management"],"publication":"Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)","user_id":"15274","abstract":[{"lang":"eng","text":"This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\\(^2\\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation."}],"citation":{"short":"A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151.","ieee":"A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.","chicago":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8.","ama":"Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8","apa":"Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8","mla":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8.","bibtex":"@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }"},"year":"2018","type":"conference","page":"132-151","intvolume":" 10773","_id":"22","conference":{"location":"Orlando, FL, USA","name":"21st Workshop on Job Scheduling Strategies for Parallel Processing","start_date":"2017-06-02","end_date":"2017-06-02"}},{"user_id":"15278","abstract":[{"text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.","lang":"eng"}],"date_created":"2018-03-22T10:53:01Z","status":"public","keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","publisher":"ACM","author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"last_name":"Mohr","first_name":"Stephan","full_name":"Mohr, Stephan"},{"last_name":"Wiebeler","full_name":"Wiebeler, Hendrik","first_name":"Hendrik"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","conference":{"end_date":"2018-07-04","start_date":"2018-07-02","name":"Platform for Advanced Scientific Computing Conference (PASC)","location":"Basel, Switzerland"},"_id":"1590","year":"2018","citation":{"mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231.","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018."},"type":"conference","title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","external_id":{"arxiv":["1710.10899"]},"place":"New York, NY, USA","project":[{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"doi":"10.1145/3218176.3218231","date_updated":"2023-09-26T11:48:12Z","language":[{"iso":"eng"}]},{"title":"Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_updated":"2022-01-12T16:32:23Z","oa":"1","language":[{"iso":"eng"}],"abstract":[{"text":"Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs.","lang":"eng"}],"ddc":["000"],"user_id":"49171","publisher":"Universität Paderborn","author":[{"first_name":"Arjun","full_name":"Ramaswami, Arjun","orcid":"https://orcid.org/0000-0002-0909-1178","last_name":"Ramaswami","id":"49171"}],"keyword":["FFT: FPGA","CP2K","OpenCL"],"file_date_updated":"2020-06-15T11:29:38Z","file":[{"file_size":1297585,"file_id":"17093","creator":"arjunr","date_updated":"2020-06-15T11:29:38Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"masterthesis.pdf","date_created":"2020-06-15T11:29:38Z","access_level":"closed"}],"status":"public","has_accepted_license":"1","date_created":"2018-11-07T16:08:32Z","_id":"5417","main_file_link":[{"open_access":"1"}],"citation":{"ieee":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.","short":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018.","bibtex":"@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn}, author={Ramaswami, Arjun}, year={2018} }","mla":"Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.","apa":"Ramaswami, A. (2018). Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn.","ama":"Ramaswami A. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn; 2018.","chicago":"Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018."},"year":"2018","type":"mastersthesis","supervisor":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}]},{"_id":"1204","citation":{"ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534."},"year":"2018","type":"conference","ddc":["000"],"user_id":"15278","date_created":"2018-03-08T14:45:18Z","status":"public","has_accepted_license":"1","file_date_updated":"2018-11-02T14:43:37Z","publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","keyword":["htrop"],"quality_controlled":"1","publisher":"ACM","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"file":[{"creator":"ups","file_id":"5281","file_size":447769,"relation":"main_file","success":1,"date_updated":"2018-11-02T14:43:37Z","content_type":"application/pdf","date_created":"2018-11-02T14:43:37Z","file_name":"p417-riebler.pdf","access_level":"closed"}],"doi":"10.1145/3178487.3178534","date_updated":"2023-09-26T11:47:23Z","language":[{"iso":"eng"}],"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","publication_status":"published","publication_identifier":{"isbn":["9781450349826"]},"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"department":[{"_id":"27"},{"_id":"518"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:47:52Z","doi":"10.1109/FCCM.2018.00037","keyword":["tet_topic_hpc"],"file_date_updated":"2018-11-02T14:45:05Z","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Mahale","full_name":"Mahale, Gopinath","first_name":"Gopinath"},{"full_name":"Alhaddad, Samer","first_name":"Samer","id":"42456","last_name":"Alhaddad"},{"first_name":"Yevgen","full_name":"Grynko, Yevgen","last_name":"Grynko","id":"26059"},{"full_name":"Schmitt, Christian","first_name":"Christian","last_name":"Schmitt"},{"last_name":"Afzal","full_name":"Afzal, Ayesha","first_name":"Ayesha"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"file":[{"file_size":269130,"creator":"ups","file_id":"5282","content_type":"application/pdf","date_updated":"2018-11-02T14:45:05Z","success":1,"relation":"main_file","file_name":"08457652.pdf","date_created":"2018-11-02T14:45:05Z","access_level":"closed"}],"date_created":"2018-03-22T10:48:01Z","has_accepted_license":"1","status":"public","abstract":[{"text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.","lang":"eng"}],"ddc":["000"],"user_id":"15278","citation":{"ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037"},"year":"2018","type":"conference","conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"_id":"1588"},{"date_updated":"2022-01-06T07:01:53Z","_id":"5421","year":"2018","citation":{"short":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL, Universität Paderborn, 2018.","ieee":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","chicago":"Gadewar, Onkar. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","apa":"Gadewar, O. (2018). Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn.","ama":"Gadewar O. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn; 2018.","mla":"Gadewar, Onkar. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","bibtex":"@book{Gadewar_2018, title={Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL}, publisher={Universität Paderborn}, author={Gadewar, Onkar}, year={2018} }"},"type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"title":"Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL","user_id":"477","author":[{"full_name":"Gadewar, Onkar","first_name":"Onkar","last_name":"Gadewar"}],"publisher":"Universität Paderborn","department":[{"_id":"27"},{"_id":"518"}],"status":"public","date_created":"2018-11-07T16:16:56Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}]},{"citation":{"ama":"Mertens JC, Boschmann A, Schmidt M, Plessl C. Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering. 2018;21(4):441-451. doi:10.1007/s12283-018-0291-0","apa":"Mertens, J. C., Boschmann, A., Schmidt, M., & Plessl, C. (2018). Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering, 21(4), 441–451. https://doi.org/10.1007/s12283-018-0291-0","chicago":"Mertens, Jan Cedric, Alexander Boschmann, M. Schmidt, and Christian Plessl. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering 21, no. 4 (2018): 441–51. https://doi.org/10.1007/s12283-018-0291-0.","mla":"Mertens, Jan Cedric, et al. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering, vol. 21, no. 4, Springer Nature, 2018, pp. 441–51, doi:10.1007/s12283-018-0291-0.","bibtex":"@article{Mertens_Boschmann_Schmidt_Plessl_2018, title={Sprint diagnostic with GPS and inertial sensor fusion}, volume={21}, DOI={10.1007/s12283-018-0291-0}, number={4}, journal={Sports Engineering}, publisher={Springer Nature}, author={Mertens, Jan Cedric and Boschmann, Alexander and Schmidt, M. and Plessl, Christian}, year={2018}, pages={441–451} }","short":"J.C. Mertens, A. Boschmann, M. Schmidt, C. Plessl, Sports Engineering 21 (2018) 441–451.","ieee":"J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” Sports Engineering, vol. 21, no. 4, pp. 441–451, 2018."},"year":"2018","type":"journal_article","page":"441-451","_id":"6516","intvolume":" 21","issue":"4","file":[{"file_name":"plessl18_sportseng.pdf","date_created":"2019-01-08T17:47:06Z","access_level":"closed","file_size":2141021,"creator":"plessl","file_id":"6517","content_type":"application/pdf","date_updated":"2019-01-08T17:47:06Z","relation":"main_file"}],"publisher":"Springer Nature","quality_controlled":"1","author":[{"first_name":"Jan Cedric","full_name":"Mertens, Jan Cedric","last_name":"Mertens"},{"last_name":"Boschmann","first_name":"Alexander","full_name":"Boschmann, Alexander"},{"full_name":"Schmidt, M.","first_name":"M.","last_name":"Schmidt"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publication":"Sports Engineering","file_date_updated":"2019-01-08T17:47:06Z","status":"public","has_accepted_license":"1","date_created":"2019-01-08T17:44:43Z","volume":21,"user_id":"16153","ddc":["000"],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:03:09Z","doi":"10.1007/s12283-018-0291-0","department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","publication_identifier":{"issn":["1369-7072","1460-2687"]},"title":"Sprint diagnostic with GPS and inertial sensor fusion"},{"status":"public","date_created":"2018-11-07T15:14:26Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"publisher":"Universität Paderborn","author":[{"last_name":"Filmwala","full_name":"Filmwala, Tasneem","first_name":"Tasneem"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"477","title":"Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform","language":[{"iso":"eng"}],"supervisor":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"year":"2018","citation":{"short":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform, Universität Paderborn, 2018.","ieee":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn, 2018.","ama":"Filmwala T. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn; 2018.","apa":"Filmwala, T. (2018). Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn.","chicago":"Filmwala, Tasneem. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn, 2018.","mla":"Filmwala, Tasneem. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn, 2018.","bibtex":"@book{Filmwala_2018, title={Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform}, publisher={Universität Paderborn}, author={Filmwala, Tasneem}, year={2018} }"},"type":"mastersthesis","_id":"5414","date_updated":"2022-01-06T07:01:52Z"},{"intvolume":" 35","_id":"13348","issue":"1","article_number":"146","type":"journal_article","year":"2018","citation":{"ieee":"S. M. H. Luk et al., “Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities,” Journal of the Optical Society of America B, vol. 35, no. 1, Art. no. 146, 2018, doi: 10.1364/josab.35.000146.","short":"S.M.H. Luk, P. Lewandowski, N.H. Kwong, E. Baudin, O. Lafont, J. Tignon, P.T. Leung, Ch.K.P. Chan, M. Babilon, S. Schumacher, R. Binder, Journal of the Optical Society of America B 35 (2018).","bibtex":"@article{Luk_Lewandowski_Kwong_Baudin_Lafont_Tignon_Leung_Chan_Babilon_Schumacher_et al._2018, title={Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities}, volume={35}, DOI={10.1364/josab.35.000146}, number={1146}, journal={Journal of the Optical Society of America B}, author={Luk, Samuel M. H. and Lewandowski, P. and Kwong, N. H. and Baudin, E. and Lafont, O. and Tignon, J. and Leung, P. T. and Chan, Ch. K. P. and Babilon, M. and Schumacher, Stefan and et al.}, year={2018} }","mla":"Luk, Samuel M. H., et al. “Theory of Optically Controlled Anisotropic Polariton Transport in Semiconductor Double Microcavities.” Journal of the Optical Society of America B, vol. 35, no. 1, 146, 2018, doi:10.1364/josab.35.000146.","chicago":"Luk, Samuel M. H., P. Lewandowski, N. H. Kwong, E. Baudin, O. Lafont, J. Tignon, P. T. Leung, et al. “Theory of Optically Controlled Anisotropic Polariton Transport in Semiconductor Double Microcavities.” Journal of the Optical Society of America B 35, no. 1 (2018). https://doi.org/10.1364/josab.35.000146.","ama":"Luk SMH, Lewandowski P, Kwong NH, et al. Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities. Journal of the Optical Society of America B. 2018;35(1). doi:10.1364/josab.35.000146","apa":"Luk, S. M. H., Lewandowski, P., Kwong, N. H., Baudin, E., Lafont, O., Tignon, J., Leung, P. T., Chan, Ch. K. P., Babilon, M., Schumacher, S., & Binder, R. (2018). Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities. Journal of the Optical Society of America B, 35(1), Article 146. https://doi.org/10.1364/josab.35.000146"},"user_id":"14931","publication":"Journal of the Optical Society of America B","author":[{"last_name":"Luk","full_name":"Luk, Samuel M. H.","first_name":"Samuel M. H."},{"last_name":"Lewandowski","first_name":"P.","full_name":"Lewandowski, P."},{"last_name":"Kwong","full_name":"Kwong, N. H.","first_name":"N. H."},{"last_name":"Baudin","first_name":"E.","full_name":"Baudin, E."},{"last_name":"Lafont","first_name":"O.","full_name":"Lafont, O."},{"last_name":"Tignon","first_name":"J.","full_name":"Tignon, J."},{"last_name":"Leung","full_name":"Leung, P. T.","first_name":"P. T."},{"last_name":"Chan","full_name":"Chan, Ch. K. P.","first_name":"Ch. K. P."},{"full_name":"Babilon, M.","first_name":"M.","last_name":"Babilon"},{"first_name":"Stefan","full_name":"Schumacher, Stefan","orcid":"0000-0003-4042-4951","last_name":"Schumacher","id":"27271"},{"full_name":"Binder, R.","first_name":"R.","last_name":"Binder"}],"date_created":"2019-09-19T13:50:06Z","status":"public","volume":35,"date_updated":"2023-02-10T15:02:47Z","doi":"10.1364/josab.35.000146","language":[{"iso":"eng"}],"title":"Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities","department":[{"_id":"15"},{"_id":"170"},{"_id":"297"},{"_id":"230"},{"_id":"429"},{"_id":"27"}],"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","publication_identifier":{"issn":["0740-3224","1520-8540"]}},{"project":[{"_id":"32","grant_number":"PL 595/2-1","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","publication_identifier":{"issn":["1943-0663"],"eissn":["1943-0671"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots","external_id":{"arxiv":["1703.02283"]},"language":[{"iso":"eng"}],"doi":"10.1109/LES.2017.2760923","date_updated":"2022-01-06T06:54:18Z","status":"public","date_created":"2017-07-25T14:41:08Z","volume":10,"author":[{"id":"24135","last_name":"Lass","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","publication":"Embedded Systems Letters","user_id":"16153","abstract":[{"lang":"eng","text":"Approximate computing has shown to provide new ways to improve performance\r\nand power consumption of error-resilient applications. While many of these\r\napplications can be found in image processing, data classification or machine\r\nlearning, we demonstrate its suitability to a problem from scientific\r\ncomputing. Utilizing the self-correcting behavior of iterative algorithms, we\r\nshow that approximate computing can be applied to the calculation of inverse\r\nmatrix p-th roots which are required in many applications in scientific\r\ncomputing. Results show great opportunities to reduce the computational effort\r\nand bandwidth required for the execution of the discussed algorithm, especially\r\nwhen targeting special accelerator hardware."}],"type":"journal_article","citation":{"chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters 10, no. 2 (2018): 33–36. https://doi.org/10.1109/LES.2017.2760923.","apa":"Lass, M., Kühne, T., & Plessl, C. (2018). Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters, 10(2), 33–36. https://doi.org/10.1109/LES.2017.2760923","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters. 2018;10(2):33-36. doi:10.1109/LES.2017.2760923","bibtex":"@article{Lass_Kühne_Plessl_2018, title={Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots}, volume={10}, DOI={10.1109/LES.2017.2760923}, number={2}, journal={Embedded Systems Letters}, publisher={IEEE}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2018}, pages={33–36} }","mla":"Lass, Michael, et al. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters, vol. 10, no. 2, IEEE, 2018, pp. 33–36, doi:10.1109/LES.2017.2760923.","short":"M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters 10 (2018) 33–36.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” Embedded Systems Letters, vol. 10, no. 2, pp. 33–36, 2018."},"year":"2018","page":" 33-36","issue":"2","_id":"20","intvolume":" 10"},{"title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","publication_identifier":{"issn":["1936-7406"]},"publication_status":"published","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1145/3053687","date_updated":"2023-09-26T13:23:58Z","language":[{"iso":"eng"}],"ddc":["000"],"user_id":"15278","abstract":[{"text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.","lang":"eng"}],"volume":10,"date_created":"2017-07-25T14:17:32Z","status":"public","has_accepted_license":"1","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","keyword":["coldboot"],"file_date_updated":"2018-11-02T16:04:14Z","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"full_name":"Mittendorf, Robert","first_name":"Robert","last_name":"Mittendorf"},{"last_name":"Löcke","full_name":"Löcke, Thomas","first_name":"Thomas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"Association for Computing Machinery (ACM)","quality_controlled":"1","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-11-02T16:04:14Z","creator":"ups","file_id":"5322","file_size":2131617,"access_level":"closed","file_name":"a24-riebler.pdf","date_created":"2018-11-02T16:04:14Z"}],"issue":"3","_id":"18","intvolume":" 10","page":"24:1-24:23","type":"journal_article","citation":{"ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi: 10.1145/3053687.","short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687.","bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={10.1145/3053687}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687","apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23. https://doi.org/10.1145/3053687"},"year":"2017"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:24:38Z","doi":"10.23919/FPL.2017.8056844","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"},{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"Flexible FPGA design for FDTD using OpenCL","type":"conference","citation":{"ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","apa":"Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844","ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844."},"year":"2017","_id":"1592","file_date_updated":"2018-11-02T15:02:28Z","keyword":["tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","quality_controlled":"1","publisher":"IEEE","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"file":[{"date_created":"2018-11-02T15:02:28Z","file_name":"08056844.pdf","access_level":"closed","file_size":230235,"file_id":"5291","creator":"ups","content_type":"application/pdf","date_updated":"2018-11-02T15:02:28Z","relation":"main_file","success":1}],"date_created":"2018-03-22T11:10:23Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures."}],"ddc":["000"],"user_id":"15278"},{"publication":"Journal of Physics: Conference Series","department":[{"_id":"27"},{"_id":"518"}],"publisher":"IOP Publishing","quality_controlled":"1","author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Vandelli","full_name":"Vandelli, Wainer","first_name":"Wainer"}],"volume":898,"date_created":"2018-03-22T10:51:20Z","status":"public","title":"High-Throughput and Low-Latency Network Communication with NetIO","user_id":"15278","type":"journal_article","citation":{"bibtex":"@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={10.1088/1742-6596/898/8/082003}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }","mla":"Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series, vol. 898, 082003, IOP Publishing, 2017, doi:10.1088/1742-6596/898/8/082003.","chicago":"Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series 898 (2017). https://doi.org/10.1088/1742-6596/898/8/082003.","apa":"Schumacher, J., Plessl, C., & Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series, 898, Article 082003. https://doi.org/10.1088/1742-6596/898/8/082003","ama":"Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series. 2017;898. doi:10.1088/1742-6596/898/8/082003","ieee":"J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi: 10.1088/1742-6596/898/8/082003.","short":"J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017)."},"year":"2017","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:24:19Z","_id":"1589","intvolume":" 898","doi":"10.1088/1742-6596/898/8/082003","article_number":"082003"},{"status":"public","date_created":"2017-07-25T14:36:16Z","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"publication_status":"published","publisher":"IEEE","author":[{"last_name":"Lass","id":"24135","first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632"},{"last_name":"Leibenger","full_name":"Leibenger, Dominik","first_name":"Dominik"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"}],"keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. 41st Conference on Local Computer Networks (LCN)","user_id":"24135","title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","abstract":[{"lang":"eng","text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments."}],"language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016.","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.","bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.","ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11","apa":"Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11."},"year":"2016","doi":"10.1109/lcn.2016.11","date_updated":"2022-01-06T06:53:56Z","_id":"19"},{"user_id":"477","title":"Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"date_created":"2018-11-07T16:15:51Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"author":[{"full_name":"Wüllrich, Gunnar","first_name":"Gunnar","last_name":"Wüllrich"}],"publisher":"Universität Paderborn","_id":"5420","date_updated":"2022-01-06T07:01:53Z","supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"language":[{"iso":"eng"}],"year":"2016","type":"mastersthesis","citation":{"bibtex":"@book{Wüllrich_2016, title={Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment}, publisher={Universität Paderborn}, author={Wüllrich, Gunnar}, year={2016} }","mla":"Wüllrich, Gunnar. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.","ama":"Wüllrich G. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn; 2016.","apa":"Wüllrich, G. (2016). Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn.","chicago":"Wüllrich, Gunnar. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.","ieee":"G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.","short":"G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment, Universität Paderborn, 2016."}},{"year":"2016","citation":{"short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","apa":"Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC).","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:26:17Z","_id":"24","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","file_date_updated":"2018-11-14T12:38:45Z","department":[{"_id":"27"},{"_id":"518"}],"file":[{"file_size":129552,"file_id":"5602","creator":"kenter","date_updated":"2018-11-14T12:38:45Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"paper_26.pdf","date_created":"2018-11-14T12:38:45Z","access_level":"closed"}],"has_accepted_license":"1","status":"public","project":[{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"}],"date_created":"2017-07-26T15:00:43Z","title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","ddc":["004"],"user_id":"15278"},{"user_id":"24135","title":"Modeling and simulation of metallic, particle-damped spheres for lightweight materials","abstract":[{"lang":"eng","text":"Lightweight materials play an ever growing role in today's world. Saving on the mass of a machine will usually translate into a lower energy consumption. However, lightweight applications are prone to develop performance problems due to vibration induced by the operation of the machine. The Fraunhofer Institute for Manufacturing Technology and Advanced Materials in Dresden conducts research into the damping properties of composite materials. They are experimenting with hollow, particle filled spheres embedded in the lightweight material. Such a system is the technical motivation of this thesis. Ultimately, a numerical experiment to derive the coefficient of restitution is required. The simulation developed in this thesis is based on a discrete element method to track the individual particle and sphere trajectories. Based on a potential based approach for the particle interactions deployed in molecular dynamics, the behavior of the particles can be controlled effectively. The simulated volume is using reflecting boundaries and encloses the hollow sphere. In this work, a highly flexible memory structure was used with a linked cell approach to cope with the highly flexible mass of particles. This allows for a linear complexity of the method in regard to the particle number by reducing the computational overhead of the interaction computation. Multiple numerical experiments show the great effect the particles have on the damping behavior of the system."},{"lang":"ger","text":"In vielen technischen Anwendungen spielt heute der Leichtbau eine große Rolle, denn durch Gewichtseinsparungen lässt sich auch Energie einsparen. Allerdings birgt der Leichtbau die Gefahr einer erhöhten Störanfälligkeit gegenüber Vibrationen, die durch die Operation von Maschinen entstehen können. Das Fraunhofer Institut für Fertigungstechnik und Angewandte Materialforschung in Dresden beschäftigt sich mit den Möglichkeiten einer Schwingungsdämpfung durch Verbundwerkstoffe. Dabei wird in die Leichtbaustruktur eine Vielzahl von Hohlkugeln eingebracht, die mit Keramikpartikeln gefüllt sind. Diese Fragestellung bildet die technische Motivation für diese Arbeit. Ziel ist, ein Experiment zur Bestimmung des Restitutionskoeffizienten numerisch nachzubilden. Die Simulation basiert auf einer Diskreten Elemente Methode um die Trajektorien der einzelnen Partikel und der Kugel berechnen zu können. Basierend auf einem Potentialansatz für die Interaktionsberechnung in der Molekulardynamik kann das Reibungsverhalten vielfältig angepasst werden. Das Simulationsvolumen wird durch reflektierende Randbedingungen abgeschlossen und umfasst die Kugelhülle. Dazu kam eine hochflexible Speicherstruktur zum Einsatz, um die heterogene Verteilung der Partikel im Raum mit einer effizienten Linked Cell Methode abbilden zu können. Dadurch wird eine in der Partikelzahl lineare Komplexität erreicht. Umfangreiche numerische Experimente zeigen den großen Effekt der Partikelfüllung auf das Dämpfungsverhalten."}],"date_created":"2017-07-26T15:19:44Z","status":"public","department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"author":[{"last_name":"Steinle","first_name":"Tobias","full_name":"Steinle, Tobias"}],"date_updated":"2022-01-06T06:59:09Z","_id":"33","supervisor":[{"first_name":"Andrea","full_name":"Walther, Andrea","last_name":"Walther"},{"full_name":"Vrabec, Jadran","first_name":"Jadran","last_name":"Vrabec"}],"language":[{"iso":"eng"}],"type":"dissertation","citation":{"ama":"Steinle T. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials.; 2016.","apa":"Steinle, T. (2016). Modeling and simulation of metallic, particle-damped spheres for lightweight materials.","chicago":"Steinle, Tobias. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials, 2016.","bibtex":"@book{Steinle_2016, title={Modeling and simulation of metallic, particle-damped spheres for lightweight materials}, author={Steinle, Tobias}, year={2016} }","mla":"Steinle, Tobias. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials. 2016.","short":"T. Steinle, Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials, 2016.","ieee":"T. Steinle, Modeling and simulation of metallic, particle-damped spheres for lightweight materials. 2016."},"year":"2016","main_file_link":[{"url":"http://nbn-resolving.de/urn:nbn:de:hbz:466:2-24042"}]},{"series_title":"Mathematics in Industry","year":"2016","citation":{"short":"M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.","ieee":"M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641.","chicago":"Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.","ama":"Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87","apa":"Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87","bibtex":"@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }","mla":"Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87."},"type":"conference","page":"633-641","_id":"34","intvolume":" 22","date_updated":"2022-01-06T06:59:14Z","doi":"10.1007/978-3-319-23413-7_87","author":[{"full_name":"Dellnitz, Michael","first_name":"Michael","last_name":"Dellnitz"},{"full_name":"Eckstein, Julian","first_name":"Julian","last_name":"Eckstein"},{"last_name":"Flaßkamp","full_name":"Flaßkamp, Kathrin","first_name":"Kathrin"},{"first_name":"Patrick","full_name":"Friedel, Patrick","last_name":"Friedel"},{"last_name":"Horenkamp","first_name":"Christian","full_name":"Horenkamp, Christian"},{"last_name":"Köhler","full_name":"Köhler, Ulrich","first_name":"Ulrich"},{"first_name":"Sina","full_name":"Ober-Blöbaum, Sina","last_name":"Ober-Blöbaum"},{"last_name":"Peitz","full_name":"Peitz, Sebastian","first_name":"Sebastian"},{"last_name":"Tiemeyer","full_name":"Tiemeyer, Sebastian","first_name":"Sebastian"}],"publisher":"Springer International Publishing","publication":"Progress in Industrial Mathematics at ECMI","department":[{"_id":"27"},{"_id":"101"}],"status":"public","date_created":"2017-07-26T15:25:33Z","volume":22,"publication_identifier":{"issn":["2212-0173"]},"place":"Cham","user_id":"24135","title":"Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control"},{"year":"2016","citation":{"short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }"},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:27:21Z","_id":"171","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:25Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:39:46Z","publication":"Workshop on Reconfigurable Computing (WRC)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-21T12:39:46Z","creator":"florida","file_id":"1538","file_size":54421,"access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","date_created":"2018-03-21T12:39:46Z"}],"title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","ddc":["040"],"user_id":"15278"},{"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}],"abstract":[{"text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.","lang":"eng"}],"ddc":["040"],"user_id":"15278","quality_controlled":"1","author":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"EDA Consortium / IEEE","file_date_updated":"2018-03-21T12:41:55Z","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file":[{"file_size":261356,"creator":"florida","file_id":"1541","date_updated":"2018-03-21T12:41:55Z","content_type":"application/pdf","success":1,"relation":"main_file","date_created":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf","access_level":"closed"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:24Z","_id":"168","citation":{"chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917."},"type":"conference","year":"2016","page":"912-917"},{"page":"91-111","type":"journal_article","citation":{"chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021."},"year":"2016","_id":"165","intvolume":" 55","file_date_updated":"2018-03-21T12:45:47Z","publication":"Computers and Electrical Engineering","author":[{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","publisher":"Elsevier","file":[{"creator":"florida","file_id":"1544","file_size":3037854,"success":1,"relation":"main_file","date_updated":"2018-03-21T12:45:47Z","content_type":"application/pdf","file_name":"165-1-s2.0-S0045790616301021-main.pdf","date_created":"2018-03-21T12:45:47Z","access_level":"closed"}],"volume":55,"date_created":"2017-10-17T12:41:24Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes."}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:26:38Z","doi":"10.1016/j.compeleceng.2016.04.021","department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"issn":["0045-7906"]},"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code"},{"_id":"161","date_updated":"2022-01-06T06:52:43Z","supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"citation":{"short":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing, Universität Paderborn, 2016.","ieee":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.","ama":"Kenter T. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn; 2016.","apa":"Kenter, T. (2016). Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn.","chicago":"Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.","bibtex":"@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016} }","mla":"Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016."},"year":"2016","type":"dissertation","user_id":"3145","ddc":["040"],"title":"Reconfigurable Accelerators in the World of General-Purpose Computing","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"date_created":"2017-10-17T12:41:23Z","status":"public","has_accepted_license":"1","file":[{"file_size":5039555,"file_id":"1545","creator":"florida","date_updated":"2018-03-21T12:46:48Z","content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-03-21T12:46:48Z","file_name":"161kenter16_diss_submission_print_16-08-26.pdf","access_level":"closed"}],"department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:46:48Z","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"}],"publisher":"Universität Paderborn"},{"doi":"10.1007/978-3-319-26408-0_13","date_updated":"2023-09-26T13:25:38Z","language":[{"iso":"eng"}],"title":"ReconOS","place":"Cham","publication_status":"published","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"editor":[{"last_name":"Koch","full_name":"Koch, Dirk","first_name":"Dirk"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"full_name":"Ziener, Daniel","first_name":"Daniel","last_name":"Ziener"}],"project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"29","page":"227-244","citation":{"ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13"},"type":"book_chapter","year":"2016","user_id":"15278","abstract":[{"text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.","lang":"eng"}],"date_created":"2017-07-26T15:07:06Z","status":"public","publication":"FPGAs for Software Programmers","publisher":"Springer International Publishing","quality_controlled":"1","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"}]},{"abstract":[{"text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"creator":"aloesch","file_id":"5613","file_size":833054,"relation":"main_file","success":1,"date_updated":"2018-11-14T13:20:32Z","content_type":"application/pdf","file_name":"chapter8.pdf","date_created":"2018-11-14T13:20:32Z","access_level":"closed"}],"author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","publisher":"Springer International Publishing","file_date_updated":"2018-11-14T13:20:32Z","publication":"Self-aware Computing Systems","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:22Z","_id":"156","year":"2016","type":"book_chapter","citation":{"ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. 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Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. 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Tölke, Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn, 2016.","short":"C. Tölke, Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung, Universität Paderborn, 2016.","mla":"Tölke, Christian. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn, 2016.","bibtex":"@book{Tölke_2016, title={Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung}, publisher={Universität Paderborn}, author={Tölke, Christian}, year={2016} }","chicago":"Tölke, Christian. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn, 2016.","ama":"Tölke C. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn; 2016.","apa":"Tölke, C. (2016). Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn."},"supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"language":[{"iso":"eng"}]},{"status":"public","date_created":"2017-07-26T15:02:20Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"author":[{"id":"24135","last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","publication":"Workshop on Approximate Computing (AC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"Using Approximate Computing in Scientific Codes","user_id":"15278","year":"2016","type":"conference","citation":{"mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.","apa":"Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC).","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.","short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016."},"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:25:17Z","_id":"25"},{"status":"public","has_accepted_license":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_created":"2017-07-26T15:16:31Z","file":[{"content_type":"application/pdf","date_updated":"2019-01-11T11:56:55Z","success":1,"relation":"main_file","file_size":394563,"file_id":"6626","creator":"deffel","access_level":"closed","file_name":"wrc_upb_polimi_final.pdf","date_created":"2019-01-11T11:56:55Z"}],"author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Ettore M. G.","full_name":"Trainiti, Ettore M. G.","last_name":"Trainiti"},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2019-01-11T11:56:55Z","publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","user_id":"15278","ddc":["040"],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","language":[{"iso":"eng"}],"type":"conference","year":"2016","citation":{"mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016."},"date_updated":"2023-09-26T13:25:59Z","_id":"31"},{"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1109/RTSI.2016.7740545","date_updated":"2023-09-26T13:28:11Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"date_created":"2017-10-17T12:41:18Z","has_accepted_license":"1","status":"public","file":[{"date_updated":"2018-03-21T13:01:09Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":184334,"file_id":"1560","creator":"florida","access_level":"closed","file_name":"138-07740545.pdf","date_created":"2018-03-21T13:01:09Z"}],"file_date_updated":"2018-03-21T13:01:09Z","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Trainiti","first_name":"Ettore M. G. ","full_name":"Trainiti, Ettore M. G. "},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"last_name":"Del Sozzo","first_name":"Emanuele","full_name":"Del Sozzo, Emanuele"},{"last_name":"Santambrogio","full_name":"Santambrogio, Marco D. ","first_name":"Marco D. "},{"last_name":"Bolchini","first_name":"Christina","full_name":"Bolchini, Christina"}],"quality_controlled":"1","publisher":"IEEE","_id":"138","page":"1-5","year":"2016","type":"conference","citation":{"chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545."}},{"citation":{"ieee":"F. Wallaschek, Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn, 2015.","short":"F. Wallaschek, Accelerating Programmable Logic Controllers with the Use of FPGAs, Universität Paderborn, 2015.","bibtex":"@book{Wallaschek_2015, title={Accelerating Programmable Logic Controllers with the use of FPGAs}, publisher={Universität Paderborn}, author={Wallaschek, Felix}, year={2015} }","mla":"Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015.","chicago":"Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015.","ama":"Wallaschek F. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn; 2015.","apa":"Wallaschek, F. (2015). Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn."},"year":"2015","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"date_updated":"2022-01-06T07:01:52Z","_id":"5419","status":"public","date_created":"2018-11-07T16:14:30Z","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"publisher":"Universität Paderborn","author":[{"last_name":"Wallaschek","full_name":"Wallaschek, Felix","first_name":"Felix"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"Accelerating Programmable Logic Controllers with the use of FPGAs","user_id":"477"},{"title":"Aktuelles Schlagwort: Approximate Computing","user_id":"15278","status":"public","date_created":"2018-03-23T13:58:34Z","publisher":"Springer","quality_controlled":"1","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Schreier","full_name":"Schreier, Peter J.","first_name":"Peter J."}],"publication":"Informatik Spektrum","department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"keyword":["approximate computing","survey"],"doi":"10.1007/s00287-015-0911-z","issue":"5","date_updated":"2023-09-26T13:30:22Z","_id":"1768","citation":{"mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.","apa":"Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z","ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399."},"year":"2015","type":"journal_article","page":"396-399","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"type":"mastersthesis","citation":{"bibtex":"@book{Funke_2015, title={An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures}, publisher={Universität Paderborn}, author={Funke, Lukas}, year={2015} }","mla":"Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015.","ama":"Funke L. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn; 2015.","apa":"Funke, L. (2015). An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn.","chicago":"Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015.","ieee":"L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn, 2015.","short":"L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures, Universität Paderborn, 2015."},"year":"2015","date_updated":"2022-01-06T07:01:52Z","_id":"5413","publisher":"Universität Paderborn","author":[{"first_name":"Lukas","full_name":"Funke, Lukas","last_name":"Funke"}],"department":[{"_id":"27"},{"_id":"518"}],"status":"public","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2018-11-07T15:10:35Z","user_id":"477","title":"An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"external_id":{"arxiv":["1412.3906"]},"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:29:59Z","oa":"1","author":[{"full_name":"Damschen, Marvin","first_name":"Marvin","last_name":"Damschen"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file_date_updated":"2019-08-01T09:10:44Z","publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","file":[{"date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf","access_level":"open_access","file_size":1176620,"creator":"florida","file_id":"1442","content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:51Z","abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"ddc":["040"],"user_id":"15278","year":"2015","type":"conference","citation":{"bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015."},"_id":"303"},{"_id":"296","intvolume":" 2015","article_number":"859425","citation":{"ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425."},"type":"journal_article","year":"2015","abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}],"ddc":["040"],"user_id":"15278","publication":"International Journal of Reconfigurable Computing (IJRC)","file_date_updated":"2018-03-20T07:47:56Z","quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"Hindawi","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:47:56Z","creator":"florida","file_id":"1444","file_size":2993898,"access_level":"closed","date_created":"2018-03-20T07:47:56Z","file_name":"296-859425.pdf"}],"volume":2015,"date_created":"2017-10-17T12:41:49Z","has_accepted_license":"1","status":"public","date_updated":"2023-09-26T13:29:08Z","doi":"10.1155/2015/859425","language":[{"iso":"eng"}],"title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}]},{"doi":"10.1088/1742-6596/664/8/082050","article_number":"082050","_id":"1775","intvolume":" 664","date_updated":"2023-09-26T13:31:23Z","year":"2015","type":"journal_article","citation":{"ieee":"J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.","short":"J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015).","mla":"Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.","bibtex":"@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }","apa":"Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050","ama":"Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050","chicago":"Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series 664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050."},"language":[{"iso":"eng"}],"title":"FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades","user_id":"15278","abstract":[{"text":"The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.","lang":"eng"}],"volume":664,"date_created":"2018-03-23T14:19:27Z","status":"public","publication":"Journal of Physics: Conference Series","department":[{"_id":"27"},{"_id":"518"}],"publisher":"IOP Publishing","author":[{"last_name":"Anderson","full_name":"Anderson, J","first_name":"J"},{"first_name":"A","full_name":"Borga, A","last_name":"Borga"},{"first_name":"H","full_name":"Boterenbrood, H","last_name":"Boterenbrood"},{"full_name":"Chen, H","first_name":"H","last_name":"Chen"},{"full_name":"Chen, K","first_name":"K","last_name":"Chen"},{"last_name":"Drake","first_name":"G","full_name":"Drake, G"},{"full_name":"Francis, D","first_name":"D","last_name":"Francis"},{"first_name":"B","full_name":"Gorini, B","last_name":"Gorini"},{"last_name":"Lanni","first_name":"F","full_name":"Lanni, F"},{"first_name":"G","full_name":"Lehmann Miotto, G","last_name":"Lehmann Miotto"},{"last_name":"Levinson","full_name":"Levinson, L","first_name":"L"},{"last_name":"Narevicius","first_name":"J","full_name":"Narevicius, J"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Roich, A","first_name":"A","last_name":"Roich"},{"full_name":"Ryu, S","first_name":"S","last_name":"Ryu"},{"full_name":"Schreuder, F","first_name":"F","last_name":"Schreuder"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"last_name":"Vermeulen","full_name":"Vermeulen, J","first_name":"J"},{"last_name":"Zhang","first_name":"J","full_name":"Zhang, J"}],"quality_controlled":"1"},{"user_id":"15278","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"first_name":"Jörn","full_name":"Schumacher, Jörn","last_name":"Schumacher"},{"last_name":"T. Anderson","full_name":"T. Anderson, J.","first_name":"J."},{"last_name":"Borga","full_name":"Borga, A.","first_name":"A."},{"full_name":"Boterenbrood, H.","first_name":"H.","last_name":"Boterenbrood"},{"first_name":"H.","full_name":"Chen, H.","last_name":"Chen"},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"last_name":"Drake","first_name":"G.","full_name":"Drake, G."},{"first_name":"D.","full_name":"Francis, D.","last_name":"Francis"},{"full_name":"Gorini, B.","first_name":"B.","last_name":"Gorini"},{"last_name":"Lanni","first_name":"F.","full_name":"Lanni, F."},{"last_name":"Lehmann-Miotto","full_name":"Lehmann-Miotto, Giovanna","first_name":"Giovanna"},{"full_name":"Levinson, L.","first_name":"L.","last_name":"Levinson"},{"first_name":"J.","full_name":"Narevicius, J.","last_name":"Narevicius"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Roich, A.","first_name":"A.","last_name":"Roich"},{"last_name":"Ryu","full_name":"Ryu, S.","first_name":"S."},{"first_name":"F.","full_name":"P. Schreuder, F.","last_name":"P. Schreuder"},{"last_name":"Vandelli","full_name":"Vandelli, Wainer","first_name":"Wainer"},{"full_name":"Vermeulen, J.","first_name":"J.","last_name":"Vermeulen"},{"full_name":"Zhang, J.","first_name":"J.","last_name":"Zhang"}],"publisher":"ACM","quality_controlled":"1","date_created":"2018-03-23T14:09:33Z","status":"public","_id":"1773","date_updated":"2023-09-26T13:31:01Z","doi":"10.1145/2675743.2771824","language":[{"iso":"eng"}],"year":"2015","type":"conference","citation":{"short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824."}},{"date_updated":"2022-01-06T07:01:52Z","_id":"5416","language":[{"iso":"eng"}],"supervisor":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"citation":{"chicago":"Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.","ama":"Löcke T. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn; 2015.","apa":"Löcke, T. (2015). Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn.","bibtex":"@book{Löcke_2015, title={Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems}, publisher={Universität Paderborn}, author={Löcke, Thomas}, year={2015} }","mla":"Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.","short":"T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems, Universität Paderborn, 2015.","ieee":"T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015."},"year":"2015","type":"mastersthesis","user_id":"477","title":"Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems","status":"public","date_created":"2018-11-07T16:06:53Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"author":[{"last_name":"Löcke","first_name":"Thomas","full_name":"Löcke, Thomas"}],"publisher":"Universität Paderborn","department":[{"_id":"27"},{"_id":"518"}]},{"supervisor":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"citation":{"chicago":"Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University, 2015.","apa":"Lass, M. (2015). Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University.","ama":"Lass M. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University; 2015.","mla":"Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn University, 2015.","bibtex":"@book{Lass_2015, place={Paderborn}, title={Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing}, publisher={Paderborn University}, author={Lass, Michael}, year={2015} }","short":"M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing, Paderborn University, Paderborn, 2015.","ieee":"M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University, 2015."},"year":"2015","type":"mastersthesis","date_updated":"2022-01-06T06:53:23Z","_id":"1794","department":[{"_id":"27"},{"_id":"518"}],"publisher":"Paderborn University","author":[{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"}],"date_created":"2018-03-26T15:24:10Z","status":"public","abstract":[{"text":"Demands for computational power and energy efficiency of computing devices are steadily increasing. At the same time, following classic methods to increase speed and reduce energy consumption of these devices becomes increasingly difficult, bringing alternative methods into focus. One of these methods is approximate computing which utilizes the fact that small errors in computations are acceptable in many applications in order to allow acceleration of these computations or to increase energy efficiency. This thesis develops elements of a workflow that can be followed to apply approximate computing to existing applications. It proposes a novel heuristic approach to the localization of code paths that are suitable to approximate computing based on findings in recent research. Additionally, an approach to identification of approximable instructions within these code paths is proposed and used to implement simulation of approximation. The parts of the workflow are implemented with the goal to lay the foundation for a partly automated toolflow. Evaluation of the developed techniques shows that the proposed methods can help providing a convenient workflow, facilitating the first steps into the application of approximate computing.","lang":"eng"}],"place":"Paderborn","user_id":"24135","title":"Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing"},{"user_id":"3118","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","place":"Berlin","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"status":"public","date_created":"2019-07-10T09:36:58Z","project":[{"_id":"30","grant_number":"01|H11004","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"publication_identifier":{"isbn":["978-3-8325-4155-2"]},"publisher":"Logos Verlag Berlin GmbH","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"}],"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"date_updated":"2022-01-06T06:50:48Z","_id":"10624","supervisor":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"language":[{"iso":"eng"}],"citation":{"apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015."},"year":"2015","type":"dissertation","page":"183"},{"type":"journal_article","year":"2015","citation":{"bibtex":"@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296}, number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian and Dellnitz, Michael}, year={2015}, pages={613–614} }","mla":"Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no. 1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296.","chicago":"Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1 (2015): 613–14. https://doi.org/10.1002/pamm.201510296.","ama":"Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296","apa":"Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614. https://doi.org/10.1002/pamm.201510296","ieee":"S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614, 2015.","short":"S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614."},"page":"613-614","doi":"10.1002/pamm.201510296","issue":"1","date_updated":"2022-01-06T06:53:19Z","_id":"1774","intvolume":" 15","volume":15,"publication_identifier":{"issn":["1617-7061"]},"status":"public","date_created":"2018-03-23T14:14:24Z","publisher":"WILEY-VCH Verlag","author":[{"last_name":"Peitz","first_name":"Sebastian","full_name":"Peitz, Sebastian"},{"full_name":"Dellnitz, Michael","first_name":"Michael","last_name":"Dellnitz"}],"department":[{"_id":"27"},{"_id":"101"}],"publication":"PAMM","title":"Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction","user_id":"24135","abstract":[{"lang":"eng","text":"In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100."}]},{"date_updated":"2022-01-06T06:53:19Z","doi":"10.1109/MC.2015.205","language":[{"iso":"eng"}],"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"_id":"1772","intvolume":" 48","issue":"7","page":"18-20","type":"journal_article","year":"2015","citation":{"ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205."},"user_id":"16153","ddc":["000"],"file":[{"file_size":5605009,"file_id":"5313","creator":"ups","content_type":"application/pdf","date_updated":"2018-11-02T15:47:45Z","success":1,"relation":"main_file","date_created":"2018-11-02T15:47:45Z","file_name":"07163237.pdf","access_level":"closed"}],"file_date_updated":"2018-11-02T15:47:45Z","publication":"IEEE Computer","keyword":["self-awareness","self-expression"],"publisher":"IEEE Computer Society","author":[{"full_name":"Torresen, Jim","first_name":"Jim","last_name":"Torresen"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Xin","full_name":"Yao, Xin","last_name":"Yao"}],"date_created":"2018-03-23T14:06:12Z","has_accepted_license":"1","status":"public","volume":48}]