Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain - Nickchen, Tobias; Engels, Gregor; Lohn, Johannes (Industrializing Additive Manufacturing)

A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices - Richters, Dorothee; Lass, Michael; Walther, Andrea; Plessl, Christian; Kühne, Thomas (Communications in Computational Physics)
We address the general mathematical problem of computing the inverse p-th root of a given matrix in an efficient way. A new method to construct iteration functions that allow calculating arbitrary p-th roots and their inverses of symmetric positive definite matrices is presented. We show that the order of convergence is at least quadratic and that adaptively adjusting a parameter q always leads to an even faster convergence. In this way, a better performance than with previously known iteration schemes is achieved. The efficiency of the iterative functions is demonstrated for various matrices with different densities, condition numbers and spectral radii.

Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs - Riebler, Heinrich

FPGAs im Rechenzentrum - Platzner, Marco; Plessl, Christian (Informatik Spektrum)

OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs - Gorlani, Paolo; Kenter, Tobias; Plessl, Christian (Proceedings of the International Conference on Field-Programmable Technology (FPT))
Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.

Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL - Riebler, Heinrich; Vaz, Gavin Francis; Kenter, Tobias; Plessl, Christian (ACM Trans. Archit. Code Optim. (TACO))
Keywords: htrop

A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems - Keller, Axel (Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP))
This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation.
Keywords: Scheduling Planning Mapping Workload management

A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices - Lass, Michael; Mohr, Stephan; Wiebeler, Hendrik; Kühne, Thomas; Plessl, Christian (Proc. Platform for Advanced Scientific Computing (PASC) Conference)
We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures. We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.
Keywords: approximate computing; linear algebra; matrix inversion; matrix p-th roots; numeric algorithm; parallel computing

Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA - Ramaswami, Arjun
Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging. In this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs. This FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs.
Keywords: FFT: FPGA; CP2K; OpenCL

Automated Code Acceleration Targeting Heterogeneous OpenCL Devices - Riebler, Heinrich; Vaz, Gavin Francis; Kenter, Tobias; Plessl, Christian (Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP))
Keywords: htrop

OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes - Kenter, Tobias; Mahale, Gopinath; Alhaddad, Samer; Grynko, Yevgen; Schmitt, Christian; Afzal, Ayesha; Hannig, Frank; Förstner, Jens; Plessl, Christian (Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM))
The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.
Keywords: tet_topic_hpc

Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL - Gadewar, Onkar

Sprint diagnostic with GPS and inertial sensor fusion - Mertens, Jan Cedric; Boschmann, Alexander; Schmidt, M.; Plessl, Christian (Sports Engineering)

Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform - Filmwala, Tasneem

Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities - Luk, Samuel M. H.; Lewandowski, P.; Kwong, N. H.; Baudin, E.; Lafont, O.; Tignon, J.; Leung, P. T.; Chan, Ch. K. P.; Babilon, M.; Schumacher, Stefan; Binder, R. (Journal of the Optical Society of America B)

Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots - Lass, Michael; Kühne, Thomas; Plessl, Christian (Embedded Systems Letters)
Approximate computing has shown to provide new ways to improve performance and power consumption of error-resilient applications. While many of these applications can be found in image processing, data classification or machine learning, we demonstrate its suitability to a problem from scientific computing. Utilizing the self-correcting behavior of iterative algorithms, we show that approximate computing can be applied to the calculation of inverse matrix p-th roots which are required in many applications in scientific computing. Results show great opportunities to reduce the computational effort and bandwidth required for the execution of the discussed algorithm, especially when targeting special accelerator hardware.

Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs - Riebler, Heinrich; Lass, Michael; Mittendorf, Robert; Löcke, Thomas; Plessl, Christian (ACM Transactions on Reconfigurable Technology and Systems (TRETS))
Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance. We evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.
Keywords: coldboot

Flexible FPGA design for FDTD using OpenCL - Kenter, Tobias; Förstner, Jens; Plessl, Christian (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.
Keywords: tet_topic_hpc

High-Throughput and Low-Latency Network Communication with NetIO - Schumacher, Jörn; Plessl, Christian; Vandelli, Wainer (Journal of Physics: Conference Series)

Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension - Lass, Michael; Leibenger, Dominik; Sorge, Christoph (Proc. 41st Conference on Local Computer Networks (LCN))
Version Control Systems (VCS) are a valuable tool for software development and document management. Both client/server and distributed (Peer-to-Peer) models exist, with the latter (e.g., Git and Mercurial) becoming increasingly popular. Their distributed nature introduces complications, especially concerning security: it is hard to control the dissemination of contents stored in distributed VCS as they rely on replication of complete repositories to any involved user. We overcome this issue by designing and implementing a concept for cryptography-enforced access control which is transparent to the user. Use of field-tested schemes (end-to-end encryption, digital signatures) allows for strong security, while adoption of convergent encryption and content-defined chunking retains storage efficiency. The concept is seamlessly integrated into Mercurial---respecting its distributed storage concept---to ensure practical usability and compatibility to existing deployments.
Keywords: access control; distributed version control systems; mercurial; peer-to-peer; convergent encryption; confidentiality; authenticity