TY - CHAP AU - Hansmeier, Tim AU - Kenter, Tobias AU - Meyer, Marius AU - Riebler, Heinrich AU - Platzner, Marco AU - Plessl, Christian ED - Haake, Claus-Jochen ED - Meyer auf der Heide, Friedhelm ED - Platzner, Marco ED - Wachsmuth, Henning ED - Wehrheim, Heike ID - 45893 T2 - On-The-Fly Computing -- Individualized IT-services in dynamic markets TI - Compute Centers I: Heterogeneous Execution Environments VL - 412 ER - TY - CHAP AU - Alt, Christoph AU - Kenter, Tobias AU - Faghih-Naini, Sara AU - Faj, Jennifer AU - Opdenhövel, Jan-Oliver AU - Plessl, Christian AU - Aizinger, Vadym AU - Hönig, Jan AU - Köstler, Harald ID - 46191 SN - 0302-9743 T2 - Lecture Notes in Computer Science TI - Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline ER - TY - CHAP AU - Ramaswami, Arjun AU - Kenter, Tobias AU - Kühne, Thomas AU - Plessl, Christian ID - 29936 SN - 0302-9743 T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing ER - TY - CHAP AB - Solving partial differential equations on unstructured grids is a cornerstone of engineering and scientific computing. Nowadays, heterogeneous parallel platforms with CPUs, GPUs, and FPGAs enable energy-efficient and computationally demanding simulations. We developed the HighPerMeshes C++-embedded Domain-Specific Language (DSL) for bridging the abstraction gap between the mathematical and algorithmic formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different parallel programming and runtime models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPerMeshes DSL, and demonstrate its usage with three examples, a Poisson and monodomain problem, respectively, solved by the continuous finite element method, and the discontinuous Galerkin method for Maxwell’s equation. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. Finally, the achievable performance and scalability are demonstrated for a typical example problem on a multi-core CPU cluster. AU - Alhaddad, Samer AU - Förstner, Jens AU - Groth, Stefan AU - Grünewald, Daniel AU - Grynko, Yevgen AU - Hannig, Frank AU - Kenter, Tobias AU - Pfreundt, Franz-Josef AU - Plessl, Christian AU - Schotte, Merlind AU - Steinke, Thomas AU - Teich, Jürgen AU - Weiser, Martin AU - Wende, Florian ID - 21587 KW - tet_topic_hpc SN - 0302-9743 T2 - Euro-Par 2020: Parallel Processing Workshops TI - HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids ER - TY - CHAP AU - Nickchen, Tobias AU - Engels, Gregor AU - Lohn, Johannes ID - 18789 SN - 9783030543334 T2 - Industrializing Additive Manufacturing TI - Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain ER - TY - CHAP AB - In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. AU - Agne, Andreas AU - Platzner, Marco AU - Plessl, Christian AU - Happe, Markus AU - Lübbers, Enno ED - Koch, Dirk ED - Hannig, Frank ED - Ziener, Daniel ID - 29 SN - 978-3-319-26406-6 T2 - FPGAs for Software Programmers TI - ReconOS ER - TY - CHAP AB - Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 156 T2 - Self-aware Computing Systems TI - Self-aware Compute Nodes ER - TY - CHAP AB - Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf. AU - Platzner, Marco AU - Plessl, Christian ED - Künsemöller, Jörn ED - Eke, Norber Otto ED - Foit, Lioba ED - Kaerlein, Timo ID - 335 SN - 978-3-7705-5730-1 T2 - Logiken strukturbildender Prozesse: Automatismen TI - Verschiebungen an der Grenze zwischen Hardware und Software ER - TY - BOOK AU - Niehörster, Oliver ID - 1790 SN - 978-3-8440-1735-9 TI - Autonomous Resource Management in Dynamic Data Centers ER - TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER -