[{"year":"2016","citation":{"mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111."},"type":"journal_article","page":"91-111","_id":"165","intvolume":" 55","file":[{"date_created":"2018-03-21T12:45:47Z","file_name":"165-1-s2.0-S0045790616301021-main.pdf","access_level":"closed","file_id":"1544","creator":"florida","file_size":3037854,"success":1,"relation":"main_file","date_updated":"2018-03-21T12:45:47Z","content_type":"application/pdf"}],"author":[{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"Elsevier","quality_controlled":"1","file_date_updated":"2018-03-21T12:45:47Z","publication":"Computers and Electrical Engineering","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:24Z","volume":55,"abstract":[{"lang":"eng","text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes."}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:26:38Z","doi":"10.1016/j.compeleceng.2016.04.021","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"publication_identifier":{"issn":["0045-7906"]},"title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:27:00Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","year":"2016","citation":{"bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917."},"type":"conference","page":"912-917","_id":"168","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:24Z","file":[{"date_created":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf","access_level":"closed","file_id":"1541","creator":"florida","file_size":261356,"success":1,"relation":"main_file","date_updated":"2018-03-21T12:41:55Z","content_type":"application/pdf"}],"publisher":"EDA Consortium / IEEE","quality_controlled":"1","author":[{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"file_date_updated":"2018-03-21T12:41:55Z","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}]},{"language":[{"iso":"eng"}],"citation":{"short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }"},"type":"conference","year":"2016","_id":"171","date_updated":"2023-09-26T13:27:21Z","file":[{"access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","date_created":"2018-03-21T12:39:46Z","content_type":"application/pdf","date_updated":"2018-03-21T12:39:46Z","relation":"main_file","success":1,"file_size":54421,"creator":"florida","file_id":"1538"}],"file_date_updated":"2018-03-21T12:39:46Z","department":[{"_id":"27"},{"_id":"518"}],"publication":"Workshop on Reconfigurable Computing (WRC)","quality_controlled":"1","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"date_created":"2017-10-17T12:41:25Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"status":"public","has_accepted_license":"1","user_id":"15278","title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","ddc":["040"]},{"_id":"1769","date_updated":"2022-01-06T06:53:17Z","intvolume":" 82","issue":"9","doi":"doi:10.1515/teme-2015-0031","type":"journal_article","citation":{"short":"S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450.","ieee":"S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm - Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015.","ama":"Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031","apa":"Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K., … Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm - Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031","chicago":"Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.","mla":"Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50, doi:doi:10.1515/teme-2015-0031.","bibtex":"@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82}, DOI={doi:10.1515/teme-2015-0031}, number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter}, author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer, Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff, Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450} }"},"year":"2015","page":"440-450","abstract":[{"lang":"eng","text":"Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals."}],"user_id":"24135","title":"Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung","publisher":"Walter de Gruyter","author":[{"first_name":"Sebastian","full_name":"Hegler, Sebastian","last_name":"Hegler"},{"full_name":"Statz, Christoph","first_name":"Christoph","last_name":"Statz"},{"first_name":"Marco","full_name":"Mütze, Marco","last_name":"Mütze"},{"first_name":"Hubert","full_name":"Mooshofer, Hubert","last_name":"Mooshofer"},{"last_name":"Goldammer","first_name":"Matthias","full_name":"Goldammer, Matthias"},{"full_name":"Fendt, Karl","first_name":"Karl","last_name":"Fendt"},{"last_name":"Schwarzer","first_name":"Stefan","full_name":"Schwarzer, Stefan"},{"last_name":"Feldhoff","full_name":"Feldhoff, Kim","first_name":"Kim"},{"full_name":"Flehmig, Martin","first_name":"Martin","last_name":"Flehmig"},{"full_name":"Markwardt, Ulf","first_name":"Ulf","last_name":"Markwardt"},{"first_name":"Wolfgang","full_name":"E. Nagel, Wolfgang","last_name":"E. Nagel"},{"first_name":"Maria","full_name":"Schütte, Maria","last_name":"Schütte"},{"full_name":"Walther, Andrea","first_name":"Andrea","last_name":"Walther"},{"first_name":"Michael","full_name":"Meinel, Michael","last_name":"Meinel"},{"last_name":"Basermann","full_name":"Basermann, Achim","first_name":"Achim"},{"last_name":"Plettemeier","full_name":"Plettemeier, Dirk","first_name":"Dirk"}],"publication":"tm - Technisches Messen","department":[{"_id":"27"},{"_id":"104"}],"status":"public","date_created":"2018-03-23T14:01:39Z","volume":82},{"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","language":[{"iso":"eng"}],"user_id":"16153","ddc":["000"],"status":"public","has_accepted_license":"1","date_created":"2018-03-23T14:06:12Z","volume":48,"file":[{"file_id":"5313","creator":"ups","file_size":5605009,"relation":"main_file","success":1,"date_updated":"2018-11-02T15:47:45Z","content_type":"application/pdf","file_name":"07163237.pdf","date_created":"2018-11-02T15:47:45Z","access_level":"closed"}],"publisher":"IEEE Computer Society","author":[{"last_name":"Torresen","first_name":"Jim","full_name":"Torresen, Jim"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Yao","first_name":"Xin","full_name":"Yao, Xin"}],"publication":"IEEE Computer","keyword":["self-awareness","self-expression"],"file_date_updated":"2018-11-02T15:47:45Z","issue":"7","_id":"1772","intvolume":" 48","type":"journal_article","year":"2015","citation":{"short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }"},"page":"18-20"},{"user_id":"24135","title":"Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction","abstract":[{"text":"In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100.","lang":"eng"}],"status":"public","date_created":"2018-03-23T14:14:24Z","publication_identifier":{"issn":["1617-7061"]},"volume":15,"author":[{"last_name":"Peitz","first_name":"Sebastian","full_name":"Peitz, Sebastian"},{"full_name":"Dellnitz, Michael","first_name":"Michael","last_name":"Dellnitz"}],"publisher":"WILEY-VCH Verlag","publication":"PAMM","department":[{"_id":"27"},{"_id":"101"}],"issue":"1","doi":"10.1002/pamm.201510296","_id":"1774","date_updated":"2022-01-06T06:53:19Z","intvolume":" 15","year":"2015","type":"journal_article","citation":{"short":"S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614.","ieee":"S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614, 2015.","chicago":"Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1 (2015): 613–14. https://doi.org/10.1002/pamm.201510296.","apa":"Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614. https://doi.org/10.1002/pamm.201510296","ama":"Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296","mla":"Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no. 1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296.","bibtex":"@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296}, number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian and Dellnitz, Michael}, year={2015}, pages={613–614} }"},"page":"613-614"},{"user_id":"3118","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","place":"Berlin","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"status":"public","date_created":"2019-07-10T09:36:58Z","project":[{"grant_number":"01|H11004","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"publication_identifier":{"isbn":["978-3-8325-4155-2"]},"publisher":"Logos Verlag Berlin GmbH","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"}],"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"date_updated":"2022-01-06T06:50:48Z","_id":"10624","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"year":"2015","type":"dissertation","citation":{"short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }"},"page":"183"},{"title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_updated":"2023-09-26T13:29:08Z","doi":"10.1155/2015/859425","language":[{"iso":"eng"}],"abstract":[{"text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:47:56Z","file_id":"1444","creator":"florida","file_size":2993898,"access_level":"closed","date_created":"2018-03-20T07:47:56Z","file_name":"296-859425.pdf"}],"publication":"International Journal of Reconfigurable Computing (IJRC)","file_date_updated":"2018-03-20T07:47:56Z","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"Hindawi","quality_controlled":"1","date_created":"2017-10-17T12:41:49Z","status":"public","has_accepted_license":"1","volume":2015,"_id":"296","intvolume":" 2015","article_number":"859425","year":"2015","type":"journal_article","citation":{"chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.","ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425."}},{"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","external_id":{"arxiv":["1412.3906"]},"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"oa":"1","date_updated":"2023-09-26T13:29:59Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.","lang":"eng"}],"date_created":"2017-10-17T12:41:51Z","status":"public","has_accepted_license":"1","file":[{"access_level":"open_access","file_name":"303-plessl15_adapt.pdf","date_created":"2018-03-20T07:46:46Z","date_updated":"2019-08-01T09:10:44Z","content_type":"application/pdf","relation":"main_file","file_size":1176620,"file_id":"1442","creator":"florida"}],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","file_date_updated":"2019-08-01T09:10:44Z","quality_controlled":"1","author":[{"first_name":"Marvin","full_name":"Damschen, Marvin","last_name":"Damschen"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"_id":"303","citation":{"mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015."},"year":"2015","type":"conference"},{"year":"2015","type":"conference","citation":{"chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824."},"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:31:01Z","_id":"1773","doi":"10.1145/2675743.2771824","author":[{"last_name":"Schumacher","first_name":"Jörn","full_name":"Schumacher, Jörn"},{"last_name":"T. Anderson","full_name":"T. Anderson, J.","first_name":"J."},{"first_name":"A.","full_name":"Borga, A.","last_name":"Borga"},{"last_name":"Boterenbrood","full_name":"Boterenbrood, H.","first_name":"H."},{"first_name":"H.","full_name":"Chen, H.","last_name":"Chen"},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"first_name":"G.","full_name":"Drake, G.","last_name":"Drake"},{"first_name":"D.","full_name":"Francis, D.","last_name":"Francis"},{"first_name":"B.","full_name":"Gorini, B.","last_name":"Gorini"},{"last_name":"Lanni","first_name":"F.","full_name":"Lanni, F."},{"last_name":"Lehmann-Miotto","first_name":"Giovanna","full_name":"Lehmann-Miotto, Giovanna"},{"first_name":"L.","full_name":"Levinson, L.","last_name":"Levinson"},{"last_name":"Narevicius","first_name":"J.","full_name":"Narevicius, J."},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Roich","full_name":"Roich, A.","first_name":"A."},{"full_name":"Ryu, S.","first_name":"S.","last_name":"Ryu"},{"full_name":"P. Schreuder, F.","first_name":"F.","last_name":"P. Schreuder"},{"last_name":"Vandelli","first_name":"Wainer","full_name":"Vandelli, Wainer"},{"first_name":"J.","full_name":"Vermeulen, J.","last_name":"Vermeulen"},{"last_name":"Zhang","full_name":"Zhang, J.","first_name":"J."}],"publisher":"ACM","quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","status":"public","date_created":"2018-03-23T14:09:33Z","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","user_id":"15278"},{"user_id":"15278","title":"Aktuelles Schlagwort: Approximate Computing","date_created":"2018-03-23T13:58:34Z","status":"public","publication":"Informatik Spektrum","department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"keyword":["approximate computing","survey"],"publisher":"Springer","quality_controlled":"1","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Schreier","full_name":"Schreier, Peter J.","first_name":"Peter J."}],"issue":"5","doi":"10.1007/s00287-015-0911-z","_id":"1768","date_updated":"2023-09-26T13:30:22Z","language":[{"iso":"eng"}],"page":"396-399","citation":{"mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","apa":"Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.","ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399."},"year":"2015","type":"journal_article"},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:38Z","quality_controlled":"1","author":[{"first_name":"Marvin","full_name":"Damschen, Marvin","last_name":"Damschen"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"EDA Consortium / IEEE","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","file_date_updated":"2018-03-21T10:29:49Z","file":[{"file_size":380552,"file_id":"1500","creator":"florida","date_updated":"2018-03-21T10:29:49Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"238-plessl15_date.pdf","date_created":"2018-03-21T10:29:49Z","access_level":"closed"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"citation":{"bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083."},"year":"2015","type":"conference","page":"1078-1083","_id":"238","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","language":[{"iso":"eng"}],"doi":"10.7873/DATE.2015.1124","date_updated":"2023-09-26T13:31:44Z"},{"volume":664,"date_created":"2018-03-23T14:19:27Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"publication":"Journal of Physics: Conference Series","author":[{"last_name":"Anderson","first_name":"J","full_name":"Anderson, J"},{"full_name":"Borga, A","first_name":"A","last_name":"Borga"},{"last_name":"Boterenbrood","full_name":"Boterenbrood, H","first_name":"H"},{"last_name":"Chen","full_name":"Chen, H","first_name":"H"},{"last_name":"Chen","full_name":"Chen, K","first_name":"K"},{"last_name":"Drake","full_name":"Drake, G","first_name":"G"},{"full_name":"Francis, D","first_name":"D","last_name":"Francis"},{"last_name":"Gorini","first_name":"B","full_name":"Gorini, B"},{"first_name":"F","full_name":"Lanni, F","last_name":"Lanni"},{"last_name":"Lehmann Miotto","first_name":"G","full_name":"Lehmann Miotto, G"},{"first_name":"L","full_name":"Levinson, L","last_name":"Levinson"},{"full_name":"Narevicius, J","first_name":"J","last_name":"Narevicius"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Roich","first_name":"A","full_name":"Roich, A"},{"last_name":"Ryu","first_name":"S","full_name":"Ryu, S"},{"last_name":"Schreuder","full_name":"Schreuder, F","first_name":"F"},{"first_name":"Jörn","full_name":"Schumacher, Jörn","last_name":"Schumacher"},{"first_name":"Wainer","full_name":"Vandelli, Wainer","last_name":"Vandelli"},{"last_name":"Vermeulen","full_name":"Vermeulen, J","first_name":"J"},{"last_name":"Zhang","first_name":"J","full_name":"Zhang, J"}],"quality_controlled":"1","publisher":"IOP Publishing","title":"FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades","user_id":"15278","abstract":[{"text":"The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.","lang":"eng"}],"year":"2015","type":"journal_article","citation":{"chicago":"Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series 664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.","apa":"Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050","ama":"Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050","mla":"Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.","bibtex":"@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }","short":"J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015).","ieee":"J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050."},"language":[{"iso":"eng"}],"doi":"10.1088/1742-6596/664/8/082050","article_number":"082050","_id":"1775","intvolume":" 664","date_updated":"2023-09-26T13:31:23Z"},{"abstract":[{"text":"In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment.","lang":"eng"}],"title":"Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres","user_id":"24135","publisher":"Springer International Publishing","author":[{"last_name":"Steinle","first_name":"Tobias","full_name":"Steinle, Tobias"},{"full_name":"Vrabec, Jadran","first_name":"Jadran","last_name":"Vrabec"},{"last_name":"Walther","first_name":"Andrea","full_name":"Walther, Andrea"}],"department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"publication":"Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)","editor":[{"last_name":"Bock","first_name":"Hans Georg","full_name":"Bock, Hans Georg"},{"last_name":"Hoang","full_name":"Hoang, Xuan Phu","first_name":"Xuan Phu"},{"last_name":"Rannacher","full_name":"Rannacher, Rolf","first_name":"Rolf"},{"last_name":"Schlöder","full_name":"Schlöder, Johannes P.","first_name":"Johannes P."}],"publication_identifier":{"isbn":["978-3-319-09063-4"]},"status":"public","date_created":"2018-03-26T13:47:16Z","date_updated":"2022-01-06T06:53:20Z","_id":"1781","doi":"10.1007/978-3-319-09063-4_19","citation":{"chicago":"Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.","apa":"Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19","ama":"Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19","bibtex":"@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }","mla":"Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.","short":"T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.","ieee":"T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243."},"year":"2014","type":"conference","page":"233-243"},{"series_title":"Lecture Notes in Computer Science","year":"2014","citation":{"chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25."},"type":"conference","page":"14-25","date_updated":"2022-01-06T06:53:20Z","_id":"1782","doi":"10.1007/978-3-319-09165-5_2","issue":"8427","publisher":"Springer","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Conf. on Computers and Games (CG)","status":"public","date_created":"2018-03-26T13:50:37Z","place":"Switzerland","title":"On Semeai Detection in Monte-Carlo Go","user_id":"24135"},{"abstract":[{"lang":"eng","text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf."}],"user_id":"15278","ddc":["040"],"file":[{"access_level":"closed","date_created":"2018-03-20T07:29:58Z","file_name":"335-2014_plessl_automatismen.pdf","date_updated":"2018-03-20T07:29:58Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":2848154,"creator":"florida","file_id":"1424"}],"publisher":"Wilhelm Fink","quality_controlled":"1","author":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"file_date_updated":"2018-03-20T07:29:58Z","publication":"Logiken strukturbildender Prozesse: Automatismen","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:57Z","_id":"335","year":"2014","type":"book_chapter","citation":{"apa":"Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Wilhelm Fink.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144."},"page":"123-144","place":"Paderborn","title":"Verschiebungen an der Grenze zwischen Hardware und Software","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"editor":[{"full_name":"Künsemöller, Jörn","first_name":"Jörn","last_name":"Künsemöller"},{"last_name":"Eke","full_name":"Eke, Norber Otto","first_name":"Norber Otto"},{"last_name":"Foit","full_name":"Foit, Lioba","first_name":"Lioba"},{"last_name":"Kaerlein","full_name":"Kaerlein, Timo","first_name":"Timo"}],"publication_identifier":{"isbn":["978-3-7705-5730-1"]},"publication_status":"published","date_updated":"2023-09-26T13:32:49Z","series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","language":[{"iso":"ger"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","file":[{"file_id":"1387","creator":"florida","file_size":330193,"relation":"main_file","success":1,"date_updated":"2018-03-20T07:02:02Z","content_type":"application/pdf","file_name":"388-plessl14_arc.pdf","date_created":"2018-03-20T07:02:02Z","access_level":"closed"}],"author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"Springer International Publishing","quality_controlled":"1","file_date_updated":"2018-03-20T07:02:02Z","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:07Z","volume":8405,"abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"user_id":"15278","ddc":["040"],"type":"conference","citation":{"ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13."},"year":"2014","page":"144-155","_id":"388","intvolume":" 8405"},{"abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.","lang":"eng"}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-20T07:20:31Z","publication":"Microprocessors and Microsystems","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"Elsevier","quality_controlled":"1","file":[{"access_level":"closed","file_name":"363-plessl13_micpro.pdf","date_created":"2018-03-20T07:20:31Z","date_updated":"2018-03-20T07:20:31Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":1499996,"file_id":"1408","creator":"florida"}],"volume":38,"date_created":"2017-10-17T12:42:02Z","has_accepted_license":"1","status":"public","_id":"363","intvolume":" 38","issue":"8, Part B","page":"911-919","type":"journal_article","year":"2014","citation":{"ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001."},"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_updated":"2023-09-26T13:33:06Z","doi":"10.1016/j.micpro.2013.12.001","language":[{"iso":"eng"}]},{"_id":"377","page":"222-229","type":"conference","year":"2014","citation":{"ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67."},"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"date_created":"2017-10-17T12:42:05Z","has_accepted_license":"1","status":"public","file_date_updated":"2018-03-20T07:14:20Z","keyword":["coldboot"],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","author":[{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"publisher":"IEEE","quality_controlled":"1","file":[{"file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z","access_level":"closed","file_id":"1397","creator":"florida","file_size":1003907,"success":1,"relation":"main_file","date_updated":"2018-03-20T07:14:20Z","content_type":"application/pdf"}],"doi":"10.1109/FCCM.2014.67","date_updated":"2023-09-26T13:33:50Z","language":[{"iso":"eng"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"abstract":[{"lang":"eng","text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems."}],"user_id":"15278","ddc":["040"],"file":[{"success":1,"relation":"main_file","date_updated":"2018-03-20T07:19:19Z","content_type":"application/pdf","creator":"florida","file_id":"1406","file_size":916052,"access_level":"closed","date_created":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","file_date_updated":"2018-03-20T07:19:19Z","publisher":"ACM","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:03Z","status":"public","has_accepted_license":"1","volume":7,"intvolume":" 7","_id":"365","issue":"2","article_number":"13","type":"journal_article","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596."},"year":"2014","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"date_updated":"2023-09-26T13:33:31Z","doi":"10.1145/2617596","language":[{"iso":"eng"}]},{"file":[{"file_id":"1426","creator":"florida","file_size":1877185,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:31:40Z","file_name":"328-plessl14_micro_01.pdf","date_created":"2018-03-20T07:31:40Z","access_level":"closed"}],"file_date_updated":"2018-03-20T07:31:40Z","publication":"IEEE Micro","quality_controlled":"1","publisher":"IEEE","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"first_name":"Bernhard","full_name":"Plattner, Bernhard","last_name":"Plattner"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_created":"2017-10-17T12:41:55Z","status":"public","has_accepted_license":"1","volume":34,"abstract":[{"text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications","lang":"eng"}],"user_id":"15278","ddc":["040"],"page":"60-71","citation":{"chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110."},"year":"2014","type":"journal_article","intvolume":" 34","_id":"328","issue":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:32:31Z","doi":"10.1109/MM.2013.110"},{"citation":{"mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149."},"year":"2014","type":"conference","page":"142-149","language":[{"iso":"eng"}],"doi":"10.1109/ISPA.2014.27","date_updated":"2023-09-26T13:35:40Z","_id":"1778","status":"public","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"date_created":"2018-03-26T13:40:14Z","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"C. Durelli","full_name":"C. Durelli, Gianluca","first_name":"Gianluca"},{"last_name":"Pogliani","full_name":"Pogliani, Marcello","first_name":"Marcello"},{"last_name":"Miele","full_name":"Miele, Antonio","first_name":"Antonio"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"D. Santambrogio, Marco","first_name":"Marco","last_name":"D. Santambrogio"},{"last_name":"Bolchini","full_name":"Bolchini, Cristiana","first_name":"Cristiana"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","user_id":"15278"},{"title":"Deferring Accelerator Offloading Decisions to Application Runtime","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2014.7032509","date_updated":"2023-09-26T13:37:02Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:17Z","file":[{"file_id":"1353","creator":"florida","file_size":557362,"success":1,"relation":"main_file","date_updated":"2018-03-16T11:29:52Z","content_type":"application/pdf","file_name":"439-plessl14a_reconfig.pdf","date_created":"2018-03-16T11:29:52Z","access_level":"closed"}],"publisher":"IEEE","author":[{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:29:52Z","_id":"439","citation":{"chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509."},"year":"2014","type":"conference","page":"1-8"},{"date_updated":"2023-09-26T13:36:40Z","doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"406","year":"2014","citation":{"ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535"},"type":"conference","page":"1-8","abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"user_id":"15278","ddc":["040"],"file":[{"file_size":932852,"file_id":"1366","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-16T11:37:42Z","success":1,"relation":"main_file","file_name":"406-ReConFig14.pdf","date_created":"2018-03-16T11:37:42Z","access_level":"closed"}],"author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","quality_controlled":"1","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:37:42Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:11Z"},{"title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","quality_controlled":"1","publisher":"Springer","author":[{"last_name":"C. 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USENIX Conference on File and Storage Technologies (FAST)","author":[{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"full_name":"Süß, Tim","first_name":"Tim","last_name":"Süß"}],"publisher":"USENIX Association","user_id":"24135","title":"File Recipe Compression in Data Deduplication Systems","page":"175-182","citation":{"mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82.","bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.","apa":"Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association.","chicago":"Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013.","ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182.","short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182."},"year":"2013","type":"conference","_id":"1793","date_updated":"2022-01-06T06:53:23Z"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:35Z","doi":"10.1109/FPT.2013.6718394","file_date_updated":"2018-03-15T10:36:08Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","keyword":["coldboot"],"author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE","file":[{"file_name":"528-plessl13_fpt.pdf","date_created":"2018-03-15T10:36:08Z","access_level":"closed","file_size":822680,"creator":"florida","file_id":"1294","content_type":"application/pdf","date_updated":"2018-03-15T10:36:08Z","success":1,"relation":"main_file"}],"date_created":"2017-10-17T12:42:35Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"ddc":["040"],"user_id":"15278","page":"386-389","citation":{"short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394."},"type":"conference","year":"2013","_id":"528"},{"ddc":["040"],"user_id":"15278","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:30Z","publisher":"IEEE","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Meyer auf der Heide","id":"15523","first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm"}],"quality_controlled":"1","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","file":[{"file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z","access_level":"closed","file_id":"1308","creator":"florida","file_size":1040834,"success":1,"relation":"main_file","date_updated":"2018-03-15T13:38:56Z","content_type":"application/pdf"}],"_id":"505","citation":{"mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013."},"year":"2013","type":"conference","title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ISORC.2013.6913232","date_updated":"2023-09-26T13:38:20Z","language":[{"iso":"eng"}]},{"doi":"10.1109/IPDPSW.2013.136","date_updated":"2023-09-26T13:38:05Z","_id":"1787","citation":{"bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73."},"year":"2013","type":"conference","page":"64-73","language":[{"iso":"eng"}],"title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","user_id":"15278","place":"Washington, DC, USA","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"status":"public","date_created":"2018-03-26T14:51:05Z","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Suess","full_name":"Suess, Tim","first_name":"Tim"},{"last_name":"Schoenrock","full_name":"Schoenrock, Andrew","first_name":"Andrew"},{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)"},{"abstract":[{"text":"Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations.","lang":"eng"}],"user_id":"15274","title":"Cost-aware and SLO Fulfilling Software as a Service","publication":"Journal of Grid Computing","department":[{"_id":"27"}],"author":[{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"id":"15273","last_name":"Simon","full_name":"Simon, Jens","first_name":"Jens"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"}],"date_created":"2018-03-29T11:16:18Z","status":"public","volume":10,"publication_status":"published","date_updated":"2022-01-06T06:54:09Z","_id":"1965","intvolume":" 10","issue":"3","doi":"10.1007/s10723-012-9230-7","language":[{"iso":"eng"}],"page":"553-577","year":"2012","citation":{"ieee":"O. Niehörster, J. Simon, A. Brinkmann, A. Keller, and J. Krüger, “Cost-aware and SLO Fulfilling Software as a Service,” Journal of Grid Computing, vol. 10, no. 3, pp. 553–577, 2012.","short":"O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid Computing 10 (2012) 553–577.","bibtex":"@article{Niehörster_Simon_Brinkmann_Keller_Krüger_2012, title={Cost-aware and SLO Fulfilling Software as a Service}, volume={10}, DOI={10.1007/s10723-012-9230-7}, number={3}, journal={Journal of Grid Computing}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Keller, Axel and Krüger, Jens}, year={2012}, pages={553–577} }","mla":"Niehörster, Oliver, et al. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing, vol. 10, no. 3, 2012, pp. 553–77, doi:10.1007/s10723-012-9230-7.","chicago":"Niehörster, Oliver, Jens Simon, André Brinkmann, Axel Keller, and Jens Krüger. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing 10, no. 3 (2012): 553–77. https://doi.org/10.1007/s10723-012-9230-7.","ama":"Niehörster O, Simon J, Brinkmann A, Keller A, Krüger J. Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing. 2012;10(3):553-577. doi:10.1007/s10723-012-9230-7","apa":"Niehörster, O., Simon, J., Brinkmann, A., Keller, A., & Krüger, J. (2012). Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing, 10(3), 553–577. https://doi.org/10.1007/s10723-012-9230-7"},"type":"journal_article"},{"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","department":[{"_id":"27"},{"_id":"78"}],"publisher":"IEEE Computer Society","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"last_name":"Redif","full_name":"Redif, Soydan","first_name":"Soydan"}],"date_created":"2018-03-29T14:34:48Z","status":"public","user_id":"24135","title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","page":"135-140","year":"2012","type":"conference","citation":{"mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125.","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140.","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140."},"_id":"2097","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/FPT.2012.6412125"},{"doi":"10.1109/ICPADS.2012.34","_id":"2098","date_updated":"2022-01-06T06:54:42Z","citation":{"ieee":"J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.","short":"J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.","bibtex":"@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }","mla":"Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34.","chicago":"Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.","apa":"Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34","ama":"Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34"},"year":"2012","type":"conference","page":"181-188","title":"ESB: Ext2 Split Block Device","user_id":"24135","status":"public","date_created":"2018-03-29T14:40:04Z","publisher":"IEEE","author":[{"full_name":"Kaiser, Jürgen","first_name":"Jürgen","last_name":"Kaiser"},{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Hartung","first_name":"Tim","full_name":"Hartung, Tim"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","department":[{"_id":"27"}]},{"user_id":"24135","title":"A Study on Data Deduplication in HPC Storage Systems","place":"Los Alamitos, CA, USA","date_created":"2018-03-29T14:41:55Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Supercomputing (SC)","author":[{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"last_name":"Kaiser","first_name":"Jürgen","full_name":"Kaiser, Jürgen"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"full_name":"Kuhn, Michael","first_name":"Michael","last_name":"Kuhn"},{"last_name":"Kunkel","first_name":"Julian","full_name":"Kunkel, Julian"},{"full_name":"Cortes, Toni","first_name":"Toni","last_name":"Cortes"}],"publisher":"IEEE Computer Society","doi":"10.1109/SC.2012.14","_id":"2099","date_updated":"2022-01-06T06:54:42Z","page":"7:1-7:11","year":"2012","citation":{"chicago":"Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14.","apa":"Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14","ama":"Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14","mla":"Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14.","bibtex":"@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }","short":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11.","ieee":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. 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A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050).","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","mla":"Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012.","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.","ieee":"S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050."},"type":"conference"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","has_accepted_license":"1","status":"public","date_created":"2018-03-29T15:04:25Z","file":[{"access_level":"closed","date_created":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-02-13T09:04:46Z","creator":"fossie","file_id":"7638","file_size":2148787}],"publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Meyer, Björn","first_name":"Björn","last_name":"Meyer"},{"first_name":"Jörn","full_name":"Schumacher, Jörn","last_name":"Schumacher"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens","id":"158","last_name":"Förstner"}],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"file_date_updated":"2019-02-13T09:04:46Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","user_id":"15278","ddc":["000"],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"year":"2012","type":"conference","citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370."},"page":"189-196","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"}},{"page":"110-126","type":"journal_article","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002"},"year":"2012","_id":"2108","intvolume":" 36","issue":"2","publication":"Microprocessors and Microsystems","keyword":["funding-altera"],"author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"quality_controlled":"1","volume":36,"date_created":"2018-03-29T15:12:38Z","status":"public","user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:39:30Z","doi":"10.1016/j.micpro.2011.04.002","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"issn":["0141-9331"]},"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators"},{"page":"1-8","year":"2012","citation":{"ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745"},"type":"conference","_id":"615","date_created":"2017-10-17T12:42:51Z","status":"public","has_accepted_license":"1","file":[{"date_updated":"2018-03-15T06:48:32Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":730144,"creator":"florida","file_id":"1246","access_level":"closed","file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z"}],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","quality_controlled":"1","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators"},{"_id":"591","year":"2012","citation":{"short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773."},"type":"conference","page":"1-8","abstract":[{"lang":"eng","text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort."}],"user_id":"15278","ddc":["040"],"file":[{"date_created":"2018-03-15T08:33:18Z","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed","file_size":371235,"creator":"florida","file_id":"1257","content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","relation":"main_file","success":1}],"author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"}],"quality_controlled":"1","publisher":"IEEE","file_date_updated":"2018-03-15T08:33:18Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:47Z","date_updated":"2023-09-26T13:41:08Z","doi":"10.1109/ReConFig.2012.6416773","language":[{"iso":"eng"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}]},{"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"date_created":"2017-10-17T12:42:50Z","status":"public","has_accepted_license":"1","file":[{"date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed","file_id":"1249","creator":"florida","file_size":146789,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T08:14:17Z"}],"publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file_date_updated":"2018-03-15T08:14:17Z","quality_controlled":"1","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"_id":"609","page":"8-9","citation":{"mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9."},"year":"2012","type":"conference","title":"Hardware/Software Platform for Self-aware Compute Nodes","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_updated":"2023-09-26T13:41:36Z","language":[{"iso":"eng"}]},{"citation":{"mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565."},"year":"2012","type":"conference","page":"559-565","_id":"567","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:42Z","publisher":"IEEE","author":[{"last_name":"Barrio","full_name":"Barrio, Pablo","first_name":"Pablo"},{"full_name":"Carreras, Carlos","first_name":"Carlos","last_name":"Carreras"},{"last_name":"Sierra","full_name":"Sierra, Roberto","first_name":"Roberto"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T10:20:24Z","success":1,"relation":"main_file","file_size":288508,"creator":"florida","file_id":"1275","access_level":"closed","date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/HPCSim.2012.6266973","date_updated":"2023-09-26T13:42:54Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures"},{"type":"conference","year":"2012","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370."},"page":"559-562","_id":"612","file":[{"access_level":"closed","date_created":"2018-03-15T06:49:03Z","file_name":"612-ruething_fpl12.pdf","date_updated":"2018-03-15T06:49:03Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":202923,"creator":"florida","file_id":"1247"}],"publisher":"IEEE","author":[{"full_name":"Rüthing, Christoph","first_name":"Christoph","last_name":"Rüthing"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","file_date_updated":"2018-03-15T06:49:03Z","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs"},{"author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"quality_controlled":"1","keyword":["funding-enhance"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","status":"public","date_created":"2018-04-03T09:18:33Z","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","user_id":"15278","type":"conference","year":"2012","citation":{"ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012."},"language":[{"iso":"eng"}],"_id":"2180","date_updated":"2023-09-26T13:40:17Z"},{"citation":{"bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315.","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315","apa":"Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012)."},"type":"journal_article","year":"2012","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:39:48Z","_id":"2177","doi":"10.1155/2012/418315","publisher":"Hindawi Publishing Corp.","quality_controlled":"1","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publication":"Int. Journal of Reconfigurable Computing (IJRC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-03T09:13:22Z","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","user_id":"15278"},{"year":"2011","citation":{"apa":"Kleineweber, C., Keller, A., Niehörster, O., & Brinkmann, A. (2011). Rule Based Mapping of Virtual Machines in Clouds. In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). https://doi.org/10.1109/PDP.2011.69","ama":"Kleineweber C, Keller A, Niehörster O, Brinkmann A. Rule Based Mapping of Virtual Machines in Clouds. In: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). ; 2011. doi:10.1109/PDP.2011.69","chicago":"Kleineweber, Christoph, Axel Keller, Oliver Niehörster, and André Brinkmann. “Rule Based Mapping of Virtual Machines in Clouds.” In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. https://doi.org/10.1109/PDP.2011.69.","bibtex":"@inproceedings{Kleineweber_Keller_Niehörster_Brinkmann_2011, title={Rule Based Mapping of Virtual Machines in Clouds}, DOI={10.1109/PDP.2011.69}, booktitle={Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)}, author={Kleineweber, Christoph and Keller, Axel and Niehörster, Oliver and Brinkmann, André}, year={2011} }","mla":"Kleineweber, Christoph, et al. “Rule Based Mapping of Virtual Machines in Clouds.” Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011, doi:10.1109/PDP.2011.69.","short":"C. Kleineweber, A. Keller, O. Niehörster, A. Brinkmann, in: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011.","ieee":"C. Kleineweber, A. Keller, O. Niehörster, and A. Brinkmann, “Rule Based Mapping of Virtual Machines in Clouds,” in Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011."},"type":"conference","language":[{"iso":"eng"}],"doi":"10.1109/PDP.2011.69","_id":"1968","date_updated":"2022-01-06T06:54:10Z","publication_status":"published","date_created":"2018-03-29T11:21:05Z","status":"public","publication":"Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)","department":[{"_id":"27"}],"author":[{"last_name":"Kleineweber","full_name":"Kleineweber, Christoph","first_name":"Christoph"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"last_name":"Niehörster","full_name":"Niehörster, Oliver","first_name":"Oliver"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"title":"Rule Based Mapping of Virtual Machines in Clouds","user_id":"15274","abstract":[{"lang":"eng","text":"Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments."}]},{"status":"public","date_created":"2018-03-29T11:22:26Z","publication_status":"published","publisher":"John Wiley & Sons","author":[{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"first_name":"Jürgen","full_name":"Kaiser, Jürgen","last_name":"Kaiser"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"first_name":"Matthias","full_name":"Keller, Matthias","last_name":"Keller"},{"last_name":"Kleineweber","full_name":"Kleineweber, Christoph","first_name":"Christoph"},{"last_name":"Konersmann","first_name":"Christoph","full_name":"Konersmann, Christoph"},{"full_name":"Niehörster, Oliver","first_name":"Oliver","last_name":"Niehörster"},{"last_name":"Schäfer","first_name":"Thorsten","full_name":"Schäfer, Thorsten"},{"full_name":"Simon, Jens","first_name":"Jens","id":"15273","last_name":"Simon"},{"full_name":"Wilhelm, Maximilan","first_name":"Maximilan","last_name":"Wilhelm"}],"department":[{"_id":"27"}],"publication":"Software: Practice and Experience","user_id":"15274","title":"Virtualized HPC: a contradiction in terms?","abstract":[{"text":"System virtualization has become the enabling technology to manage the increasing number of different applications inside data centers. The abstraction from the underlying hardware and the provision of multiple virtual machines (VM) on a single physical server have led to a consolidation and more efficient usage of physical servers. The abstraction from the hardware also eases the provision of applications on different data centers, as applied in several cloud computing environments. In this case, the application need not adapt to the environment of the cloud computing provider, but can travel around with its own VM image, including its own operating system and libraries. System virtualization and cloud computing could also be very attractive in the context of high‐performance computing (HPC). Today, HPC centers have to cope with both, the management of the infrastructure and also the applications. Virtualization technology would enable these centers to focus on the infrastructure, while the users, collaborating inside their virtual organizations (VOs), would be able to provide the software. Nevertheless, there seems to be a contradiction between HPC and cloud computing, as there are very few successful approaches to virtualize HPC centers. This work discusses the underlying reasons, including the management and performance, and presents solutions to overcome the contradiction, including a set of new libraries. The viability of the presented approach is shown based on evaluating a selected parallel, scientific application in a virtualized HPC environment. ","lang":"eng"}],"language":[{"iso":"eng"}],"type":"journal_article","citation":{"short":"G. Birkenheuer, A. Brinkmann, J. Kaiser, A. Keller, M. Keller, C. Kleineweber, C. Konersmann, O. Niehörster, T. Schäfer, J. Simon, M. Wilhelm, Software: Practice and Experience (2011).","ieee":"G. Birkenheuer et al., “Virtualized HPC: a contradiction in terms?,” Software: Practice and Experience, 2011.","ama":"Birkenheuer G, Brinkmann A, Kaiser J, et al. Virtualized HPC: a contradiction in terms? Software: Practice and Experience. 2011. doi:10.1002/spe.1055","apa":"Birkenheuer, G., Brinkmann, A., Kaiser, J., Keller, A., Keller, M., Kleineweber, C., … Wilhelm, M. (2011). Virtualized HPC: a contradiction in terms? Software: Practice and Experience. https://doi.org/10.1002/spe.1055","chicago":"Birkenheuer, Georg, André Brinkmann, Jürgen Kaiser, Axel Keller, Matthias Keller, Christoph Kleineweber, Christoph Konersmann, et al. “Virtualized HPC: A Contradiction in Terms?” Software: Practice and Experience, 2011. https://doi.org/10.1002/spe.1055.","mla":"Birkenheuer, Georg, et al. “Virtualized HPC: A Contradiction in Terms?” Software: Practice and Experience, John Wiley & Sons, 2011, doi:10.1002/spe.1055.","bibtex":"@article{Birkenheuer_Brinkmann_Kaiser_Keller_Keller_Kleineweber_Konersmann_Niehörster_Schäfer_Simon_et al._2011, title={Virtualized HPC: a contradiction in terms?}, DOI={10.1002/spe.1055}, journal={Software: Practice and Experience}, publisher={John Wiley & Sons}, author={Birkenheuer, Georg and Brinkmann, André and Kaiser, Jürgen and Keller, Axel and Keller, Matthias and Kleineweber, Christoph and Konersmann, Christoph and Niehörster, Oliver and Schäfer, Thorsten and Simon, Jens and et al.}, year={2011} }"},"year":"2011","doi":"10.1002/spe.1055","_id":"1971","date_updated":"2022-01-06T06:54:10Z"},{"citation":{"mla":"Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52.","bibtex":"@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware SaaS Stack}, DOI={10.1109/MASCOTS.2011.52}, booktitle={Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, author={Niehörster, Oliver and Keller, Axel and Brinkmann, André}, year={2011} }","chicago":"Niehörster, Oliver, Axel Keller, and André Brinkmann. “An Energy-Aware SaaS Stack.” In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011. https://doi.org/10.1109/MASCOTS.2011.52.","ama":"Niehörster O, Keller A, Brinkmann A. An Energy-Aware SaaS Stack. In: Proc. Int. Meeting of the IEEE Int. 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Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011."},"type":"conference","year":"2011","language":[{"iso":"eng"}],"_id":"1972","date_updated":"2022-01-06T06:54:10Z","doi":"10.1109/MASCOTS.2011.52","author":[{"last_name":"Niehörster","first_name":"Oliver","full_name":"Niehörster, Oliver"},{"last_name":"Keller","id":"15274","first_name":"Axel","full_name":"Keller, Axel"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"publication":"Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)","department":[{"_id":"27"}],"publication_status":"published","status":"public","date_created":"2018-03-29T11:23:22Z","abstract":[{"text":"We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds.","lang":"eng"}],"title":"An Energy-Aware SaaS Stack","user_id":"15274"},{"place":"Washington, DC","title":"Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems","user_id":"24135","publication":"Proc. Int. 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Effert, Y. Kang, E. Miller, A. Brinkmann, T. Cortes, in: Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, Washington, DC, 2011, pp. 1–10.","mla":"Miranda, Alberto, et al. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1–10, doi:10.1109/HiPC.2011.6152745.","bibtex":"@inproceedings{Miranda_Effert_Kang_Miller_Brinkmann_Cortes_2011, place={Washington, DC}, title={Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems}, DOI={10.1109/HiPC.2011.6152745}, booktitle={Proc. Int. Conf. on High Performance Computing (HIPC)}, publisher={IEEE Computer Society}, author={Miranda, Alberto and Effert, Sascha and Kang, Yangwook and Miller, Ethan and Brinkmann, André and Cortes, Toni}, year={2011}, pages={1–10} }","ama":"Miranda A, Effert S, Kang Y, Miller E, Brinkmann A, Cortes T. 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Washington, DC: IEEE Computer Society, 2011. https://doi.org/10.1109/HiPC.2011.6152745."},"type":"conference","year":"2011"},{"user_id":"24135","title":"Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System","status":"public","date_created":"2018-04-03T14:32:23Z","publisher":"IEEE","author":[{"full_name":"Grawinkel, Matthias","first_name":"Matthias","last_name":"Grawinkel"},{"last_name":"Pargmann","first_name":"Markus","full_name":"Pargmann, Markus"},{"last_name":"Dömer","first_name":"Hubert","full_name":"Dömer, Hubert"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","doi":"10.1109/ICPADS.2011.77","_id":"2189","date_updated":"2022-01-06T06:55:18Z","citation":{"short":"M. Grawinkel, M. Pargmann, H. Dömer, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–387.","ieee":"M. Grawinkel, M. Pargmann, H. Dömer, and A. Brinkmann, “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2011, pp. 380–387.","apa":"Grawinkel, M., Pargmann, M., Dömer, H., & Brinkmann, A. (2011). Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 380–387). IEEE. https://doi.org/10.1109/ICPADS.2011.77","ama":"Grawinkel M, Pargmann M, Dömer H, Brinkmann A. Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2011:380-387. doi:10.1109/ICPADS.2011.77","chicago":"Grawinkel, Matthias, Markus Pargmann, Hubert Dömer, and André Brinkmann. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 380–87. IEEE, 2011. https://doi.org/10.1109/ICPADS.2011.77.","bibtex":"@inproceedings{Grawinkel_Pargmann_Dömer_Brinkmann_2011, title={Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System}, DOI={10.1109/ICPADS.2011.77}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Grawinkel, Matthias and Pargmann, Markus and Dömer, Hubert and Brinkmann, André}, year={2011}, pages={380–387} }","mla":"Grawinkel, Matthias, et al. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–87, doi:10.1109/ICPADS.2011.77."},"year":"2011","type":"conference","page":"380-387"},{"publisher":"IEEE Computer Society","author":[{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"department":[{"_id":"27"}],"publication":"Proc. IEEE Int. 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Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28.","bibtex":"@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28}, booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André}, year={2011}, pages={138–145} }","chicago":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 138–45. Washington DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28.","ama":"Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed Configuration Effects. In: Proc. IEEE Int. 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Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/CloudCom.2011.28"},"type":"conference","page":"138-145","date_updated":"2022-01-06T06:55:19Z","_id":"2190","doi":"10.1109/CloudCom.2011.28"},{"publication":"Intel European Research and Innovation Conference","keyword":["funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Kauschke, Michael","first_name":"Michael","last_name":"Kauschke"}],"date_created":"2018-04-03T14:34:57Z","status":"public","user_id":"24135","title":"Estimation and Partitioning for CPU-Accelerator Architectures","type":"conference","year":"2011","citation":{"ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011.","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.","apa":"Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference."},"date_updated":"2022-01-06T06:55:19Z","_id":"2191"},{"volume":9,"date_created":"2018-04-03T14:36:06Z","status":"public","publication":"Journal of Grid Computing","department":[{"_id":"27"}],"publisher":"Springer","author":[{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Högqvist","first_name":"Mikael","full_name":"Högqvist, Mikael"},{"last_name":"Papaspyrou","first_name":"Alexander","full_name":"Papaspyrou, Alexander"},{"full_name":"Schott, Bernhard","first_name":"Bernhard","last_name":"Schott"},{"first_name":"Dietmar","full_name":"Sommerfeld, Dietmar","last_name":"Sommerfeld"},{"last_name":"Ziegler","first_name":"Wolfgang","full_name":"Ziegler, Wolfgang"}],"title":"Infrastructure Federation Through Virtualized Delegation of Resources and Services","user_id":"24135","page":"355-377","type":"journal_article","citation":{"short":"G. Birkenheuer, A. Brinkmann, M. Högqvist, A. Papaspyrou, B. Schott, D. Sommerfeld, W. Ziegler, Journal of Grid Computing 9 (2011) 355–377.","ieee":"G. Birkenheuer et al., “Infrastructure Federation Through Virtualized Delegation of Resources and Services,” Journal of Grid Computing, vol. 9, no. 3, pp. 355–377, 2011.","chicago":"Birkenheuer, Georg, André Brinkmann, Mikael Högqvist, Alexander Papaspyrou, Bernhard Schott, Dietmar Sommerfeld, and Wolfgang Ziegler. “Infrastructure Federation Through Virtualized Delegation of Resources and Services.” Journal of Grid Computing 9, no. 3 (2011): 355–77. https://doi.org/10.1007/s10723-011-9192-1.","ama":"Birkenheuer G, Brinkmann A, Högqvist M, et al. Infrastructure Federation Through Virtualized Delegation of Resources and Services. Journal of Grid Computing. 2011;9(3):355-377. doi:10.1007/s10723-011-9192-1","apa":"Birkenheuer, G., Brinkmann, A., Högqvist, M., Papaspyrou, A., Schott, B., Sommerfeld, D., & Ziegler, W. (2011). Infrastructure Federation Through Virtualized Delegation of Resources and Services. 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Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}]},{"language":[{"iso":"eng"}],"page":"177-180","year":"2011","type":"conference","citation":{"short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. 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