[{"title":"SIMULATeQCD: A simple multi-GPU lattice code for QCD calculations","user_id":"90492","abstract":[{"text":"The rise of exascale supercomputers has fueled competition among GPU vendors, driving lattice QCD developers to write code that supports multiple APIs. Moreover, new developments in algorithms and physics research require frequent updates to existing software. These challenges have to be balanced against constantly changing personnel. At the same time, there is a wide range of applications for HISQ fermions in QCD studies. This situation encourages the development of software featuring a HISQ action that is flexible, high-performing, open source, easy to use, and easy to adapt. In this technical paper, we explain the design strategy, provide implementation details, list available algorithms and modules, and show key performance indicators for SIMULATeQCD, a simple multi-GPU lattice code for large-scale QCD calculations, mainly developed and used by the HotQCD collaboration. The code is publicly available on GitHub.","lang":"eng"}],"status":"public","date_created":"2023-07-24T10:55:25Z","author":[{"last_name":"Mazur","id":"90492","first_name":"Lukas","full_name":"Mazur, Lukas","orcid":" 0000-0001-6304-7082"},{"full_name":"Bollweg, Dennis","first_name":"Dennis","last_name":"Bollweg"},{"full_name":"Clarke, David A.","first_name":"David A.","last_name":"Clarke"},{"last_name":"Altenkort","first_name":"Luis","full_name":"Altenkort, Luis"},{"last_name":"Kaczmarek","full_name":"Kaczmarek, Olaf","first_name":"Olaf"},{"last_name":"Larsen","full_name":"Larsen, Rasmus","first_name":"Rasmus"},{"first_name":"Hai-Tao","full_name":"Shu, Hai-Tao","last_name":"Shu"},{"first_name":"Jishnu","full_name":"Goswami, Jishnu","last_name":"Goswami"},{"full_name":"Scior, Philipp","first_name":"Philipp","last_name":"Scior"},{"full_name":"Sandmeyer, Hauke","first_name":"Hauke","last_name":"Sandmeyer"},{"full_name":"Neumann, Marius","first_name":"Marius","last_name":"Neumann"},{"last_name":"Dick","first_name":"Henrik","full_name":"Dick, Henrik"},{"first_name":"Sajid","full_name":"Ali, Sajid","last_name":"Ali"},{"full_name":"Kim, Jangho","first_name":"Jangho","last_name":"Kim"},{"full_name":"Schmidt, Christian","first_name":"Christian","last_name":"Schmidt"},{"full_name":"Petreczky, Peter","first_name":"Peter","last_name":"Petreczky"},{"last_name":"Mukherjee","full_name":"Mukherjee, Swagato","first_name":"Swagato"}],"publication":"Computer Physics Communications","department":[{"_id":"27"}],"doi":"10.48550/ARXIV.2306.01098","date_updated":"2023-07-26T09:21:35Z","_id":"46120","year":"2023","type":"journal_article","citation":{"mla":"Mazur, Lukas, et al. “SIMULATeQCD: A Simple Multi-GPU Lattice Code for QCD Calculations.” Computer Physics Communications, 2023, doi:10.48550/ARXIV.2306.01098.","bibtex":"@article{Mazur_Bollweg_Clarke_Altenkort_Kaczmarek_Larsen_Shu_Goswami_Scior_Sandmeyer_et al._2023, title={SIMULATeQCD: A simple multi-GPU lattice code for QCD calculations}, DOI={10.48550/ARXIV.2306.01098}, journal={Computer Physics Communications}, author={Mazur, Lukas and Bollweg, Dennis and Clarke, David A. and Altenkort, Luis and Kaczmarek, Olaf and Larsen, Rasmus and Shu, Hai-Tao and Goswami, Jishnu and Scior, Philipp and Sandmeyer, Hauke and et al.}, year={2023} }","ama":"Mazur L, Bollweg D, Clarke DA, et al. SIMULATeQCD: A simple multi-GPU lattice code for QCD calculations. Computer Physics Communications. Published online 2023. doi:10.48550/ARXIV.2306.01098","apa":"Mazur, L., Bollweg, D., Clarke, D. A., Altenkort, L., Kaczmarek, O., Larsen, R., Shu, H.-T., Goswami, J., Scior, P., Sandmeyer, H., Neumann, M., Dick, H., Ali, S., Kim, J., Schmidt, C., Petreczky, P., & Mukherjee, S. (2023). SIMULATeQCD: A simple multi-GPU lattice code for QCD calculations. Computer Physics Communications. https://doi.org/10.48550/ARXIV.2306.01098","chicago":"Mazur, Lukas, Dennis Bollweg, David A. Clarke, Luis Altenkort, Olaf Kaczmarek, Rasmus Larsen, Hai-Tao Shu, et al. “SIMULATeQCD: A Simple Multi-GPU Lattice Code for QCD Calculations.” Computer Physics Communications, 2023. https://doi.org/10.48550/ARXIV.2306.01098.","ieee":"L. Mazur et al., “SIMULATeQCD: A simple multi-GPU lattice code for QCD calculations,” Computer Physics Communications, 2023, doi: 10.48550/ARXIV.2306.01098.","short":"L. Mazur, D. Bollweg, D.A. Clarke, L. Altenkort, O. Kaczmarek, R. Larsen, H.-T. Shu, J. Goswami, P. Scior, H. Sandmeyer, M. Neumann, H. Dick, S. Ali, J. Kim, C. Schmidt, P. Petreczky, S. Mukherjee, Computer Physics Communications (2023)."},"language":[{"iso":"eng"}]},{"publication_status":"published","publication_identifier":{"issn":["2470-0010","2470-0029"]},"department":[{"_id":"27"}],"title":"Viscosity of pure-glue QCD from the lattice","language":[{"iso":"eng"}],"doi":"10.1103/physrevd.108.014503","date_updated":"2023-07-26T09:23:32Z","date_created":"2023-07-24T10:54:18Z","status":"public","volume":108,"publication":"Physical Review D","publisher":"American Physical Society (APS)","quality_controlled":"1","author":[{"full_name":"Altenkort, Luis","first_name":"Luis","last_name":"Altenkort"},{"full_name":"Eller, Alexander M.","first_name":"Alexander M.","last_name":"Eller"},{"last_name":"Francis","first_name":"Anthony","full_name":"Francis, Anthony"},{"first_name":"Olaf","full_name":"Kaczmarek, Olaf","last_name":"Kaczmarek"},{"last_name":"Mazur","id":"90492","first_name":"Lukas","full_name":"Mazur, Lukas","orcid":" 0000-0001-6304-7082"},{"full_name":"Moore, Guy D.","first_name":"Guy D.","last_name":"Moore"},{"full_name":"Shu, Hai-Tao","first_name":"Hai-Tao","last_name":"Shu"}],"user_id":"90492","type":"journal_article","year":"2023","citation":{"ieee":"L. Altenkort et al., “Viscosity of pure-glue QCD from the lattice,” Physical Review D, vol. 108, no. 1, Art. no. 014503, 2023, doi: 10.1103/physrevd.108.014503.","short":"L. Altenkort, A.M. Eller, A. Francis, O. Kaczmarek, L. Mazur, G.D. Moore, H.-T. Shu, Physical Review D 108 (2023).","mla":"Altenkort, Luis, et al. “Viscosity of Pure-Glue QCD from the Lattice.” Physical Review D, vol. 108, no. 1, 014503, American Physical Society (APS), 2023, doi:10.1103/physrevd.108.014503.","bibtex":"@article{Altenkort_Eller_Francis_Kaczmarek_Mazur_Moore_Shu_2023, title={Viscosity of pure-glue QCD from the lattice}, volume={108}, DOI={10.1103/physrevd.108.014503}, number={1014503}, journal={Physical Review D}, publisher={American Physical Society (APS)}, author={Altenkort, Luis and Eller, Alexander M. and Francis, Anthony and Kaczmarek, Olaf and Mazur, Lukas and Moore, Guy D. and Shu, Hai-Tao}, year={2023} }","apa":"Altenkort, L., Eller, A. M., Francis, A., Kaczmarek, O., Mazur, L., Moore, G. D., & Shu, H.-T. (2023). Viscosity of pure-glue QCD from the lattice. Physical Review D, 108(1), Article 014503. https://doi.org/10.1103/physrevd.108.014503","ama":"Altenkort L, Eller AM, Francis A, et al. Viscosity of pure-glue QCD from the lattice. Physical Review D. 2023;108(1). doi:10.1103/physrevd.108.014503","chicago":"Altenkort, Luis, Alexander M. Eller, Anthony Francis, Olaf Kaczmarek, Lukas Mazur, Guy D. Moore, and Hai-Tao Shu. “Viscosity of Pure-Glue QCD from the Lattice.” Physical Review D 108, no. 1 (2023). https://doi.org/10.1103/physrevd.108.014503."},"issue":"1","article_number":"014503","intvolume":" 108","_id":"46119"},{"oa":"1","doi":"10.1145/3576200","date_updated":"2023-07-28T08:02:05Z","language":[{"iso":"eng"}],"title":"Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"name":"SFB 901: SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"publication_status":"published","publication_identifier":{"issn":["1936-7406","1936-7414"]},"department":[{"_id":"27"},{"_id":"518"}],"_id":"38041","citation":{"ieee":"M. Meyer, T. Kenter, and C. Plessl, “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks,” ACM Transactions on Reconfigurable Technology and Systems, 2023, doi: 10.1145/3576200.","short":"M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (2023).","mla":"Meyer, Marius, et al. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable Technology and Systems, Association for Computing Machinery (ACM), 2023, doi:10.1145/3576200.","bibtex":"@article{Meyer_Kenter_Plessl_2023, title={Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks}, DOI={10.1145/3576200}, journal={ACM Transactions on Reconfigurable Technology and Systems}, publisher={Association for Computing Machinery (ACM)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2023} }","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable Technology and Systems, 2023. https://doi.org/10.1145/3576200.","apa":"Meyer, M., Kenter, T., & Plessl, C. (2023). Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/3576200","ama":"Meyer M, Kenter T, Plessl C. Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions on Reconfigurable Technology and Systems. Published online 2023. doi:10.1145/3576200"},"year":"2023","type":"journal_article","main_file_link":[{"url":"https://dl.acm.org/doi/10.1145/3576200","open_access":"1"}],"user_id":"24135","abstract":[{"lang":"eng","text":"
The effect of traces of ethanol in supercritical carbon dioxide on the mixture's thermodynamic properties is studied by molecular simulations and Taylor dispersion measurements.
"}],"user_id":"15278","keyword":["Physical and Theoretical Chemistry","General Physics and Astronomy"],"publication":"Physical Chemistry Chemical Physics","quality_controlled":"1","author":[{"last_name":"Chatwell","full_name":"Chatwell, René Spencer","first_name":"René Spencer"},{"first_name":"Gabriela","full_name":"Guevara-Carrion, Gabriela","last_name":"Guevara-Carrion"},{"last_name":"Gaponenko","first_name":"Yuri","full_name":"Gaponenko, Yuri"},{"last_name":"Shevtsova","first_name":"Valentina","full_name":"Shevtsova, Valentina"},{"last_name":"Vrabec","first_name":"Jadran","full_name":"Vrabec, Jadran"}],"publisher":"Royal Society of Chemistry (RSC)","date_created":"2022-06-28T07:23:22Z","status":"public","volume":23},{"date_created":"2022-02-21T14:26:37Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","publication_status":"published","publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Karp","first_name":"Martin","full_name":"Karp, Martin"},{"first_name":"Artur","full_name":"Podobas, Artur","last_name":"Podobas"},{"first_name":"Niclas","full_name":"Jansson, Niclas","last_name":"Jansson"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Schlatter, Philipp","first_name":"Philipp","last_name":"Schlatter"},{"last_name":"Markidis","first_name":"Stefano","full_name":"Markidis, Stefano"}],"user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","language":[{"iso":"eng"}],"type":"conference","year":"2021","citation":{"ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116"},"doi":"10.1109/ipdps49936.2021.00116","_id":"29937","date_updated":"2024-01-22T09:59:13Z"},{"ddc":["000"],"title":"Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain","user_id":"27340","place":"Cham","publication_identifier":{"isbn":["9783030543334","9783030543341"]},"publication_status":"published","status":"public","date_created":"2020-09-01T13:49:42Z","author":[{"full_name":"Nickchen, Tobias","first_name":"Tobias","last_name":"Nickchen"},{"last_name":"Engels","first_name":"Gregor","full_name":"Engels, Gregor"},{"last_name":"Lohn","full_name":"Lohn, Johannes","first_name":"Johannes"}],"department":[{"_id":"534"},{"_id":"624"},{"_id":"27"},{"_id":"66"},{"_id":"219"}],"publication":"Industrializing Additive Manufacturing","doi":"10.1007/978-3-030-54334-1_4","_id":"18789","date_updated":"2022-01-06T06:53:52Z","conference":{"end_date":"2020-09-03","start_date":"2020-09-01"},"type":"book_chapter","year":"2020","citation":{"short":"T. Nickchen, G. Engels, J. Lohn, in: Industrializing Additive Manufacturing, Cham, 2020.","ieee":"T. Nickchen, G. Engels, and J. Lohn, “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain,” in Industrializing Additive Manufacturing, Cham, 2020.","apa":"Nickchen, T., Engels, G., & Lohn, J. (2020). Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain. In Industrializing Additive Manufacturing. Cham. https://doi.org/10.1007/978-3-030-54334-1_4","ama":"Nickchen T, Engels G, Lohn J. Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain. In: Industrializing Additive Manufacturing. Cham; 2020. doi:10.1007/978-3-030-54334-1_4","chicago":"Nickchen, Tobias, Gregor Engels, and Johannes Lohn. “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain.” In Industrializing Additive Manufacturing. Cham, 2020. https://doi.org/10.1007/978-3-030-54334-1_4.","bibtex":"@inbook{Nickchen_Engels_Lohn_2020, place={Cham}, title={Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain}, DOI={10.1007/978-3-030-54334-1_4}, booktitle={Industrializing Additive Manufacturing}, author={Nickchen, Tobias and Engels, Gregor and Lohn, Johannes}, year={2020} }","mla":"Nickchen, Tobias, et al. “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain.” Industrializing Additive Manufacturing, 2020, doi:10.1007/978-3-030-54334-1_4."},"language":[{"iso":"eng"}]},{"user_id":"15278","abstract":[{"lang":"eng","text":"State-of-the-art methods in materials science such as artificial intelligence and data-driven techniques advance the investigation of photovoltaic materials.
"}],"volume":22,"status":"public","date_created":"2022-06-28T08:02:39Z","publisher":"Royal Society of Chemistry (RSC)","author":[{"full_name":"Mirhosseini, Hossein","first_name":"Hossein","last_name":"Mirhosseini"},{"first_name":"Ramya","full_name":"Kormath Madam Raghupathy, Ramya","last_name":"Kormath Madam Raghupathy"},{"full_name":"Sahoo, Sudhir K.","first_name":"Sudhir K.","last_name":"Sahoo"},{"last_name":"Wiebeler","first_name":"Hendrik","full_name":"Wiebeler, Hendrik"},{"last_name":"Chugh","first_name":"Manjusha","full_name":"Chugh, Manjusha"},{"first_name":"Thomas D.","full_name":"Kühne, Thomas D.","last_name":"Kühne"}],"keyword":["Physical and Theoretical Chemistry","General Physics and Astronomy"],"publication":"Physical Chemistry Chemical Physics","issue":"46","_id":"32246","intvolume":" 22","type":"journal_article","citation":{"bibtex":"@article{Mirhosseini_Kormath Madam Raghupathy_Sahoo_Wiebeler_Chugh_Kühne_2020, title={In silico investigation of Cu(In,Ga)Se2-based solar cells}, volume={22}, DOI={10.1039/d0cp04712k}, number={46}, journal={Physical Chemistry Chemical Physics}, publisher={Royal Society of Chemistry (RSC)}, author={Mirhosseini, Hossein and Kormath Madam Raghupathy, Ramya and Sahoo, Sudhir K. and Wiebeler, Hendrik and Chugh, Manjusha and Kühne, Thomas D.}, year={2020}, pages={26682–26701} }","mla":"Mirhosseini, Hossein, et al. “In Silico Investigation of Cu(In,Ga)Se2-Based Solar Cells.” Physical Chemistry Chemical Physics, vol. 22, no. 46, Royal Society of Chemistry (RSC), 2020, pp. 26682–701, doi:10.1039/d0cp04712k.","apa":"Mirhosseini, H., Kormath Madam Raghupathy, R., Sahoo, S. K., Wiebeler, H., Chugh, M., & Kühne, T. D. (2020). In silico investigation of Cu(In,Ga)Se2-based solar cells. Physical Chemistry Chemical Physics, 22(46), 26682–26701. https://doi.org/10.1039/d0cp04712k","ama":"Mirhosseini H, Kormath Madam Raghupathy R, Sahoo SK, Wiebeler H, Chugh M, Kühne TD. In silico investigation of Cu(In,Ga)Se2-based solar cells. Physical Chemistry Chemical Physics. 2020;22(46):26682-26701. doi:10.1039/d0cp04712k","chicago":"Mirhosseini, Hossein, Ramya Kormath Madam Raghupathy, Sudhir K. Sahoo, Hendrik Wiebeler, Manjusha Chugh, and Thomas D. Kühne. “In Silico Investigation of Cu(In,Ga)Se2-Based Solar Cells.” Physical Chemistry Chemical Physics 22, no. 46 (2020): 26682–701. https://doi.org/10.1039/d0cp04712k.","ieee":"H. Mirhosseini, R. Kormath Madam Raghupathy, S. K. Sahoo, H. Wiebeler, M. Chugh, and T. D. Kühne, “In silico investigation of Cu(In,Ga)Se2-based solar cells,” Physical Chemistry Chemical Physics, vol. 22, no. 46, pp. 26682–26701, 2020, doi: 10.1039/d0cp04712k.","short":"H. Mirhosseini, R. Kormath Madam Raghupathy, S.K. Sahoo, H. Wiebeler, M. Chugh, T.D. Kühne, Physical Chemistry Chemical Physics 22 (2020) 26682–26701."},"year":"2020","page":"26682-26701","title":"In silico investigation of Cu(In,Ga)Se2-based solar cells","publication_identifier":{"issn":["1463-9076","1463-9084"]},"publication_status":"published","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"}],"doi":"10.1039/d0cp04712k","date_updated":"2022-06-28T08:03:05Z","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"citation":{"apa":"Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813.","ama":"Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020.","chicago":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","bibtex":"@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }","mla":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","short":"V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020).","ieee":"V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020."},"type":"preprint","year":"2020","_id":"32242","date_updated":"2022-06-28T07:27:19Z","publication":"arXiv:2011.00813","department":[{"_id":"27"}],"author":[{"first_name":"Viktor","full_name":"Bengs, Viktor","last_name":"Bengs"},{"first_name":"Eyke","full_name":"Hüllermeier, Eyke","last_name":"Hüllermeier"}],"date_created":"2022-06-28T07:26:54Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","external_id":{"arxiv":["2011.00813"]},"abstract":[{"text":"We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms.","lang":"eng"}],"user_id":"15278","title":"Multi-Armed Bandits with Censored Consumption of Resources"},{"file":[{"relation":"main_file","success":1,"date_updated":"2020-05-25T15:21:56Z","content_type":"application/pdf","creator":"lass","file_id":"17061","file_size":4887650,"access_level":"closed","file_name":"5.0007045.pdf","date_created":"2020-05-25T15:21:56Z"}],"author":[{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"last_name":"Iannuzzi","full_name":"Iannuzzi, Marcella","first_name":"Marcella"},{"last_name":"Ben","first_name":"Mauro Del","full_name":"Ben, Mauro Del"},{"full_name":"Rybkin, Vladimir V.","first_name":"Vladimir V.","last_name":"Rybkin"},{"last_name":"Seewald","full_name":"Seewald, Patrick","first_name":"Patrick"},{"full_name":"Stein, Frederick","first_name":"Frederick","last_name":"Stein"},{"full_name":"Laino, Teodoro","first_name":"Teodoro","last_name":"Laino"},{"full_name":"Khaliullin, Rustam Z.","first_name":"Rustam Z.","last_name":"Khaliullin"},{"first_name":"Ole","full_name":"Schütt, Ole","last_name":"Schütt"},{"last_name":"Schiffmann","full_name":"Schiffmann, Florian","first_name":"Florian"},{"first_name":"Dorothea","full_name":"Golze, Dorothea","last_name":"Golze"},{"last_name":"Wilhelm","first_name":"Jan","full_name":"Wilhelm, Jan"},{"last_name":"Chulkov","full_name":"Chulkov, Sergey","first_name":"Sergey"},{"last_name":"Mohammad Hossein Bani-Hashemian","first_name":"Mohammad Hossein Bani-Hashemian","full_name":"Mohammad Hossein Bani-Hashemian, Mohammad Hossein Bani-Hashemian"},{"full_name":"Weber, Valéry","first_name":"Valéry","last_name":"Weber"},{"last_name":"Borstnik","first_name":"Urban","full_name":"Borstnik, Urban"},{"full_name":"Taillefumier, Mathieu","first_name":"Mathieu","last_name":"Taillefumier"},{"first_name":"Alice Shoshana","full_name":"Jakobovits, Alice Shoshana","last_name":"Jakobovits"},{"last_name":"Lazzaro","first_name":"Alfio","full_name":"Lazzaro, Alfio"},{"full_name":"Pabst, Hans","first_name":"Hans","last_name":"Pabst"},{"last_name":"Müller","first_name":"Tiziano","full_name":"Müller, Tiziano"},{"full_name":"Schade, Robert","orcid":"0000-0002-6268-539","first_name":"Robert","id":"75963","last_name":"Schade"},{"last_name":"Guidon","first_name":"Manuel","full_name":"Guidon, Manuel"},{"first_name":"Samuel","full_name":"Andermatt, Samuel","last_name":"Andermatt"},{"full_name":"Holmberg, Nico","first_name":"Nico","last_name":"Holmberg"},{"last_name":"Schenter","first_name":"Gregory K.","full_name":"Schenter, Gregory K."},{"first_name":"Anna","full_name":"Hehn, Anna","last_name":"Hehn"},{"last_name":"Bussy","full_name":"Bussy, Augustin","first_name":"Augustin"},{"last_name":"Belleflamme","first_name":"Fabian","full_name":"Belleflamme, Fabian"},{"last_name":"Tabacchi","full_name":"Tabacchi, Gloria","first_name":"Gloria"},{"first_name":"Andreas","full_name":"Glöß, Andreas","last_name":"Glöß"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"first_name":"Iain","full_name":"Bethune, Iain","last_name":"Bethune"},{"full_name":"Mundy, Christopher J.","first_name":"Christopher J.","last_name":"Mundy"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Watkins, Matt","first_name":"Matt","last_name":"Watkins"},{"last_name":"VandeVondele","first_name":"Joost","full_name":"VandeVondele, Joost"},{"first_name":"Matthias","full_name":"Krack, Matthias","last_name":"Krack"},{"last_name":"Hutter","first_name":"Jürg","full_name":"Hutter, Jürg"}],"quality_controlled":"1","file_date_updated":"2020-05-25T15:21:56Z","publication":"The Journal of Chemical Physics","status":"public","has_accepted_license":"1","date_created":"2020-03-10T15:12:31Z","volume":152,"abstract":[{"lang":"eng","text":"CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension."}],"user_id":"75963","ddc":["540"],"main_file_link":[{"url":"https://aip.scitation.org/doi/pdf/10.1063/5.0007045?download=true","open_access":"1"}],"citation":{"bibtex":"@article{Kühne_Iannuzzi_Ben_Rybkin_Seewald_Stein_Laino_Khaliullin_Schütt_Schiffmann_et al._2020, title={CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations}, volume={152}, DOI={10.1063/5.0007045}, number={19194103}, journal={The Journal of Chemical Physics}, author={Kühne, Thomas and Iannuzzi, Marcella and Ben, Mauro Del and Rybkin, Vladimir V. and Seewald, Patrick and Stein, Frederick and Laino, Teodoro and Khaliullin, Rustam Z. and Schütt, Ole and Schiffmann, Florian and et al.}, year={2020} }","mla":"Kühne, Thomas, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics, vol. 152, no. 19, 194103, 2020, doi:10.1063/5.0007045.","ieee":"T. Kühne et al., “CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations,” The Journal of Chemical Physics, vol. 152, no. 19, Art. no. 194103, 2020, doi: 10.1063/5.0007045.","chicago":"Kühne, Thomas, Marcella Iannuzzi, Mauro Del Ben, Vladimir V. Rybkin, Patrick Seewald, Frederick Stein, Teodoro Laino, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics 152, no. 19 (2020). https://doi.org/10.1063/5.0007045.","short":"T. Kühne, M. Iannuzzi, M.D. Ben, V.V. Rybkin, P. Seewald, F. Stein, T. Laino, R.Z. Khaliullin, O. Schütt, F. Schiffmann, D. Golze, J. Wilhelm, S. Chulkov, M.H.B.-H. Mohammad Hossein Bani-Hashemian, V. Weber, U. Borstnik, M. Taillefumier, A.S. Jakobovits, A. Lazzaro, H. Pabst, T. Müller, R. Schade, M. Guidon, S. Andermatt, N. Holmberg, G.K. Schenter, A. Hehn, A. Bussy, F. Belleflamme, G. Tabacchi, A. Glöß, M. Lass, I. Bethune, C.J. Mundy, C. Plessl, M. Watkins, J. VandeVondele, M. Krack, J. Hutter, The Journal of Chemical Physics 152 (2020).","ama":"Kühne T, Iannuzzi M, Ben MD, et al. CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics. 2020;152(19). doi:10.1063/5.0007045","apa":"Kühne, T., Iannuzzi, M., Ben, M. D., Rybkin, V. V., Seewald, P., Stein, F., Laino, T., Khaliullin, R. Z., Schütt, O., Schiffmann, F., Golze, D., Wilhelm, J., Chulkov, S., Mohammad Hossein Bani-Hashemian, M. H. B.-H., Weber, V., Borstnik, U., Taillefumier, M., Jakobovits, A. S., Lazzaro, A., … Hutter, J. (2020). CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics, 152(19), Article 194103. https://doi.org/10.1063/5.0007045"},"year":"2020","type":"journal_article","_id":"16277","intvolume":" 152","issue":"19","article_number":"194103","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","external_id":{"arxiv":["2003.03868"]},"title":"CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations","language":[{"iso":"eng"}],"date_updated":"2023-08-02T14:56:21Z","oa":"1","doi":"10.1063/5.0007045"},{"user_id":"75963","abstract":[{"lang":"eng","text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs."}],"date_created":"2020-04-28T14:44:21Z","status":"public","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","quality_controlled":"1","author":[{"id":"24135","last_name":"Lass","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael"},{"full_name":"Schade, Robert","orcid":"0000-0002-6268-539","first_name":"Robert","id":"75963","last_name":"Schade"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE Computer Society","conference":{"location":"Atlanta, GA, US","name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)"},"_id":"16898","page":"1127-1140","year":"2020","type":"conference","citation":{"bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.","chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.","short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140."},"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K","external_id":{"arxiv":["2004.10811"]},"place":"Los Alamitos, CA, USA","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"doi":"10.1109/SC41405.2020.00084","date_updated":"2023-08-02T14:55:59Z","language":[{"iso":"eng"}]},{"publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","related_material":{"link":[{"description":"Official repository of the benchmark suite on GitHub","relation":"supplementary_material","url":"https://github.com/pc2/HPCC_FPGA"}]},"language":[{"iso":"eng"}],"doi":"10.1109/h2rc51942.2020.00007","date_updated":"2023-09-26T11:42:53Z","date_created":"2021-04-16T10:17:22Z","status":"public","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","author":[{"full_name":"Meyer, Marius","first_name":"Marius","id":"40778","last_name":"Meyer"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","user_id":"15278","abstract":[{"lang":"eng","text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community."}],"type":"conference","year":"2020","citation":{"ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007."},"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"_id":"21632"},{"year":"2020","type":"journal_article","citation":{"apa":"Rengaraj, V., Lass, M., Plessl, C., & Kühne, T. (2020). Accurate Sampling with Noisy Forces from Approximate Computing. Computation, 8(2), Article 39. https://doi.org/10.3390/computation8020039","ama":"Rengaraj V, Lass M, Plessl C, Kühne T. Accurate Sampling with Noisy Forces from Approximate Computing. Computation. 2020;8(2). doi:10.3390/computation8020039","chicago":"Rengaraj, Varadarajan, Michael Lass, Christian Plessl, and Thomas Kühne. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation 8, no. 2 (2020). https://doi.org/10.3390/computation8020039.","bibtex":"@article{Rengaraj_Lass_Plessl_Kühne_2020, title={Accurate Sampling with Noisy Forces from Approximate Computing}, volume={8}, DOI={10.3390/computation8020039}, number={239}, journal={Computation}, publisher={MDPI}, author={Rengaraj, Varadarajan and Lass, Michael and Plessl, Christian and Kühne, Thomas}, year={2020} }","mla":"Rengaraj, Varadarajan, et al. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation, vol. 8, no. 2, 39, MDPI, 2020, doi:10.3390/computation8020039.","short":"V. Rengaraj, M. Lass, C. Plessl, T. Kühne, Computation 8 (2020).","ieee":"V. Rengaraj, M. Lass, C. Plessl, and T. Kühne, “Accurate Sampling with Noisy Forces from Approximate Computing,” Computation, vol. 8, no. 2, Art. no. 39, 2020, doi: 10.3390/computation8020039."},"main_file_link":[{"url":"https://www.mdpi.com/2079-3197/8/2/39/pdf","open_access":"1"}],"article_number":"39","issue":"2","intvolume":" 8","_id":"12878","volume":8,"status":"public","date_created":"2019-07-23T12:03:07Z","publisher":"MDPI","quality_controlled":"1","author":[{"first_name":"Varadarajan","full_name":"Rengaraj, Varadarajan","last_name":"Rengaraj"},{"last_name":"Lass","id":"24135","first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"}],"publication":"Computation","user_id":"15278","abstract":[{"text":"In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.3390/computation8020039","oa":"1","date_updated":"2023-09-26T11:43:52Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"Accurate Sampling with Noisy Forces from Approximate Computing","external_id":{"arxiv":["1907.08497"]}},{"user_id":"16153","ddc":["000"],"article_type":"original","status":"public","has_accepted_license":"1","date_created":"2019-02-13T15:01:43Z","volume":16,"file":[{"file_id":"7695","creator":"deffel","file_size":872822,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-02-13T14:59:07Z","file_name":"htrop19_taco.pdf","date_created":"2019-02-13T14:59:07Z","access_level":"closed"}],"publisher":"ACM","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","file_date_updated":"2019-02-13T14:59:07Z","publication":"ACM Trans. Archit. Code Optim. (TACO)","keyword":["htrop"],"issue":"2","_id":"7689","intvolume":" 16","year":"2019","citation":{"ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019.","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, ACM Trans. Archit. Code Optim. (TACO) 16 (2019) 14:1–14:26.","bibtex":"@article{Riebler_Vaz_Kenter_Plessl_2019, title={Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}, volume={16}, DOI={10.1145/3319423}, number={2}, journal={ACM Trans. Archit. Code Optim. (TACO)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2019}, pages={14:1–14:26} }","mla":"Riebler, Heinrich, et al. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:10.1145/3319423.","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2019). Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans. Archit. Code Optim. (TACO), 16(2), 14:1–14:26. https://doi.org/10.1145/3319423","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans Archit Code Optim (TACO). 2019;16(2):14:1–14:26. doi:10.1145/3319423","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO) 16, no. 2 (2019): 14:1–14:26. https://doi.org/10.1145/3319423."},"type":"journal_article","page":"14:1–14:26","title":"Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1145/3319423","date_updated":"2022-01-06T07:03:44Z","language":[{"iso":"eng"}]},{"ddc":["004"],"user_id":"3145","abstract":[{"text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.","lang":"eng"}],"date_created":"2020-01-09T12:54:48Z","status":"public","has_accepted_license":"1","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2020-01-09T12:53:57Z","publisher":"IEEE","author":[{"first_name":"Paolo","full_name":"Gorlani, Paolo","last_name":"Gorlani","id":"72045"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file":[{"relation":"main_file","success":1,"date_updated":"2020-01-09T12:53:57Z","content_type":"application/pdf","creator":"plessl","file_id":"15479","file_size":250559,"access_level":"closed","file_name":"gorlani19_fpt.pdf","date_created":"2020-01-09T12:53:57Z"}],"conference":{"name":"International Conference on Field-Programmable Technology (FPT)"},"_id":"15478","citation":{"bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }","mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.","short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019."},"type":"conference","year":"2019","title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","project":[{"name":"HighPerMeshes","grant_number":"01|H16005","_id":"33"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1","_id":"32"}],"department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1109/ICFPT47387.2019.00020","date_updated":"2022-01-06T06:52:26Z","language":[{"iso":"eng"}]},{"doi":"10.17619/UNIPB/1-830","date_updated":"2022-11-30T14:44:15Z","_id":"34167","supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"language":[{"iso":"eng"}],"type":"dissertation","year":"2019","citation":{"chicago":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019. https://doi.org/10.17619/UNIPB/1-830.","apa":"Riebler, H. (2019). Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. https://doi.org/10.17619/UNIPB/1-830","ama":"Riebler H. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs.; 2019. doi:10.17619/UNIPB/1-830","bibtex":"@book{Riebler_2019, title={Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs}, DOI={10.17619/UNIPB/1-830}, author={Riebler, Heinrich}, year={2019} }","mla":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs. 2019, doi:10.17619/UNIPB/1-830.","short":"H. Riebler, Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019.","ieee":"H. Riebler, Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. 2019."},"user_id":"15504","title":"Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs","status":"public","date_created":"2022-11-30T14:36:04Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"}],"department":[{"_id":"27"}]},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:45:02Z","doi":"10.4208/cicp.OA-2018-0053","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"},{"_id":"104"}],"project":[{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"external_id":{"arxiv":["1703.02456"]},"title":"A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices","type":"journal_article","year":"2019","citation":{"bibtex":"@article{Richters_Lass_Walther_Plessl_Kühne_2019, title={A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices}, volume={25}, DOI={10.4208/cicp.OA-2018-0053}, number={2}, journal={Communications in Computational Physics}, publisher={Global Science Press}, author={Richters, Dorothee and Lass, Michael and Walther, Andrea and Plessl, Christian and Kühne, Thomas}, year={2019}, pages={564–585} }","mla":"Richters, Dorothee, et al. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics, vol. 25, no. 2, Global Science Press, 2019, pp. 564–85, doi:10.4208/cicp.OA-2018-0053.","chicago":"Richters, Dorothee, Michael Lass, Andrea Walther, Christian Plessl, and Thomas Kühne. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics 25, no. 2 (2019): 564–85. https://doi.org/10.4208/cicp.OA-2018-0053.","ama":"Richters D, Lass M, Walther A, Plessl C, Kühne T. A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics. 2019;25(2):564-585. doi:10.4208/cicp.OA-2018-0053","apa":"Richters, D., Lass, M., Walther, A., Plessl, C., & Kühne, T. (2019). A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics, 25(2), 564–585. https://doi.org/10.4208/cicp.OA-2018-0053","ieee":"D. Richters, M. Lass, A. Walther, C. Plessl, and T. Kühne, “A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices,” Communications in Computational Physics, vol. 25, no. 2, pp. 564–585, 2019, doi: 10.4208/cicp.OA-2018-0053.","short":"D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics 25 (2019) 564–585."},"page":"564-585","_id":"21","intvolume":" 25","issue":"2","publisher":"Global Science Press","quality_controlled":"1","author":[{"first_name":"Dorothee","full_name":"Richters, Dorothee","last_name":"Richters"},{"id":"24135","last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael"},{"first_name":"Andrea","full_name":"Walther, Andrea","last_name":"Walther"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"}],"publication":"Communications in Computational Physics","status":"public","date_created":"2017-07-25T14:48:26Z","volume":25,"abstract":[{"lang":"eng","text":"We address the general mathematical problem of computing the inverse p-th\r\nroot of a given matrix in an efficient way. A new method to construct iteration\r\nfunctions that allow calculating arbitrary p-th roots and their inverses of\r\nsymmetric positive definite matrices is presented. We show that the order of\r\nconvergence is at least quadratic and that adaptively adjusting a parameter q\r\nalways leads to an even faster convergence. In this way, a better performance\r\nthan with previously known iteration schemes is achieved. The efficiency of the\r\niterative functions is demonstrated for various matrices with different\r\ndensities, condition numbers and spectral radii."}],"user_id":"15278"},{"ddc":["004"],"user_id":"15278","file_date_updated":"2019-07-22T12:45:02Z","publication":"Informatik Spektrum","author":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","file":[{"file_size":248360,"creator":"plessl","file_id":"12872","content_type":"application/pdf","date_updated":"2019-07-22T12:45:02Z","relation":"main_file","file_name":"plessl19_informatik_spektrum.pdf","date_created":"2019-07-22T12:45:02Z","access_level":"open_access"}],"date_created":"2019-07-22T12:42:44Z","status":"public","has_accepted_license":"1","_id":"12871","year":"2019","type":"journal_article","citation":{"short":"M. Platzner, C. Plessl, Informatik Spektrum (2019).","ieee":"M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.","ama":"Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w","apa":"Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik Spektrum. https://doi.org/10.1007/s00287-019-01187-w","chicago":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.","bibtex":"@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }","mla":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w."},"title":"FPGAs im Rechenzentrum","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_status":"published","publication_identifier":{"issn":["0170-6012","1432-122X"]},"date_updated":"2023-09-26T11:45:57Z","doi":"10.1007/s00287-019-01187-w","oa":"1","language":[{"iso":"ger"}]},{"issue":"2","intvolume":" 10","_id":"20","year":"2018","citation":{"short":"M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters 10 (2018) 33–36.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” Embedded Systems Letters, vol. 10, no. 2, pp. 33–36, 2018.","apa":"Lass, M., Kühne, T., & Plessl, C. (2018). Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters, 10(2), 33–36. https://doi.org/10.1109/LES.2017.2760923","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters. 2018;10(2):33-36. doi:10.1109/LES.2017.2760923","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters 10, no. 2 (2018): 33–36. https://doi.org/10.1109/LES.2017.2760923.","mla":"Lass, Michael, et al. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters, vol. 10, no. 2, IEEE, 2018, pp. 33–36, doi:10.1109/LES.2017.2760923.","bibtex":"@article{Lass_Kühne_Plessl_2018, title={Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots}, volume={10}, DOI={10.1109/LES.2017.2760923}, number={2}, journal={Embedded Systems Letters}, publisher={IEEE}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2018}, pages={33–36} }"},"type":"journal_article","page":" 33-36","user_id":"16153","abstract":[{"lang":"eng","text":"Approximate computing has shown to provide new ways to improve performance\r\nand power consumption of error-resilient applications. While many of these\r\napplications can be found in image processing, data classification or machine\r\nlearning, we demonstrate its suitability to a problem from scientific\r\ncomputing. Utilizing the self-correcting behavior of iterative algorithms, we\r\nshow that approximate computing can be applied to the calculation of inverse\r\nmatrix p-th roots which are required in many applications in scientific\r\ncomputing. Results show great opportunities to reduce the computational effort\r\nand bandwidth required for the execution of the discussed algorithm, especially\r\nwhen targeting special accelerator hardware."}],"volume":10,"status":"public","date_created":"2017-07-25T14:41:08Z","author":[{"last_name":"Lass","id":"24135","first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"IEEE","publication":"Embedded Systems Letters","doi":"10.1109/LES.2017.2760923","date_updated":"2022-01-06T06:54:18Z","language":[{"iso":"eng"}],"title":"Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots","external_id":{"arxiv":["1703.02283"]},"publication_status":"published","publication_identifier":{"eissn":["1943-0671"],"issn":["1943-0663"]},"project":[{"grant_number":"PL 595/2-1","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}]},{"language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-77398-8_8","date_updated":"2022-01-06T06:55:22Z","editor":[{"last_name":"Klusáček","first_name":"D.","full_name":"Klusáček, D."},{"first_name":"W.","full_name":"Cirne, W.","last_name":"Cirne"},{"last_name":"Desai","full_name":"Desai, N.","first_name":"N."}],"publication_status":"published","publication_identifier":{"isbn":["978-3-319-77398-8","978-3-319-77397-1"]},"department":[{"_id":"27"}],"title":"A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems","citation":{"mla":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8.","bibtex":"@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }","apa":"Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8","ama":"Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8","chicago":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8.","ieee":"A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.","short":"A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151."},"year":"2018","type":"conference","page":"132-151","intvolume":" 10773","_id":"22","conference":{"location":"Orlando, FL, USA","start_date":"2017-06-02","name":"21st Workshop on Job Scheduling Strategies for Parallel Processing","end_date":"2017-06-02"},"status":"public","date_created":"2017-07-25T14:54:08Z","volume":10773,"author":[{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"}],"publisher":"Springer","keyword":["Scheduling Planning Mapping Workload management"],"publication":"Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)","user_id":"15274","abstract":[{"text":"This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\\(^2\\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation.","lang":"eng"}]},{"language":[{"iso":"eng"}],"doi":"10.1007/s12283-018-0291-0","date_updated":"2022-01-06T07:03:09Z","publication_identifier":{"issn":["1369-7072","1460-2687"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}],"title":"Sprint diagnostic with GPS and inertial sensor fusion","citation":{"short":"J.C. Mertens, A. Boschmann, M. Schmidt, C. Plessl, Sports Engineering 21 (2018) 441–451.","ieee":"J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” Sports Engineering, vol. 21, no. 4, pp. 441–451, 2018.","chicago":"Mertens, Jan Cedric, Alexander Boschmann, M. Schmidt, and Christian Plessl. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering 21, no. 4 (2018): 441–51. https://doi.org/10.1007/s12283-018-0291-0.","apa":"Mertens, J. C., Boschmann, A., Schmidt, M., & Plessl, C. (2018). Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering, 21(4), 441–451. https://doi.org/10.1007/s12283-018-0291-0","ama":"Mertens JC, Boschmann A, Schmidt M, Plessl C. Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering. 2018;21(4):441-451. doi:10.1007/s12283-018-0291-0","mla":"Mertens, Jan Cedric, et al. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering, vol. 21, no. 4, Springer Nature, 2018, pp. 441–51, doi:10.1007/s12283-018-0291-0.","bibtex":"@article{Mertens_Boschmann_Schmidt_Plessl_2018, title={Sprint diagnostic with GPS and inertial sensor fusion}, volume={21}, DOI={10.1007/s12283-018-0291-0}, number={4}, journal={Sports Engineering}, publisher={Springer Nature}, author={Mertens, Jan Cedric and Boschmann, Alexander and Schmidt, M. and Plessl, Christian}, year={2018}, pages={441–451} }"},"year":"2018","type":"journal_article","page":"441-451","issue":"4","intvolume":" 21","_id":"6516","volume":21,"has_accepted_license":"1","status":"public","date_created":"2019-01-08T17:44:43Z","author":[{"last_name":"Mertens","first_name":"Jan Cedric","full_name":"Mertens, Jan Cedric"},{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Schmidt","first_name":"M.","full_name":"Schmidt, M."},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"Springer Nature","quality_controlled":"1","file_date_updated":"2019-01-08T17:47:06Z","publication":"Sports Engineering","file":[{"access_level":"closed","date_created":"2019-01-08T17:47:06Z","file_name":"plessl18_sportseng.pdf","relation":"main_file","content_type":"application/pdf","date_updated":"2019-01-08T17:47:06Z","creator":"plessl","file_id":"6517","file_size":2141021}],"ddc":["000"],"user_id":"16153"},{"doi":"10.1364/josab.35.000146","date_updated":"2023-02-10T15:02:47Z","language":[{"iso":"eng"}],"title":"Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","publication_identifier":{"issn":["0740-3224","1520-8540"]},"department":[{"_id":"15"},{"_id":"170"},{"_id":"297"},{"_id":"230"},{"_id":"429"},{"_id":"27"}],"issue":"1","article_number":"146","_id":"13348","intvolume":" 35","year":"2018","citation":{"short":"S.M.H. Luk, P. Lewandowski, N.H. Kwong, E. Baudin, O. Lafont, J. Tignon, P.T. Leung, Ch.K.P. Chan, M. Babilon, S. Schumacher, R. Binder, Journal of the Optical Society of America B 35 (2018).","ieee":"S. M. H. Luk et al., “Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities,” Journal of the Optical Society of America B, vol. 35, no. 1, Art. no. 146, 2018, doi: 10.1364/josab.35.000146.","chicago":"Luk, Samuel M. H., P. Lewandowski, N. H. Kwong, E. Baudin, O. Lafont, J. Tignon, P. T. Leung, et al. “Theory of Optically Controlled Anisotropic Polariton Transport in Semiconductor Double Microcavities.” Journal of the Optical Society of America B 35, no. 1 (2018). https://doi.org/10.1364/josab.35.000146.","ama":"Luk SMH, Lewandowski P, Kwong NH, et al. Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities. Journal of the Optical Society of America B. 2018;35(1). doi:10.1364/josab.35.000146","apa":"Luk, S. M. H., Lewandowski, P., Kwong, N. H., Baudin, E., Lafont, O., Tignon, J., Leung, P. T., Chan, Ch. K. P., Babilon, M., Schumacher, S., & Binder, R. (2018). Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities. Journal of the Optical Society of America B, 35(1), Article 146. https://doi.org/10.1364/josab.35.000146","mla":"Luk, Samuel M. H., et al. “Theory of Optically Controlled Anisotropic Polariton Transport in Semiconductor Double Microcavities.” Journal of the Optical Society of America B, vol. 35, no. 1, 146, 2018, doi:10.1364/josab.35.000146.","bibtex":"@article{Luk_Lewandowski_Kwong_Baudin_Lafont_Tignon_Leung_Chan_Babilon_Schumacher_et al._2018, title={Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities}, volume={35}, DOI={10.1364/josab.35.000146}, number={1146}, journal={Journal of the Optical Society of America B}, author={Luk, Samuel M. H. and Lewandowski, P. and Kwong, N. H. and Baudin, E. and Lafont, O. and Tignon, J. and Leung, P. T. and Chan, Ch. K. P. and Babilon, M. and Schumacher, Stefan and et al.}, year={2018} }"},"type":"journal_article","user_id":"14931","date_created":"2019-09-19T13:50:06Z","status":"public","volume":35,"publication":"Journal of the Optical Society of America B","author":[{"last_name":"Luk","full_name":"Luk, Samuel M. H.","first_name":"Samuel M. H."},{"full_name":"Lewandowski, P.","first_name":"P.","last_name":"Lewandowski"},{"last_name":"Kwong","full_name":"Kwong, N. H.","first_name":"N. H."},{"first_name":"E.","full_name":"Baudin, E.","last_name":"Baudin"},{"last_name":"Lafont","first_name":"O.","full_name":"Lafont, O."},{"last_name":"Tignon","first_name":"J.","full_name":"Tignon, J."},{"last_name":"Leung","full_name":"Leung, P. T.","first_name":"P. T."},{"last_name":"Chan","first_name":"Ch. K. P.","full_name":"Chan, Ch. K. P."},{"last_name":"Babilon","full_name":"Babilon, M.","first_name":"M."},{"id":"27271","last_name":"Schumacher","full_name":"Schumacher, Stefan","orcid":"0000-0003-4042-4951","first_name":"Stefan"},{"first_name":"R.","full_name":"Binder, R.","last_name":"Binder"}]},{"abstract":[{"text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.","lang":"eng"}],"user_id":"15278","ddc":["000"],"file":[{"relation":"main_file","success":1,"date_updated":"2018-11-02T14:45:05Z","content_type":"application/pdf","creator":"ups","file_id":"5282","file_size":269130,"access_level":"closed","file_name":"08457652.pdf","date_created":"2018-11-02T14:45:05Z"}],"file_date_updated":"2018-11-02T14:45:05Z","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","keyword":["tet_topic_hpc"],"publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Mahale","full_name":"Mahale, Gopinath","first_name":"Gopinath"},{"id":"42456","last_name":"Alhaddad","full_name":"Alhaddad, Samer","first_name":"Samer"},{"last_name":"Grynko","id":"26059","first_name":"Yevgen","full_name":"Grynko, Yevgen"},{"last_name":"Schmitt","full_name":"Schmitt, Christian","first_name":"Christian"},{"last_name":"Afzal","first_name":"Ayesha","full_name":"Afzal, Ayesha"},{"last_name":"Hannig","full_name":"Hannig, Frank","first_name":"Frank"},{"first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","id":"158"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","date_created":"2018-03-22T10:48:01Z","has_accepted_license":"1","status":"public","conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"_id":"1588","citation":{"short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }"},"year":"2018","type":"conference","title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"grant_number":"01|H16005A","name":"HighPerMeshes","_id":"33"},{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"date_updated":"2023-09-26T11:47:52Z","doi":"10.1109/FCCM.2018.00037","language":[{"iso":"eng"}]},{"project":[{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","external_id":{"arxiv":["1710.10899"]},"place":"New York, NY, USA","language":[{"iso":"eng"}],"doi":"10.1145/3218176.3218231","date_updated":"2023-09-26T11:48:12Z","date_created":"2018-03-22T10:53:01Z","status":"public","keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","publisher":"ACM","author":[{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"},{"full_name":"Mohr, Stephan","first_name":"Stephan","last_name":"Mohr"},{"last_name":"Wiebeler","first_name":"Hendrik","full_name":"Wiebeler, Hendrik"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","user_id":"15278","abstract":[{"lang":"eng","text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution."}],"citation":{"ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231.","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231"},"year":"2018","type":"conference","conference":{"end_date":"2018-07-04","start_date":"2018-07-02","name":"Platform for Advanced Scientific Computing Conference (PASC)","location":"Basel, Switzerland"},"_id":"1590"},{"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"publication_identifier":{"isbn":["9781450349826"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1145/3178487.3178534","date_updated":"2023-09-26T11:47:23Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["000"],"date_created":"2018-03-08T14:45:18Z","status":"public","has_accepted_license":"1","file":[{"date_updated":"2018-11-02T14:43:37Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":447769,"file_id":"5281","creator":"ups","access_level":"closed","file_name":"p417-riebler.pdf","date_created":"2018-11-02T14:43:37Z"}],"keyword":["htrop"],"publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","file_date_updated":"2018-11-02T14:43:37Z","publisher":"ACM","quality_controlled":"1","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"_id":"1204","type":"conference","citation":{"short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534.","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }"},"year":"2018"},{"doi":"10.1145/3053687","date_updated":"2023-09-26T13:23:58Z","language":[{"iso":"eng"}],"title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","publication_identifier":{"issn":["1936-7406"]},"publication_status":"published","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"issue":"3","_id":"18","intvolume":" 10","year":"2017","citation":{"chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.","apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23. https://doi.org/10.1145/3053687","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687.","bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={10.1145/3053687}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.","ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi: 10.1145/3053687."},"type":"journal_article","page":"24:1-24:23","ddc":["000"],"user_id":"15278","abstract":[{"text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.","lang":"eng"}],"volume":10,"has_accepted_license":"1","status":"public","date_created":"2017-07-25T14:17:32Z","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"full_name":"Mittendorf, Robert","first_name":"Robert","last_name":"Mittendorf"},{"last_name":"Löcke","first_name":"Thomas","full_name":"Löcke, Thomas"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"Association for Computing Machinery (ACM)","keyword":["coldboot"],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","file_date_updated":"2018-11-02T16:04:14Z","file":[{"success":1,"relation":"main_file","date_updated":"2018-11-02T16:04:14Z","content_type":"application/pdf","creator":"ups","file_id":"5322","file_size":2131617,"access_level":"closed","file_name":"a24-riebler.pdf","date_created":"2018-11-02T16:04:14Z"}]},{"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-11-02T15:02:28Z","keyword":["tet_topic_hpc"],"quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens","id":"158","last_name":"Förstner"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","file":[{"date_created":"2018-11-02T15:02:28Z","file_name":"08056844.pdf","access_level":"closed","creator":"ups","file_id":"5291","file_size":230235,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-11-02T15:02:28Z"}],"date_created":"2018-03-22T11:10:23Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures."}],"ddc":["000"],"user_id":"15278","citation":{"ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844.","apa":"Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844","ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844"},"type":"conference","year":"2017","_id":"1592","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"},{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"Flexible FPGA design for FDTD using OpenCL","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:24:38Z","doi":"10.23919/FPL.2017.8056844"},{"language":[{"iso":"eng"}],"type":"journal_article","citation":{"chicago":"Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series 898 (2017). https://doi.org/10.1088/1742-6596/898/8/082003.","apa":"Schumacher, J., Plessl, C., & Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series, 898, Article 082003. https://doi.org/10.1088/1742-6596/898/8/082003","ama":"Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series. 2017;898. doi:10.1088/1742-6596/898/8/082003","mla":"Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series, vol. 898, 082003, IOP Publishing, 2017, doi:10.1088/1742-6596/898/8/082003.","bibtex":"@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={10.1088/1742-6596/898/8/082003}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }","short":"J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017).","ieee":"J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi: 10.1088/1742-6596/898/8/082003."},"year":"2017","doi":"10.1088/1742-6596/898/8/082003","article_number":"082003","_id":"1589","intvolume":" 898","date_updated":"2023-09-26T13:24:19Z","date_created":"2018-03-22T10:51:20Z","status":"public","volume":898,"publication":"Journal of Physics: Conference Series","department":[{"_id":"27"},{"_id":"518"}],"author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Wainer","full_name":"Vandelli, Wainer","last_name":"Vandelli"}],"quality_controlled":"1","publisher":"IOP Publishing","user_id":"15278","title":"High-Throughput and Low-Latency Network Communication with NetIO"},{"abstract":[{"lang":"eng","text":"Lightweight materials play an ever growing role in today's world. Saving on the mass of a machine will usually translate into a lower energy consumption. However, lightweight applications are prone to develop performance problems due to vibration induced by the operation of the machine. The Fraunhofer Institute for Manufacturing Technology and Advanced Materials in Dresden conducts research into the damping properties of composite materials. They are experimenting with hollow, particle filled spheres embedded in the lightweight material. Such a system is the technical motivation of this thesis. Ultimately, a numerical experiment to derive the coefficient of restitution is required. The simulation developed in this thesis is based on a discrete element method to track the individual particle and sphere trajectories. Based on a potential based approach for the particle interactions deployed in molecular dynamics, the behavior of the particles can be controlled effectively. The simulated volume is using reflecting boundaries and encloses the hollow sphere. In this work, a highly flexible memory structure was used with a linked cell approach to cope with the highly flexible mass of particles. This allows for a linear complexity of the method in regard to the particle number by reducing the computational overhead of the interaction computation. Multiple numerical experiments show the great effect the particles have on the damping behavior of the system."},{"text":"In vielen technischen Anwendungen spielt heute der Leichtbau eine große Rolle, denn durch Gewichtseinsparungen lässt sich auch Energie einsparen. Allerdings birgt der Leichtbau die Gefahr einer erhöhten Störanfälligkeit gegenüber Vibrationen, die durch die Operation von Maschinen entstehen können. Das Fraunhofer Institut für Fertigungstechnik und Angewandte Materialforschung in Dresden beschäftigt sich mit den Möglichkeiten einer Schwingungsdämpfung durch Verbundwerkstoffe. Dabei wird in die Leichtbaustruktur eine Vielzahl von Hohlkugeln eingebracht, die mit Keramikpartikeln gefüllt sind. Diese Fragestellung bildet die technische Motivation für diese Arbeit. Ziel ist, ein Experiment zur Bestimmung des Restitutionskoeffizienten numerisch nachzubilden. Die Simulation basiert auf einer Diskreten Elemente Methode um die Trajektorien der einzelnen Partikel und der Kugel berechnen zu können. Basierend auf einem Potentialansatz für die Interaktionsberechnung in der Molekulardynamik kann das Reibungsverhalten vielfältig angepasst werden. Das Simulationsvolumen wird durch reflektierende Randbedingungen abgeschlossen und umfasst die Kugelhülle. Dazu kam eine hochflexible Speicherstruktur zum Einsatz, um die heterogene Verteilung der Partikel im Raum mit einer effizienten Linked Cell Methode abbilden zu können. Dadurch wird eine in der Partikelzahl lineare Komplexität erreicht. Umfangreiche numerische Experimente zeigen den großen Effekt der Partikelfüllung auf das Dämpfungsverhalten.","lang":"ger"}],"title":"Modeling and simulation of metallic, particle-damped spheres for lightweight materials","user_id":"24135","department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"author":[{"first_name":"Tobias","full_name":"Steinle, Tobias","last_name":"Steinle"}],"date_created":"2017-07-26T15:19:44Z","status":"public","date_updated":"2022-01-06T06:59:09Z","_id":"33","main_file_link":[{"url":"http://nbn-resolving.de/urn:nbn:de:hbz:466:2-24042"}],"type":"dissertation","year":"2016","citation":{"chicago":"Steinle, Tobias. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials, 2016.","ama":"Steinle T. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials.; 2016.","apa":"Steinle, T. (2016). Modeling and simulation of metallic, particle-damped spheres for lightweight materials.","mla":"Steinle, Tobias. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials. 2016.","bibtex":"@book{Steinle_2016, title={Modeling and simulation of metallic, particle-damped spheres for lightweight materials}, author={Steinle, Tobias}, year={2016} }","short":"T. Steinle, Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials, 2016.","ieee":"T. Steinle, Modeling and simulation of metallic, particle-damped spheres for lightweight materials. 2016."},"supervisor":[{"last_name":"Walther","first_name":"Andrea","full_name":"Walther, Andrea"},{"first_name":"Jadran","full_name":"Vrabec, Jadran","last_name":"Vrabec"}],"language":[{"iso":"eng"}]},{"_id":"34","date_updated":"2022-01-06T06:59:14Z","intvolume":" 22","doi":"10.1007/978-3-319-23413-7_87","series_title":"Mathematics in Industry","citation":{"ieee":"M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641.","short":"M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.","bibtex":"@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }","mla":"Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87.","chicago":"Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.","apa":"Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87","ama":"Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87"},"type":"conference","year":"2016","page":"633-641","place":"Cham","title":"Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control","user_id":"24135","author":[{"last_name":"Dellnitz","first_name":"Michael","full_name":"Dellnitz, Michael"},{"last_name":"Eckstein","full_name":"Eckstein, Julian","first_name":"Julian"},{"first_name":"Kathrin","full_name":"Flaßkamp, Kathrin","last_name":"Flaßkamp"},{"first_name":"Patrick","full_name":"Friedel, Patrick","last_name":"Friedel"},{"first_name":"Christian","full_name":"Horenkamp, Christian","last_name":"Horenkamp"},{"first_name":"Ulrich","full_name":"Köhler, Ulrich","last_name":"Köhler"},{"full_name":"Ober-Blöbaum, Sina","first_name":"Sina","last_name":"Ober-Blöbaum"},{"last_name":"Peitz","full_name":"Peitz, Sebastian","first_name":"Sebastian"},{"first_name":"Sebastian","full_name":"Tiemeyer, Sebastian","last_name":"Tiemeyer"}],"publisher":"Springer International Publishing","department":[{"_id":"27"},{"_id":"101"}],"publication":"Progress in Industrial Mathematics at ECMI","publication_identifier":{"issn":["2212-0173"]},"volume":22,"status":"public","date_created":"2017-07-26T15:25:33Z"},{"type":"conference","year":"2016","citation":{"ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11","apa":"Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11.","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.","bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.","ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016."},"language":[{"iso":"eng"}],"_id":"19","date_updated":"2022-01-06T06:53:56Z","doi":"10.1109/lcn.2016.11","keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. 41st Conference on Local Computer Networks (LCN)","author":[{"id":"24135","last_name":"Lass","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael"},{"last_name":"Leibenger","first_name":"Dominik","full_name":"Leibenger, Dominik"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"publisher":"IEEE","publication_status":"published","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"date_created":"2017-07-25T14:36:16Z","status":"public","abstract":[{"text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments.","lang":"eng"}],"title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","user_id":"24135"},{"user_id":"3145","ddc":["040"],"title":"Reconfigurable Accelerators in the World of General-Purpose Computing","file":[{"file_id":"1545","creator":"florida","file_size":5039555,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-21T12:46:48Z","file_name":"161kenter16_diss_submission_print_16-08-26.pdf","date_created":"2018-03-21T12:46:48Z","access_level":"closed"}],"file_date_updated":"2018-03-21T12:46:48Z","department":[{"_id":"27"},{"_id":"518"}],"author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"}],"publisher":"Universität Paderborn","date_created":"2017-10-17T12:41:23Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"has_accepted_license":"1","status":"public","date_updated":"2022-01-06T06:52:43Z","_id":"161","supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"type":"dissertation","citation":{"chicago":"Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.","apa":"Kenter, T. (2016). Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn.","ama":"Kenter T. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn; 2016.","mla":"Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.","bibtex":"@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016} }","short":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing, Universität Paderborn, 2016.","ieee":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016."},"year":"2016"},{"date_created":"2017-07-26T15:07:06Z","status":"public","publication":"FPGAs for Software Programmers","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"}],"quality_controlled":"1","publisher":"Springer International Publishing","user_id":"15278","abstract":[{"text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.","lang":"eng"}],"page":"227-244","year":"2016","type":"book_chapter","citation":{"ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13"},"_id":"29","project":[{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"editor":[{"last_name":"Koch","first_name":"Dirk","full_name":"Koch, Dirk"},{"last_name":"Hannig","first_name":"Frank","full_name":"Hannig, Frank"},{"first_name":"Daniel","full_name":"Ziener, Daniel","last_name":"Ziener"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"ReconOS","place":"Cham","language":[{"iso":"eng"}],"doi":"10.1007/978-3-319-26408-0_13","date_updated":"2023-09-26T13:25:38Z"},{"_id":"31","date_updated":"2023-09-26T13:25:59Z","language":[{"iso":"eng"}],"year":"2016","type":"conference","citation":{"apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016."},"user_id":"15278","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","ddc":["040"],"date_created":"2017-07-26T15:16:31Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"status":"public","has_accepted_license":"1","file":[{"access_level":"closed","date_created":"2019-01-11T11:56:55Z","file_name":"wrc_upb_polimi_final.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2019-01-11T11:56:55Z","creator":"deffel","file_id":"6626","file_size":394563}],"publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","file_date_updated":"2019-01-11T11:56:55Z","department":[{"_id":"27"},{"_id":"518"}],"quality_controlled":"1","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G.","first_name":"Ettore M. G."},{"first_name":"Gianluca C.","full_name":"Durelli, Gianluca C.","last_name":"Durelli"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}]},{"_id":"24","date_updated":"2023-09-26T13:26:17Z","year":"2016","citation":{"mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","apa":"Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC).","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016."},"type":"conference","language":[{"iso":"eng"}],"title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","ddc":["004"],"user_id":"15278","publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-11-14T12:38:45Z","quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"file":[{"creator":"kenter","file_id":"5602","file_size":129552,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-11-14T12:38:45Z","file_name":"paper_26.pdf","date_created":"2018-11-14T12:38:45Z","access_level":"closed"}],"project":[{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subproject C2"}],"date_created":"2017-07-26T15:00:43Z","status":"public","has_accepted_license":"1"},{"type":"conference","year":"2016","citation":{"apa":"Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC).","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }","mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016.","short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016."},"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:25:17Z","_id":"25","status":"public","date_created":"2017-07-26T15:02:20Z","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"author":[{"last_name":"Lass","id":"24135","first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publication":"Workshop on Approximate Computing (AC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"Using Approximate Computing in Scientific Codes","user_id":"15278"},{"_id":"138","page":"1-5","year":"2016","type":"conference","citation":{"short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545."},"abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-21T13:01:09Z","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","quality_controlled":"1","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Trainiti","first_name":"Ettore M. G. ","full_name":"Trainiti, Ettore M. G. "},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele","first_name":"Emanuele"},{"full_name":"Santambrogio, Marco D. ","first_name":"Marco D. ","last_name":"Santambrogio"},{"full_name":"Bolchini, Christina","first_name":"Christina","last_name":"Bolchini"}],"publisher":"IEEE","file":[{"content_type":"application/pdf","date_updated":"2018-03-21T13:01:09Z","relation":"main_file","success":1,"file_size":184334,"creator":"florida","file_id":"1560","access_level":"closed","date_created":"2018-03-21T13:01:09Z","file_name":"138-07740545.pdf"}],"date_created":"2017-10-17T12:41:18Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:28:11Z","doi":"10.1109/RTSI.2016.7740545","language":[{"iso":"eng"}],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}]},{"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:22Z","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer International Publishing","quality_controlled":"1","file_date_updated":"2018-11-14T13:20:32Z","publication":"Self-aware Computing Systems","file":[{"success":1,"relation":"main_file","date_updated":"2018-11-14T13:20:32Z","content_type":"application/pdf","file_id":"5613","creator":"aloesch","file_size":833054,"access_level":"closed","date_created":"2018-11-14T13:20:32Z","file_name":"chapter8.pdf"}],"_id":"156","type":"book_chapter","year":"2016","citation":{"bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165."},"page":"145-165","title":"Self-aware Compute Nodes","place":"Cham","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"doi":"10.1007/978-3-319-39675-0_8","date_updated":"2023-09-26T13:27:44Z","language":[{"iso":"eng"}],"series_title":"Natural Computing Series (NCS)"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:26:38Z","doi":"10.1016/j.compeleceng.2016.04.021","department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"issn":["0045-7906"]},"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code","page":"91-111","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021."},"type":"journal_article","year":"2016","intvolume":" 55","_id":"165","publication":"Computers and Electrical Engineering","file_date_updated":"2018-03-21T12:45:47Z","quality_controlled":"1","author":[{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"Elsevier","file":[{"date_created":"2018-03-21T12:45:47Z","file_name":"165-1-s2.0-S0045790616301021-main.pdf","access_level":"closed","file_id":"1544","creator":"florida","file_size":3037854,"success":1,"relation":"main_file","date_updated":"2018-03-21T12:45:47Z","content_type":"application/pdf"}],"volume":55,"date_created":"2017-10-17T12:41:24Z","has_accepted_license":"1","status":"public","abstract":[{"text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.","lang":"eng"}],"ddc":["040"],"user_id":"15278"},{"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"user_id":"15278","ddc":["040"],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-21T12:41:55Z","creator":"florida","file_id":"1541","file_size":261356,"access_level":"closed","file_name":"168-07459438.pdf","date_created":"2018-03-21T12:41:55Z"}],"file_date_updated":"2018-03-21T12:41:55Z","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":[{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"EDA Consortium / IEEE","quality_controlled":"1","date_created":"2017-10-17T12:41:24Z","status":"public","has_accepted_license":"1","_id":"168","page":"912-917","year":"2016","type":"conference","citation":{"ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016."}},{"quality_controlled":"1","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publication":"Workshop on Reconfigurable Computing (WRC)","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:39:46Z","file":[{"date_created":"2018-03-21T12:39:46Z","file_name":"171-plessl16_fpl_wrc.pdf","access_level":"closed","creator":"florida","file_id":"1538","file_size":54421,"success":1,"relation":"main_file","date_updated":"2018-03-21T12:39:46Z","content_type":"application/pdf"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:25Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"ddc":["040"],"title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","user_id":"15278","year":"2016","citation":{"bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:27:21Z","_id":"171"},{"type":"journal_article","citation":{"chicago":"Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.","ama":"Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031","apa":"Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K., … Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm - Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031","bibtex":"@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82}, DOI={doi:10.1515/teme-2015-0031}, number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter}, author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer, Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff, Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450} }","mla":"Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50, doi:doi:10.1515/teme-2015-0031.","short":"S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450.","ieee":"S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm - Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015."},"year":"2015","page":"440-450","_id":"1769","date_updated":"2022-01-06T06:53:17Z","intvolume":" 82","doi":"doi:10.1515/teme-2015-0031","issue":"9","author":[{"full_name":"Hegler, Sebastian","first_name":"Sebastian","last_name":"Hegler"},{"last_name":"Statz","first_name":"Christoph","full_name":"Statz, Christoph"},{"first_name":"Marco","full_name":"Mütze, Marco","last_name":"Mütze"},{"first_name":"Hubert","full_name":"Mooshofer, Hubert","last_name":"Mooshofer"},{"full_name":"Goldammer, Matthias","first_name":"Matthias","last_name":"Goldammer"},{"last_name":"Fendt","first_name":"Karl","full_name":"Fendt, Karl"},{"last_name":"Schwarzer","first_name":"Stefan","full_name":"Schwarzer, Stefan"},{"full_name":"Feldhoff, Kim","first_name":"Kim","last_name":"Feldhoff"},{"last_name":"Flehmig","first_name":"Martin","full_name":"Flehmig, Martin"},{"last_name":"Markwardt","first_name":"Ulf","full_name":"Markwardt, Ulf"},{"last_name":"E. Nagel","full_name":"E. Nagel, Wolfgang","first_name":"Wolfgang"},{"first_name":"Maria","full_name":"Schütte, Maria","last_name":"Schütte"},{"last_name":"Walther","first_name":"Andrea","full_name":"Walther, Andrea"},{"first_name":"Michael","full_name":"Meinel, Michael","last_name":"Meinel"},{"full_name":"Basermann, Achim","first_name":"Achim","last_name":"Basermann"},{"first_name":"Dirk","full_name":"Plettemeier, Dirk","last_name":"Plettemeier"}],"publisher":"Walter de Gruyter","publication":"tm - Technisches Messen","department":[{"_id":"27"},{"_id":"104"}],"volume":82,"status":"public","date_created":"2018-03-23T14:01:39Z","abstract":[{"text":"Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.","lang":"eng"}],"title":"Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung","user_id":"24135"},{"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","language":[{"iso":"eng"}],"ddc":["000"],"user_id":"16153","volume":48,"status":"public","has_accepted_license":"1","date_created":"2018-03-23T14:06:12Z","author":[{"full_name":"Torresen, Jim","first_name":"Jim","last_name":"Torresen"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Yao","first_name":"Xin","full_name":"Yao, Xin"}],"publisher":"IEEE Computer Society","file_date_updated":"2018-11-02T15:47:45Z","publication":"IEEE Computer","keyword":["self-awareness","self-expression"],"file":[{"content_type":"application/pdf","date_updated":"2018-11-02T15:47:45Z","success":1,"relation":"main_file","file_size":5605009,"file_id":"5313","creator":"ups","access_level":"closed","date_created":"2018-11-02T15:47:45Z","file_name":"07163237.pdf"}],"issue":"7","_id":"1772","intvolume":" 48","type":"journal_article","year":"2015","citation":{"ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.","mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205"},"page":"18-20"},{"publication_identifier":{"issn":["1617-7061"]},"volume":15,"date_created":"2018-03-23T14:14:24Z","status":"public","publication":"PAMM","department":[{"_id":"27"},{"_id":"101"}],"publisher":"WILEY-VCH Verlag","author":[{"full_name":"Peitz, Sebastian","first_name":"Sebastian","last_name":"Peitz"},{"last_name":"Dellnitz","full_name":"Dellnitz, Michael","first_name":"Michael"}],"title":"Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction","user_id":"24135","abstract":[{"text":"In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100.","lang":"eng"}],"page":"613-614","year":"2015","type":"journal_article","citation":{"ama":"Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296","apa":"Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614. https://doi.org/10.1002/pamm.201510296","chicago":"Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1 (2015): 613–14. https://doi.org/10.1002/pamm.201510296.","mla":"Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no. 1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296.","bibtex":"@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296}, number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian and Dellnitz, Michael}, year={2015}, pages={613–614} }","short":"S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614.","ieee":"S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614, 2015."},"doi":"10.1002/pamm.201510296","issue":"1","_id":"1774","intvolume":" 15","date_updated":"2022-01-06T06:53:19Z"},{"publisher":"Logos Verlag Berlin GmbH","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"}],"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"publication_identifier":{"isbn":["978-3-8325-4155-2"]},"status":"public","date_created":"2019-07-10T09:36:58Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004","_id":"30"}],"place":"Berlin","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","user_id":"3118","citation":{"short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }"},"year":"2015","type":"dissertation","page":"183","supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:48Z","_id":"10624"},{"doi":"10.1155/2015/859425","date_updated":"2023-09-26T13:29:08Z","language":[{"iso":"eng"}],"title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"article_number":"859425","_id":"296","intvolume":" 2015","type":"journal_article","year":"2015","citation":{"mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425","ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425.","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015)."},"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}],"volume":2015,"date_created":"2017-10-17T12:41:49Z","has_accepted_license":"1","status":"public","file_date_updated":"2018-03-20T07:47:56Z","publication":"International Journal of Reconfigurable Computing (IJRC)","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"Hindawi","file":[{"creator":"florida","file_id":"1444","file_size":2993898,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:47:56Z","file_name":"296-859425.pdf","date_created":"2018-03-20T07:47:56Z","access_level":"closed"}]},{"language":[{"iso":"eng"}],"oa":"1","date_updated":"2023-09-26T13:29:59Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","external_id":{"arxiv":["1412.3906"]},"year":"2015","type":"conference","citation":{"chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015."},"_id":"303","date_created":"2017-10-17T12:41:51Z","has_accepted_license":"1","status":"public","file":[{"content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file","file_size":1176620,"creator":"florida","file_id":"1442","access_level":"open_access","date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf"}],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","file_date_updated":"2019-08-01T09:10:44Z","author":[{"full_name":"Damschen, Marvin","first_name":"Marvin","last_name":"Damschen"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}]},{"user_id":"15278","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","quality_controlled":"1","publisher":"ACM","author":[{"last_name":"Schumacher","first_name":"Jörn","full_name":"Schumacher, Jörn"},{"last_name":"T. Anderson","full_name":"T. Anderson, J.","first_name":"J."},{"full_name":"Borga, A.","first_name":"A.","last_name":"Borga"},{"first_name":"H.","full_name":"Boterenbrood, H.","last_name":"Boterenbrood"},{"last_name":"Chen","full_name":"Chen, H.","first_name":"H."},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"full_name":"Drake, G.","first_name":"G.","last_name":"Drake"},{"last_name":"Francis","first_name":"D.","full_name":"Francis, D."},{"first_name":"B.","full_name":"Gorini, B.","last_name":"Gorini"},{"full_name":"Lanni, F.","first_name":"F.","last_name":"Lanni"},{"full_name":"Lehmann-Miotto, Giovanna","first_name":"Giovanna","last_name":"Lehmann-Miotto"},{"last_name":"Levinson","full_name":"Levinson, L.","first_name":"L."},{"first_name":"J.","full_name":"Narevicius, J.","last_name":"Narevicius"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Roich","full_name":"Roich, A.","first_name":"A."},{"last_name":"Ryu","full_name":"Ryu, S.","first_name":"S."},{"full_name":"P. Schreuder, F.","first_name":"F.","last_name":"P. Schreuder"},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"last_name":"Vermeulen","first_name":"J.","full_name":"Vermeulen, J."},{"first_name":"J.","full_name":"Zhang, J.","last_name":"Zhang"}],"publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-03-23T14:09:33Z","date_updated":"2023-09-26T13:31:01Z","_id":"1773","doi":"10.1145/2675743.2771824","language":[{"iso":"eng"}],"year":"2015","citation":{"ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824"},"type":"conference"},{"_id":"1768","date_updated":"2023-09-26T13:30:22Z","issue":"5","doi":"10.1007/s00287-015-0911-z","language":[{"iso":"eng"}],"page":"396-399","year":"2015","citation":{"ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.","short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.","apa":"Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z"},"type":"journal_article","user_id":"15278","title":"Aktuelles Schlagwort: Approximate Computing","keyword":["approximate computing","survey"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"publication":"Informatik Spektrum","publisher":"Springer","quality_controlled":"1","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Schreier, Peter J.","first_name":"Peter J.","last_name":"Schreier"}],"date_created":"2018-03-23T13:58:34Z","status":"public"},{"citation":{"ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124."},"type":"conference","year":"2015","page":"1078-1083","_id":"238","publisher":"EDA Consortium / IEEE","quality_controlled":"1","author":[{"last_name":"Damschen","full_name":"Damschen, Marvin","first_name":"Marvin"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","file_date_updated":"2018-03-21T10:29:49Z","file":[{"file_size":380552,"creator":"florida","file_id":"1500","date_updated":"2018-03-21T10:29:49Z","content_type":"application/pdf","success":1,"relation":"main_file","date_created":"2018-03-21T10:29:49Z","file_name":"238-plessl15_date.pdf","access_level":"closed"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:38Z","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:31:44Z","doi":"10.7873/DATE.2015.1124","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi"},{"abstract":[{"lang":"eng","text":"The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed."}],"title":"FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"publication":"Journal of Physics: Conference Series","author":[{"last_name":"Anderson","first_name":"J","full_name":"Anderson, J"},{"last_name":"Borga","first_name":"A","full_name":"Borga, A"},{"last_name":"Boterenbrood","first_name":"H","full_name":"Boterenbrood, H"},{"full_name":"Chen, H","first_name":"H","last_name":"Chen"},{"last_name":"Chen","full_name":"Chen, K","first_name":"K"},{"last_name":"Drake","full_name":"Drake, G","first_name":"G"},{"first_name":"D","full_name":"Francis, D","last_name":"Francis"},{"last_name":"Gorini","full_name":"Gorini, B","first_name":"B"},{"last_name":"Lanni","first_name":"F","full_name":"Lanni, F"},{"last_name":"Lehmann Miotto","first_name":"G","full_name":"Lehmann Miotto, G"},{"full_name":"Levinson, L","first_name":"L","last_name":"Levinson"},{"last_name":"Narevicius","full_name":"Narevicius, J","first_name":"J"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Roich","full_name":"Roich, A","first_name":"A"},{"last_name":"Ryu","first_name":"S","full_name":"Ryu, S"},{"last_name":"Schreuder","first_name":"F","full_name":"Schreuder, F"},{"last_name":"Schumacher","first_name":"Jörn","full_name":"Schumacher, Jörn"},{"last_name":"Vandelli","full_name":"Vandelli, Wainer","first_name":"Wainer"},{"first_name":"J","full_name":"Vermeulen, J","last_name":"Vermeulen"},{"full_name":"Zhang, J","first_name":"J","last_name":"Zhang"}],"quality_controlled":"1","publisher":"IOP Publishing","volume":664,"date_created":"2018-03-23T14:19:27Z","status":"public","intvolume":" 664","_id":"1775","date_updated":"2023-09-26T13:31:23Z","doi":"10.1088/1742-6596/664/8/082050","article_number":"082050","year":"2015","type":"journal_article","citation":{"bibtex":"@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }","mla":"Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.","apa":"Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050","ama":"Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050","chicago":"Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series 664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.","ieee":"J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.","short":"J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015)."},"language":[{"iso":"eng"}]},{"user_id":"24135","title":"Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres","abstract":[{"lang":"eng","text":"In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment."}],"date_created":"2018-03-26T13:47:16Z","status":"public","publication_identifier":{"isbn":["978-3-319-09063-4"]},"editor":[{"full_name":"Bock, Hans Georg","first_name":"Hans Georg","last_name":"Bock"},{"full_name":"Hoang, Xuan Phu","first_name":"Xuan Phu","last_name":"Hoang"},{"last_name":"Rannacher","first_name":"Rolf","full_name":"Rannacher, Rolf"},{"full_name":"Schlöder, Johannes P.","first_name":"Johannes P.","last_name":"Schlöder"}],"publication":"Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)","department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"publisher":"Springer International Publishing","author":[{"first_name":"Tobias","full_name":"Steinle, Tobias","last_name":"Steinle"},{"full_name":"Vrabec, Jadran","first_name":"Jadran","last_name":"Vrabec"},{"last_name":"Walther","first_name":"Andrea","full_name":"Walther, Andrea"}],"doi":"10.1007/978-3-319-09063-4_19","_id":"1781","date_updated":"2022-01-06T06:53:20Z","page":"233-243","citation":{"chicago":"Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.","apa":"Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19","ama":"Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19","mla":"Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.","bibtex":"@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }","short":"T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.","ieee":"T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243."},"type":"conference","year":"2014"},{"status":"public","date_created":"2018-03-26T13:50:37Z","publisher":"Springer","author":[{"last_name":"Graf","full_name":"Graf, Tobias","first_name":"Tobias"},{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Conf. on Computers and Games (CG)","title":"On Semeai Detection in Monte-Carlo Go","user_id":"24135","place":"Switzerland","citation":{"mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25."},"type":"conference","year":"2014","page":"14-25","series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-09165-5_2","issue":"8427","date_updated":"2022-01-06T06:53:20Z","_id":"1782"},{"date_updated":"2023-09-26T13:32:49Z","language":[{"iso":"ger"}],"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","title":"Verschiebungen an der Grenze zwischen Hardware und Software","place":"Paderborn","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"editor":[{"last_name":"Künsemöller","first_name":"Jörn","full_name":"Künsemöller, Jörn"},{"last_name":"Eke","full_name":"Eke, Norber Otto","first_name":"Norber Otto"},{"first_name":"Lioba","full_name":"Foit, Lioba","last_name":"Foit"},{"last_name":"Kaerlein","first_name":"Timo","full_name":"Kaerlein, Timo"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-7705-5730-1"]},"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"_id":"335","year":"2014","type":"book_chapter","citation":{"mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","apa":"Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Wilhelm Fink.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144."},"page":"123-144","user_id":"15278","ddc":["040"],"abstract":[{"text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.","lang":"eng"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:57Z","file":[{"file_id":"1424","creator":"florida","file_size":2848154,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:29:58Z","date_created":"2018-03-20T07:29:58Z","file_name":"335-2014_plessl_automatismen.pdf","access_level":"closed"}],"publisher":"Wilhelm Fink","author":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publication":"Logiken strukturbildender Prozesse: Automatismen","file_date_updated":"2018-03-20T07:29:58Z"},{"doi":"10.1007/978-3-319-05960-0_13","date_updated":"2023-09-26T13:34:08Z","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science (LNCS)","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","place":"Cham","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"388","intvolume":" 8405","page":"144-155","type":"conference","citation":{"ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13."},"year":"2014","ddc":["040"],"user_id":"15278","abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"volume":8405,"date_created":"2017-10-17T12:42:07Z","has_accepted_license":"1","status":"public","file_date_updated":"2018-03-20T07:02:02Z","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"Springer International Publishing","quality_controlled":"1","file":[{"access_level":"closed","file_name":"388-plessl14_arc.pdf","date_created":"2018-03-20T07:02:02Z","relation":"main_file","success":1,"date_updated":"2018-03-20T07:02:02Z","content_type":"application/pdf","creator":"florida","file_id":"1387","file_size":330193}]},{"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2013.12.001","date_updated":"2023-09-26T13:33:06Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:02Z","volume":38,"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:20:31Z","file_id":"1408","creator":"florida","file_size":1499996,"access_level":"closed","file_name":"363-plessl13_micpro.pdf","date_created":"2018-03-20T07:20:31Z"}],"quality_controlled":"1","publisher":"Elsevier","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Hangmann","first_name":"Hendrik","full_name":"Hangmann, Hendrik"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publication":"Microprocessors and Microsystems","file_date_updated":"2018-03-20T07:20:31Z","user_id":"15278","ddc":["040"],"abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.","lang":"eng"}],"type":"journal_article","citation":{"ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001."},"year":"2014","page":"911-919","issue":"8, Part B","_id":"363","intvolume":" 38"},{"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2014.67","date_updated":"2023-09-26T13:33:50Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","citation":{"apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67."},"type":"conference","year":"2014","page":"222-229","_id":"377","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:05Z","file":[{"content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z","success":1,"relation":"main_file","file_size":1003907,"file_id":"1397","creator":"florida","access_level":"closed","file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z"}],"author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"}],"publisher":"IEEE","quality_controlled":"1","file_date_updated":"2018-03-20T07:14:20Z","keyword":["coldboot"],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}]},{"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","language":[{"iso":"eng"}],"doi":"10.1145/2617596","date_updated":"2023-09-26T13:33:31Z","date_created":"2017-10-17T12:42:03Z","status":"public","has_accepted_license":"1","volume":7,"file":[{"date_created":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf","access_level":"closed","creator":"florida","file_id":"1406","file_size":916052,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:19:19Z"}],"file_date_updated":"2018-03-20T07:19:19Z","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publisher":"ACM","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems."}],"year":"2014","type":"journal_article","citation":{"bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014)."},"issue":"2","article_number":"13","_id":"365","intvolume":" 7"},{"page":"60-71","type":"journal_article","year":"2014","citation":{"short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }"},"intvolume":" 34","_id":"328","issue":"1","file_date_updated":"2018-03-20T07:31:40Z","publication":"IEEE Micro","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Keller","full_name":"Keller, Ariane","first_name":"Ariane"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"IEEE","file":[{"file_id":"1426","creator":"florida","file_size":1877185,"relation":"main_file","success":1,"date_updated":"2018-03-20T07:31:40Z","content_type":"application/pdf","date_created":"2018-03-20T07:31:40Z","file_name":"328-plessl14_micro_01.pdf","access_level":"closed"}],"volume":34,"date_created":"2017-10-17T12:41:55Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:32:31Z","doi":"10.1109/MM.2013.110","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"title":"ReconOS - An Operating System Approach for Reconfigurable Computing"},{"_id":"1778","date_updated":"2023-09-26T13:35:40Z","doi":"10.1109/ISPA.2014.27","language":[{"iso":"eng"}],"year":"2014","type":"conference","citation":{"mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149."},"page":"142-149","user_id":"15278","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","quality_controlled":"1","author":[{"last_name":"C. Durelli","full_name":"C. Durelli, Gianluca","first_name":"Gianluca"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"last_name":"Miele","full_name":"Miele, Antonio","first_name":"Antonio"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"last_name":"D. Santambrogio","full_name":"D. Santambrogio, Marco","first_name":"Marco"},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"publisher":"IEEE","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","status":"public","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2018-03-26T13:40:14Z"},{"date_created":"2017-10-17T12:42:17Z","has_accepted_license":"1","status":"public","file":[{"date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","access_level":"closed","file_size":557362,"file_id":"1353","creator":"florida","date_updated":"2018-03-16T11:29:52Z","content_type":"application/pdf","relation":"main_file","success":1}],"file_date_updated":"2018-03-16T11:29:52Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"page":"1-8","year":"2014","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509"},"type":"conference","_id":"439","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032509","date_updated":"2023-09-26T13:37:02Z"},{"doi":"10.1109/ReConFig.2014.7032535","date_updated":"2023-09-26T13:36:40Z","language":[{"iso":"eng"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"406","page":"1-8","year":"2014","citation":{"short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535."},"type":"conference","ddc":["040"],"user_id":"15278","abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"date_created":"2017-10-17T12:42:11Z","has_accepted_license":"1","status":"public","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:37:42Z","publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","file":[{"access_level":"closed","date_created":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-16T11:37:42Z","file_id":"1366","creator":"florida","file_size":932852}]},{"quality_controlled":"1","author":[{"first_name":"Gianluca","full_name":"C. Durelli, Gianluca","last_name":"C. Durelli"},{"last_name":"Copolla","full_name":"Copolla, Marcello","first_name":"Marcello"},{"last_name":"Djafarian","first_name":"Karim","full_name":"Djafarian, Karim"},{"last_name":"Koranaros","full_name":"Koranaros, George","first_name":"George"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"first_name":"Michele","full_name":"Paolino, Michele","last_name":"Paolino"},{"full_name":"Pell, Oliver","first_name":"Oliver","last_name":"Pell"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"publisher":"Springer","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","status":"public","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"date_created":"2018-03-26T13:45:35Z","title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","citation":{"short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. 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Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.","bibtex":"@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={10.1109/TVLSI.2013.2248069}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }","mla":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.","apa":"Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. 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USENIX Association, 2013.","apa":"Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association.","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.","mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82.","bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }","short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.","ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182."},"type":"conference","year":"2013","page":"175-182","_id":"1793","date_updated":"2022-01-06T06:53:23Z","status":"public","date_created":"2018-03-26T15:16:03Z","publisher":"USENIX Association","author":[{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"full_name":"Süß, Tim","first_name":"Tim","last_name":"Süß"}],"publication":"Proc. USENIX Conference on File and Storage Technologies (FAST)","department":[{"_id":"27"}],"user_id":"24135","title":"File Recipe Compression in Data Deduplication Systems"},{"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","language":[{"iso":"eng"}],"doi":"10.1109/FPT.2013.6718394","date_updated":"2023-09-26T13:37:35Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:35Z","file":[{"file_size":822680,"creator":"florida","file_id":"1294","content_type":"application/pdf","date_updated":"2018-03-15T10:36:08Z","success":1,"relation":"main_file","date_created":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf","access_level":"closed"}],"quality_controlled":"1","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Sorge, Christoph","first_name":"Christoph","last_name":"Sorge"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","file_date_updated":"2018-03-15T10:36:08Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","keyword":["coldboot"],"user_id":"15278","ddc":["040"],"abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"type":"conference","citation":{"ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394."},"year":"2013","page":"386-389","_id":"528"},{"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:38:20Z","doi":"10.1109/ISORC.2013.6913232","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Kling","first_name":"Peter","full_name":"Kling, Peter"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","id":"15523"}],"file":[{"file_id":"1308","creator":"florida","file_size":1040834,"relation":"main_file","success":1,"date_updated":"2018-03-15T13:38:56Z","content_type":"application/pdf","file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z","access_level":"closed"}],"date_created":"2017-10-17T12:42:30Z","has_accepted_license":"1","status":"public","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"ddc":["040"],"user_id":"15278","citation":{"ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232"},"year":"2013","type":"conference","_id":"505"},{"publication_identifier":{"isbn":["978-0-7695-4979-8"]},"date_created":"2018-03-26T14:51:05Z","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"status":"public","publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Suess, Tim","first_name":"Tim","last_name":"Suess"},{"last_name":"Schoenrock","full_name":"Schoenrock, Andrew","first_name":"Andrew"},{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","user_id":"15278","place":"Washington, DC, USA","page":"64-73","year":"2013","citation":{"ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136."},"type":"conference","language":[{"iso":"eng"}],"doi":"10.1109/IPDPSW.2013.136","date_updated":"2023-09-26T13:38:05Z","_id":"1787"},{"abstract":[{"text":"Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations.","lang":"eng"}],"user_id":"15274","title":"Cost-aware and SLO Fulfilling Software as a Service","author":[{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"full_name":"Simon, Jens","first_name":"Jens","id":"15273","last_name":"Simon"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"}],"department":[{"_id":"27"}],"publication":"Journal of Grid Computing","status":"public","date_created":"2018-03-29T11:16:18Z","volume":10,"publication_status":"published","intvolume":" 10","_id":"1965","date_updated":"2022-01-06T06:54:09Z","issue":"3","doi":"10.1007/s10723-012-9230-7","language":[{"iso":"eng"}],"citation":{"ieee":"O. Niehörster, J. Simon, A. Brinkmann, A. Keller, and J. Krüger, “Cost-aware and SLO Fulfilling Software as a Service,” Journal of Grid Computing, vol. 10, no. 3, pp. 553–577, 2012.","short":"O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid Computing 10 (2012) 553–577.","bibtex":"@article{Niehörster_Simon_Brinkmann_Keller_Krüger_2012, title={Cost-aware and SLO Fulfilling Software as a Service}, volume={10}, DOI={10.1007/s10723-012-9230-7}, number={3}, journal={Journal of Grid Computing}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Keller, Axel and Krüger, Jens}, year={2012}, pages={553–577} }","mla":"Niehörster, Oliver, et al. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing, vol. 10, no. 3, 2012, pp. 553–77, doi:10.1007/s10723-012-9230-7.","apa":"Niehörster, O., Simon, J., Brinkmann, A., Keller, A., & Krüger, J. (2012). Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing, 10(3), 553–577. https://doi.org/10.1007/s10723-012-9230-7","ama":"Niehörster O, Simon J, Brinkmann A, Keller A, Krüger J. Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing. 2012;10(3):553-577. doi:10.1007/s10723-012-9230-7","chicago":"Niehörster, Oliver, Jens Simon, André Brinkmann, Axel Keller, and Jens Krüger. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing 10, no. 3 (2012): 553–77. https://doi.org/10.1007/s10723-012-9230-7."},"year":"2012","type":"journal_article","page":"553-577"},{"title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","user_id":"24135","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","status":"public","date_created":"2018-03-29T14:34:48Z","_id":"2097","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/FPT.2012.6412125","year":"2012","type":"conference","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125.","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140."},"page":"135-140"},{"date_updated":"2022-01-06T06:54:42Z","_id":"2098","doi":"10.1109/ICPADS.2012.34","page":"181-188","type":"conference","year":"2012","citation":{"mla":"Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34.","bibtex":"@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }","ama":"Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34","apa":"Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34","chicago":"Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.","ieee":"J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.","short":"J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188."},"title":"ESB: Ext2 Split Block Device","user_id":"24135","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","publisher":"IEEE","author":[{"full_name":"Kaiser, Jürgen","first_name":"Jürgen","last_name":"Kaiser"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"},{"first_name":"Tim","full_name":"Hartung, Tim","last_name":"Hartung"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"date_created":"2018-03-29T14:40:04Z","status":"public"},{"type":"conference","year":"2012","citation":{"ieee":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on Supercomputing (SC), 2012, pp. 7:1-7:11.","short":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11.","mla":"Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14.","bibtex":"@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }","ama":"Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14","apa":"Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14","chicago":"Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14."},"page":"7:1-7:11","doi":"10.1109/SC.2012.14","_id":"2099","date_updated":"2022-01-06T06:54:42Z","status":"public","date_created":"2018-03-29T14:41:55Z","publisher":"IEEE Computer Society","author":[{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Kaiser","full_name":"Kaiser, Jürgen","first_name":"Jürgen"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"full_name":"Kuhn, Michael","first_name":"Michael","last_name":"Kuhn"},{"full_name":"Kunkel, Julian","first_name":"Julian","last_name":"Kunkel"},{"first_name":"Toni","full_name":"Cortes, Toni","last_name":"Cortes"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Supercomputing (SC)","title":"A Study on Data Deduplication in HPC Storage Systems","user_id":"24135","place":"Los Alamitos, CA, USA"},{"citation":{"ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012.","short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012.","apa":"Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG).","ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012."},"year":"2012","type":"conference","_id":"2100","date_updated":"2022-01-06T06:54:42Z","status":"public","date_created":"2018-03-29T14:43:18Z","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","user_id":"24135","title":"FPGA implementation of a second-order convolutive blind signal separation algorithm"},{"citation":{"bibtex":"@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13}, booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel, Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012}, pages={13–17} }","mla":"Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13.","apa":"Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW) (pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13","ama":"Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17. doi:10.1109/SC.Companion.2012.13","chicago":"Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann. “Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop (PDSW), 13–17. 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Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651.","ieee":"S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012.","chicago":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100, no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.","ama":"Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343","apa":"Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. Int. Journal of Electronics, 100(12), 1646–1651. https://doi.org/10.1080/00207217.2012.751343","bibtex":"@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }","mla":"Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no. 12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343."},"user_id":"24135","title":"Parallel algorithm for computation of second-order sequential best rotations","date_created":"2018-04-03T09:05:36Z","status":"public","volume":100,"publication":"Int. Journal of Electronics","department":[{"_id":"27"},{"_id":"78"}],"author":[{"last_name":"Redif","first_name":"Soydan","full_name":"Redif, Soydan"},{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"}],"publisher":"Taylor & Francis"},{"date_created":"2018-04-03T09:08:00Z","status":"public","volume":7,"department":[{"_id":"27"},{"_id":"78"}],"publication":"Journal of Computers","publisher":"Academy Publishers","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"first_name":"Khaled","full_name":"Benkrid, Khaled","last_name":"Benkrid"}],"user_id":"24135","title":"Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer","page":"1312-1328","type":"journal_article","citation":{"mla":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28.","bibtex":"@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }","apa":"Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328.","ama":"Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.","chicago":"Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.","ieee":"S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012.","short":"S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328."},"year":"2012","issue":"6","date_updated":"2022-01-06T06:55:12Z","_id":"2174","intvolume":" 7"},{"volume":175,"date_created":"2018-04-03T09:12:01Z","status":"public","department":[{"_id":"27"}],"publication":"Studies in Health Technology and Informatics","author":[{"last_name":"Herres-Pawlis","first_name":"Sonja","full_name":"Herres-Pawlis, Sonja"},{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"last_name":"Jäkel","first_name":"René","full_name":"Jäkel, René"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"full_name":"Dos Santos Vieira, Ines","first_name":"Ines","last_name":"Dos Santos Vieira"}],"publisher":"IOP Publishing","title":"Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway","user_id":"24135","page":"142-151","type":"journal_article","citation":{"short":"S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, S. Gesing, R. Grunzke, R. Jäkel, O. Kohlbacher, J. Krüger, I. Dos Santos Vieira, Studies in Health Technology and Informatics 175 (2012) 142–151.","ieee":"S. Herres-Pawlis et al., “Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway,” Studies in Health Technology and Informatics, vol. 175, pp. 142–151, 2012.","ama":"Herres-Pawlis S, Birkenheuer G, Brinkmann A, et al. Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway. Studies in Health Technology and Informatics. 2012;175:142-151. doi:10.3233/978-1-61499-054-3-142","apa":"Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Gesing, S., Grunzke, R., Jäkel, R., … Dos Santos Vieira, I. (2012). Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway. Studies in Health Technology and Informatics, 175, 142–151. https://doi.org/10.3233/978-1-61499-054-3-142","chicago":"Herres-Pawlis, Sonja, Georg Birkenheuer, André Brinkmann, Sandra Gesing, Richard Grunzke, René Jäkel, Oliver Kohlbacher, Jens Krüger, and Ines Dos Santos Vieira. “Workflow-Enhanced Conformational Analysis of Guanidine Zinc Complexes via a Science Gateway.” Studies in Health Technology and Informatics 175 (2012): 142–51. https://doi.org/10.3233/978-1-61499-054-3-142.","mla":"Herres-Pawlis, Sonja, et al. “Workflow-Enhanced Conformational Analysis of Guanidine Zinc Complexes via a Science Gateway.” Studies in Health Technology and Informatics, vol. 175, IOP Publishing, 2012, pp. 142–51, doi:10.3233/978-1-61499-054-3-142.","bibtex":"@article{Herres-Pawlis_Birkenheuer_Brinkmann_Gesing_Grunzke_Jäkel_Kohlbacher_Krüger_Dos Santos Vieira_2012, title={Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway}, volume={175}, DOI={10.3233/978-1-61499-054-3-142}, journal={Studies in Health Technology and Informatics}, publisher={IOP Publishing}, author={Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Gesing, Sandra and Grunzke, Richard and Jäkel, René and Kohlbacher, Oliver and Krüger, Jens and Dos Santos Vieira, Ines}, year={2012}, pages={142–151} }"},"year":"2012","doi":"10.3233/978-1-61499-054-3-142","intvolume":" 175","_id":"2176","date_updated":"2022-01-06T06:55:13Z"},{"citation":{"chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050).","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","mla":"Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012.","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.","ieee":"S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050."},"type":"conference","year":"2012","date_updated":"2022-01-06T06:55:13Z","_id":"2178","volume":"PoS(EGICF12-EMITC2)050","date_created":"2018-04-03T09:15:35Z","status":"public","department":[{"_id":"27"}],"publication":"Proceedings of Science","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"last_name":"Herres-Pawlis","first_name":"Sonja","full_name":"Herres-Pawlis, Sonja"},{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Grunzke","first_name":"Richard","full_name":"Grunzke, Richard"},{"last_name":"Kacsuk","first_name":"Peter","full_name":"Kacsuk, Peter"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"},{"first_name":"Miklos","full_name":"Kozlovszky, Miklos","last_name":"Kozlovszky"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph","last_name":"Müller-Pfefferkorn"},{"full_name":"Schäfer, Patrick","first_name":"Patrick","last_name":"Schäfer"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"}],"title":"A Science Gateway Getting Ready for Serving the International Molecular Simulation Community","user_id":"24135"},{"has_accepted_license":"1","status":"public","date_created":"2018-03-29T15:04:25Z","quality_controlled":"1","author":[{"last_name":"Meyer","first_name":"Björn","full_name":"Meyer, Björn"},{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"158","last_name":"Förstner","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens"}],"publisher":"IEEE","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"file_date_updated":"2019-02-13T09:04:46Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"access_level":"closed","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","date_created":"2019-02-13T09:04:46Z","success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-02-13T09:04:46Z","creator":"fossie","file_id":"7638","file_size":2148787}],"ddc":["000"],"user_id":"15278","abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"year":"2012","citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }"},"type":"conference","page":"189-196","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z"},{"language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","publication_identifier":{"issn":["0141-9331"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","page":"110-126","year":"2012","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002."},"type":"journal_article","issue":"2","intvolume":" 36","_id":"2108","volume":36,"date_created":"2018-03-29T15:12:38Z","status":"public","keyword":["funding-altera"],"publication":"Microprocessors and Microsystems","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"15278"},{"file":[{"date_created":"2018-03-15T06:48:32Z","file_name":"615-ReConFig12_01.pdf","access_level":"closed","file_size":730144,"file_id":"1246","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","publisher":"IEEE","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Hangmann","first_name":"Hendrik","full_name":"Hangmann, Hendrik"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:51Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"user_id":"15278","ddc":["040"],"page":"1-8","type":"conference","year":"2012","citation":{"short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }"},"_id":"615","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745"},{"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","language":[{"iso":"eng"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:47Z","quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T08:33:18Z","file":[{"access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z","success":1,"relation":"main_file","date_updated":"2018-03-15T08:33:18Z","content_type":"application/pdf","file_id":"1257","creator":"florida","file_size":371235}],"_id":"591","type":"conference","citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773."},"year":"2012","page":"1-8"},{"abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","date_created":"2018-03-15T08:14:17Z","date_updated":"2018-03-15T08:14:17Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":146789,"creator":"florida","file_id":"1249"}],"file_date_updated":"2018-03-15T08:14:17Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:50Z","has_accepted_license":"1","status":"public","_id":"609","page":"8-9","citation":{"apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9."},"year":"2012","type":"conference","title":"Hardware/Software Platform for Self-aware Compute Nodes","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_updated":"2023-09-26T13:41:36Z","language":[{"iso":"eng"}]},{"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/HPCSim.2012.6266973","date_updated":"2023-09-26T13:42:54Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"date_created":"2017-10-17T12:42:42Z","status":"public","has_accepted_license":"1","file":[{"success":1,"relation":"main_file","date_updated":"2018-03-15T10:20:24Z","content_type":"application/pdf","file_id":"1275","creator":"florida","file_size":288508,"access_level":"closed","file_name":"567-ba-ca-12a.pdf","date_created":"2018-03-15T10:20:24Z"}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","publisher":"IEEE","author":[{"full_name":"Barrio, Pablo","first_name":"Pablo","last_name":"Barrio"},{"full_name":"Carreras, Carlos","first_name":"Carlos","last_name":"Carreras"},{"last_name":"Sierra","first_name":"Roberto","full_name":"Sierra, Roberto"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","_id":"567","page":"559-565","citation":{"short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973."},"type":"conference","year":"2012"},{"citation":{"chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370."},"year":"2012","type":"conference","page":"559-562","_id":"612","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","publisher":"IEEE","author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-03-15T06:49:03Z","file":[{"success":1,"relation":"main_file","date_updated":"2018-03-15T06:49:03Z","content_type":"application/pdf","file_id":"1247","creator":"florida","file_size":202923,"access_level":"closed","file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:42:03Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012."},"year":"2012","_id":"2180","date_updated":"2023-09-26T13:40:17Z","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["funding-enhance"],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","status":"public","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"date_created":"2018-04-03T09:18:33Z","user_id":"15278","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux"},{"citation":{"short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315.","apa":"Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.","bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }"},"type":"journal_article","year":"2012","language":[{"iso":"eng"}],"doi":"10.1155/2012/418315","date_updated":"2023-09-26T13:39:48Z","_id":"2177","date_created":"2018-04-03T09:13:22Z","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Int. Journal of Reconfigurable Computing (IJRC)","publisher":"Hindawi Publishing Corp.","author":[{"full_name":"Grad, Mariusz","first_name":"Mariusz","last_name":"Grad"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","user_id":"15278"},{"_id":"1968","date_updated":"2022-01-06T06:54:10Z","doi":"10.1109/PDP.2011.69","citation":{"chicago":"Kleineweber, Christoph, Axel Keller, Oliver Niehörster, and André Brinkmann. “Rule Based Mapping of Virtual Machines in Clouds.” In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. https://doi.org/10.1109/PDP.2011.69.","ama":"Kleineweber C, Keller A, Niehörster O, Brinkmann A. Rule Based Mapping of Virtual Machines in Clouds. In: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). ; 2011. doi:10.1109/PDP.2011.69","apa":"Kleineweber, C., Keller, A., Niehörster, O., & Brinkmann, A. (2011). Rule Based Mapping of Virtual Machines in Clouds. In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). https://doi.org/10.1109/PDP.2011.69","mla":"Kleineweber, Christoph, et al. “Rule Based Mapping of Virtual Machines in Clouds.” Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011, doi:10.1109/PDP.2011.69.","bibtex":"@inproceedings{Kleineweber_Keller_Niehörster_Brinkmann_2011, title={Rule Based Mapping of Virtual Machines in Clouds}, DOI={10.1109/PDP.2011.69}, booktitle={Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)}, author={Kleineweber, Christoph and Keller, Axel and Niehörster, Oliver and Brinkmann, André}, year={2011} }","short":"C. Kleineweber, A. Keller, O. Niehörster, A. Brinkmann, in: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011.","ieee":"C. Kleineweber, A. Keller, O. Niehörster, and A. Brinkmann, “Rule Based Mapping of Virtual Machines in Clouds,” in Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011."},"year":"2011","type":"conference","language":[{"iso":"eng"}],"abstract":[{"text":"Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments.","lang":"eng"}],"title":"Rule Based Mapping of Virtual Machines in Clouds","user_id":"15274","author":[{"last_name":"Kleineweber","full_name":"Kleineweber, Christoph","first_name":"Christoph"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"last_name":"Niehörster","full_name":"Niehörster, Oliver","first_name":"Oliver"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)","publication_status":"published","status":"public","date_created":"2018-03-29T11:21:05Z"},{"doi":"10.1002/spe.1055","_id":"1971","date_updated":"2022-01-06T06:54:10Z","language":[{"iso":"eng"}],"year":"2011","type":"journal_article","citation":{"mla":"Birkenheuer, Georg, et al. “Virtualized HPC: A Contradiction in Terms?” Software: Practice and Experience, John Wiley & Sons, 2011, doi:10.1002/spe.1055.","bibtex":"@article{Birkenheuer_Brinkmann_Kaiser_Keller_Keller_Kleineweber_Konersmann_Niehörster_Schäfer_Simon_et al._2011, title={Virtualized HPC: a contradiction in terms?}, DOI={10.1002/spe.1055}, journal={Software: Practice and Experience}, publisher={John Wiley & Sons}, author={Birkenheuer, Georg and Brinkmann, André and Kaiser, Jürgen and Keller, Axel and Keller, Matthias and Kleineweber, Christoph and Konersmann, Christoph and Niehörster, Oliver and Schäfer, Thorsten and Simon, Jens and et al.}, year={2011} }","chicago":"Birkenheuer, Georg, André Brinkmann, Jürgen Kaiser, Axel Keller, Matthias Keller, Christoph Kleineweber, Christoph Konersmann, et al. “Virtualized HPC: A Contradiction in Terms?” Software: Practice and Experience, 2011. https://doi.org/10.1002/spe.1055.","ama":"Birkenheuer G, Brinkmann A, Kaiser J, et al. Virtualized HPC: a contradiction in terms? Software: Practice and Experience. 2011. doi:10.1002/spe.1055","apa":"Birkenheuer, G., Brinkmann, A., Kaiser, J., Keller, A., Keller, M., Kleineweber, C., … Wilhelm, M. (2011). Virtualized HPC: a contradiction in terms? Software: Practice and Experience. https://doi.org/10.1002/spe.1055","ieee":"G. Birkenheuer et al., “Virtualized HPC: a contradiction in terms?,” Software: Practice and Experience, 2011.","short":"G. Birkenheuer, A. Brinkmann, J. Kaiser, A. Keller, M. Keller, C. Kleineweber, C. Konersmann, O. Niehörster, T. Schäfer, J. Simon, M. Wilhelm, Software: Practice and Experience (2011)."},"user_id":"15274","title":"Virtualized HPC: a contradiction in terms?","abstract":[{"text":"System virtualization has become the enabling technology to manage the increasing number of different applications inside data centers. The abstraction from the underlying hardware and the provision of multiple virtual machines (VM) on a single physical server have led to a consolidation and more efficient usage of physical servers. The abstraction from the hardware also eases the provision of applications on different data centers, as applied in several cloud computing environments. In this case, the application need not adapt to the environment of the cloud computing provider, but can travel around with its own VM image, including its own operating system and libraries. System virtualization and cloud computing could also be very attractive in the context of high‐performance computing (HPC). Today, HPC centers have to cope with both, the management of the infrastructure and also the applications. Virtualization technology would enable these centers to focus on the infrastructure, while the users, collaborating inside their virtual organizations (VOs), would be able to provide the software. Nevertheless, there seems to be a contradiction between HPC and cloud computing, as there are very few successful approaches to virtualize HPC centers. This work discusses the underlying reasons, including the management and performance, and presents solutions to overcome the contradiction, including a set of new libraries. The viability of the presented approach is shown based on evaluating a selected parallel, scientific application in a virtualized HPC environment. ","lang":"eng"}],"status":"public","date_created":"2018-03-29T11:22:26Z","publication_status":"published","publisher":"John Wiley & Sons","author":[{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Kaiser","full_name":"Kaiser, Jürgen","first_name":"Jürgen"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"last_name":"Keller","full_name":"Keller, Matthias","first_name":"Matthias"},{"last_name":"Kleineweber","full_name":"Kleineweber, Christoph","first_name":"Christoph"},{"first_name":"Christoph","full_name":"Konersmann, Christoph","last_name":"Konersmann"},{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"first_name":"Thorsten","full_name":"Schäfer, Thorsten","last_name":"Schäfer"},{"first_name":"Jens","full_name":"Simon, Jens","last_name":"Simon","id":"15273"},{"first_name":"Maximilan","full_name":"Wilhelm, Maximilan","last_name":"Wilhelm"}],"department":[{"_id":"27"}],"publication":"Software: Practice and Experience"},{"abstract":[{"lang":"eng","text":"We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds."}],"user_id":"15274","title":"An Energy-Aware SaaS Stack","author":[{"full_name":"Niehörster, Oliver","first_name":"Oliver","last_name":"Niehörster"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publication":"Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-29T11:23:22Z","publication_status":"published","date_updated":"2022-01-06T06:54:10Z","_id":"1972","doi":"10.1109/MASCOTS.2011.52","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware SaaS Stack}, DOI={10.1109/MASCOTS.2011.52}, booktitle={Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, author={Niehörster, Oliver and Keller, Axel and Brinkmann, André}, year={2011} }","mla":"Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52.","chicago":"Niehörster, Oliver, Axel Keller, and André Brinkmann. “An Energy-Aware SaaS Stack.” In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011. https://doi.org/10.1109/MASCOTS.2011.52.","apa":"Niehörster, O., Keller, A., & Brinkmann, A. (2011). An Energy-Aware SaaS Stack. In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). https://doi.org/10.1109/MASCOTS.2011.52","ama":"Niehörster O, Keller A, Brinkmann A. An Energy-Aware SaaS Stack. In: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). ; 2011. doi:10.1109/MASCOTS.2011.52","ieee":"O. Niehörster, A. Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,” in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","short":"O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011."},"year":"2011","type":"conference"},{"_id":"2188","date_updated":"2022-01-06T06:55:18Z","doi":"10.1109/HiPC.2011.6152745","citation":{"mla":"Miranda, Alberto, et al. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1–10, doi:10.1109/HiPC.2011.6152745.","bibtex":"@inproceedings{Miranda_Effert_Kang_Miller_Brinkmann_Cortes_2011, place={Washington, DC}, title={Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems}, DOI={10.1109/HiPC.2011.6152745}, booktitle={Proc. Int. Conf. on High Performance Computing (HIPC)}, publisher={IEEE Computer Society}, author={Miranda, Alberto and Effert, Sascha and Kang, Yangwook and Miller, Ethan and Brinkmann, André and Cortes, Toni}, year={2011}, pages={1–10} }","chicago":"Miranda, Alberto, Sascha Effert, Yangwook Kang, Ethan Miller, André Brinkmann, and Toni Cortes. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” In Proc. Int. Conf. on High Performance Computing (HIPC), 1–10. Washington, DC: IEEE Computer Society, 2011. https://doi.org/10.1109/HiPC.2011.6152745.","ama":"Miranda A, Effert S, Kang Y, Miller E, Brinkmann A, Cortes T. Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems. In: Proc. Int. Conf. on High Performance Computing (HIPC). Washington, DC: IEEE Computer Society; 2011:1-10. doi:10.1109/HiPC.2011.6152745","apa":"Miranda, A., Effert, S., Kang, Y., Miller, E., Brinkmann, A., & Cortes, T. (2011). Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems. In Proc. Int. Conf. on High Performance Computing (HIPC) (pp. 1–10). Washington, DC: IEEE Computer Society. https://doi.org/10.1109/HiPC.2011.6152745","ieee":"A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, and T. Cortes, “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems,” in Proc. Int. Conf. on High Performance Computing (HIPC), 2011, pp. 1–10.","short":"A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, T. Cortes, in: Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, Washington, DC, 2011, pp. 1–10."},"year":"2011","type":"conference","page":"1-10","place":"Washington, DC","user_id":"24135","title":"Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems","publisher":"IEEE Computer Society","author":[{"last_name":"Miranda","first_name":"Alberto","full_name":"Miranda, Alberto"},{"full_name":"Effert, Sascha","first_name":"Sascha","last_name":"Effert"},{"last_name":"Kang","first_name":"Yangwook","full_name":"Kang, Yangwook"},{"last_name":"Miller","full_name":"Miller, Ethan","first_name":"Ethan"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"full_name":"Cortes, Toni","first_name":"Toni","last_name":"Cortes"}],"department":[{"_id":"27"}],"publication":"Proc. Int. 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In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2011:380-387. doi:10.1109/ICPADS.2011.77","chicago":"Grawinkel, Matthias, Markus Pargmann, Hubert Dömer, and André Brinkmann. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 380–87. IEEE, 2011. https://doi.org/10.1109/ICPADS.2011.77.","mla":"Grawinkel, Matthias, et al. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–87, doi:10.1109/ICPADS.2011.77.","bibtex":"@inproceedings{Grawinkel_Pargmann_Dömer_Brinkmann_2011, title={Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System}, DOI={10.1109/ICPADS.2011.77}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Grawinkel, Matthias and Pargmann, Markus and Dömer, Hubert and Brinkmann, André}, year={2011}, pages={380–387} }"},"type":"conference","page":"380-387","title":"Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System","user_id":"24135","status":"public","date_created":"2018-04-03T14:32:23Z","author":[{"first_name":"Matthias","full_name":"Grawinkel, Matthias","last_name":"Grawinkel"},{"last_name":"Pargmann","first_name":"Markus","full_name":"Pargmann, Markus"},{"last_name":"Dömer","first_name":"Hubert","full_name":"Dömer, Hubert"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publisher":"IEEE","publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","department":[{"_id":"27"}]},{"place":"Washington DC, USA","user_id":"24135","title":"Autonomic Resource Management Handling Delayed Configuration Effects","author":[{"full_name":"Niehörster, Oliver","first_name":"Oliver","last_name":"Niehörster"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publisher":"IEEE Computer Society","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)","status":"public","date_created":"2018-04-03T14:33:50Z","date_updated":"2022-01-06T06:55:19Z","_id":"2190","doi":"10.1109/CloudCom.2011.28","type":"conference","year":"2011","citation":{"ieee":"O. Niehörster and A. Brinkmann, “Autonomic Resource Management Handling Delayed Configuration Effects,” in Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 2011, pp. 138–145.","short":"O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, Washington DC, USA, 2011, pp. 138–145.","bibtex":"@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28}, booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André}, year={2011}, pages={138–145} }","mla":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28.","ama":"Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed Configuration Effects. In: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom). Washington DC, USA: IEEE Computer Society; 2011:138-145. doi:10.1109/CloudCom.2011.28","apa":"Niehörster, O., & Brinkmann, A. (2011). Autonomic Resource Management Handling Delayed Configuration Effects. In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) (pp. 138–145). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/CloudCom.2011.28","chicago":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 138–45. Washington DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28."},"page":"138-145"},{"user_id":"24135","title":"Estimation and Partitioning for CPU-Accelerator Architectures","publication":"Intel European Research and Innovation Conference","keyword":["funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}],"date_created":"2018-04-03T14:34:57Z","status":"public","_id":"2191","date_updated":"2022-01-06T06:55:19Z","year":"2011","citation":{"bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.","apa":"Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011.","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011."},"type":"conference"},{"citation":{"chicago":"Birkenheuer, Georg, André Brinkmann, Mikael Högqvist, Alexander Papaspyrou, Bernhard Schott, Dietmar Sommerfeld, and Wolfgang Ziegler. “Infrastructure Federation Through Virtualized Delegation of Resources and Services.” Journal of Grid Computing 9, no. 3 (2011): 355–77. https://doi.org/10.1007/s10723-011-9192-1.","ama":"Birkenheuer G, Brinkmann A, Högqvist M, et al. Infrastructure Federation Through Virtualized Delegation of Resources and Services. Journal of Grid Computing. 2011;9(3):355-377. doi:10.1007/s10723-011-9192-1","apa":"Birkenheuer, G., Brinkmann, A., Högqvist, M., Papaspyrou, A., Schott, B., Sommerfeld, D., & Ziegler, W. (2011). Infrastructure Federation Through Virtualized Delegation of Resources and Services. Journal of Grid Computing, 9(3), 355–377. https://doi.org/10.1007/s10723-011-9192-1","bibtex":"@article{Birkenheuer_Brinkmann_Högqvist_Papaspyrou_Schott_Sommerfeld_Ziegler_2011, title={Infrastructure Federation Through Virtualized Delegation of Resources and Services}, volume={9}, DOI={10.1007/s10723-011-9192-1}, number={3}, journal={Journal of Grid Computing}, publisher={Springer}, author={Birkenheuer, Georg and Brinkmann, André and Högqvist, Mikael and Papaspyrou, Alexander and Schott, Bernhard and Sommerfeld, Dietmar and Ziegler, Wolfgang}, year={2011}, pages={355–377} }","mla":"Birkenheuer, Georg, et al. “Infrastructure Federation Through Virtualized Delegation of Resources and Services.” Journal of Grid Computing, vol. 9, no. 3, Springer, 2011, pp. 355–77, doi:10.1007/s10723-011-9192-1.","short":"G. Birkenheuer, A. Brinkmann, M. Högqvist, A. Papaspyrou, B. Schott, D. Sommerfeld, W. Ziegler, Journal of Grid Computing 9 (2011) 355–377.","ieee":"G. Birkenheuer et al., “Infrastructure Federation Through Virtualized Delegation of Resources and Services,” Journal of Grid Computing, vol. 9, no. 3, pp. 355–377, 2011."},"type":"journal_article","year":"2011","page":"355-377","_id":"2192","date_updated":"2022-01-06T06:55:19Z","intvolume":" 9","issue":"3","doi":"10.1007/s10723-011-9192-1","author":[{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"first_name":"Mikael","full_name":"Högqvist, Mikael","last_name":"Högqvist"},{"last_name":"Papaspyrou","first_name":"Alexander","full_name":"Papaspyrou, Alexander"},{"full_name":"Schott, Bernhard","first_name":"Bernhard","last_name":"Schott"},{"first_name":"Dietmar","full_name":"Sommerfeld, Dietmar","last_name":"Sommerfeld"},{"full_name":"Ziegler, Wolfgang","first_name":"Wolfgang","last_name":"Ziegler"}],"publisher":"Springer","department":[{"_id":"27"}],"publication":"Journal of Grid Computing","status":"public","date_created":"2018-04-03T14:36:06Z","volume":9,"user_id":"24135","title":"Infrastructure Federation Through Virtualized Delegation of Resources and Services"},{"user_id":"24135","title":"Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability","publication":"Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)","department":[{"_id":"27"}],"publisher":"IEEE Computer Society","author":[{"last_name":"Grawinkel","first_name":"Matthias","full_name":"Grawinkel, Matthias"},{"last_name":"Schäfer","first_name":"Thorsten","full_name":"Schäfer, Thorsten"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"first_name":"Jens","full_name":"Hagemeyer, Jens","last_name":"Hagemeyer"},{"last_name":"Porrmann","full_name":"Porrmann, Mario","first_name":"Mario"}],"date_created":"2018-04-03T15:01:31Z","status":"public","date_updated":"2022-01-06T06:55:21Z","_id":"2195","doi":"10.1109/mascots.2011.13","page":"297-306","citation":{"mla":"Grawinkel, Matthias, et al. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297–306, doi:10.1109/mascots.2011.13.","bibtex":"@inproceedings{Grawinkel_Schäfer_Brinkmann_Hagemeyer_Porrmann_2011, title={Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability}, DOI={10.1109/mascots.2011.13}, booktitle={Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, publisher={IEEE Computer Society}, author={Grawinkel, Matthias and Schäfer, Thorsten and Brinkmann, André and Hagemeyer, Jens and Porrmann, Mario}, year={2011}, pages={297–306} }","ama":"Grawinkel M, Schäfer T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). 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Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"user_id":"15278","ddc":["040"],"citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. 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As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. 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Cracow Grid Workshop (CGW), 2009, pp. 55–63."},"date_updated":"2022-01-06T06:55:32Z","_id":"2240"},{"_id":"2260","date_updated":"2022-01-06T06:55:37Z","year":"2009","type":"conference","citation":{"chicago":"Birkenheuer, Georg, Arthur Carlson, Alexander Fölling, Mikael Högqvist, Andreas Hoheisel, Alexander Papaspyrou, Klaus Rieger, Bernhard Schott, and Wolfgang Ziegler. “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!” In Proc. Cracow Grid Workshop (CGW), 96–103, 2009.","apa":"Birkenheuer, G., Carlson, A., Fölling, A., Högqvist, M., Hoheisel, A., Papaspyrou, A., … Ziegler, W. (2009). Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! In Proc. Cracow Grid Workshop (CGW) (pp. 96–103).","ama":"Birkenheuer G, Carlson A, Fölling A, et al. Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! In: Proc. Cracow Grid Workshop (CGW). ; 2009:96-103.","bibtex":"@inproceedings{Birkenheuer_Carlson_Fölling_Högqvist_Hoheisel_Papaspyrou_Rieger_Schott_Ziegler_2009, title={Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!}, booktitle={Proc. Cracow Grid Workshop (CGW)}, author={Birkenheuer, Georg and Carlson, Arthur and Fölling, Alexander and Högqvist, Mikael and Hoheisel, Andreas and Papaspyrou, Alexander and Rieger, Klaus and Schott, Bernhard and Ziegler, Wolfgang}, year={2009}, pages={96–103} }","mla":"Birkenheuer, Georg, et al. “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!” Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","short":"G. Birkenheuer, A. Carlson, A. Fölling, M. Högqvist, A. Hoheisel, A. Papaspyrou, K. Rieger, B. Schott, W. Ziegler, in: Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","ieee":"G. Birkenheuer et al., “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!,” in Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103."},"page":"96-103","title":"Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!","user_id":"24135","publication_identifier":{"isbn":["978-83-61433-01-9"]},"status":"public","date_created":"2018-04-06T15:14:46Z","author":[{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Carlson, Arthur","first_name":"Arthur","last_name":"Carlson"},{"full_name":"Fölling, Alexander","first_name":"Alexander","last_name":"Fölling"},{"first_name":"Mikael","full_name":"Högqvist, Mikael","last_name":"Högqvist"},{"full_name":"Hoheisel, Andreas","first_name":"Andreas","last_name":"Hoheisel"},{"full_name":"Papaspyrou, Alexander","first_name":"Alexander","last_name":"Papaspyrou"},{"last_name":"Rieger","full_name":"Rieger, Klaus","first_name":"Klaus"},{"full_name":"Schott, Bernhard","first_name":"Bernhard","last_name":"Schott"},{"last_name":"Ziegler","first_name":"Wolfgang","full_name":"Ziegler, Wolfgang"}],"department":[{"_id":"27"}],"publication":"Proc. Cracow Grid Workshop (CGW)"},{"_id":"2264","date_updated":"2022-01-06T06:55:37Z","doi":"10.1145/1534530.1534541","page":"8:1-8:12","year":"2009","citation":{"bibtex":"@inproceedings{Meister_Brinkmann_2009, place={New York}, title={Multi-Level Comparison of Data Deduplication in a Backup Scenario}, DOI={10.1145/1534530.1534541}, booktitle={Proc. of the Israeli Experimental Systems Conference (SYSTOR)}, publisher={ACM}, author={Meister, Dirk and Brinkmann, André}, year={2009}, pages={8:1-8:12} }","mla":"Meister, Dirk, and André Brinkmann. “Multi-Level Comparison of Data Deduplication in a Backup Scenario.” Proc. of the Israeli Experimental Systems Conference (SYSTOR), ACM, 2009, pp. 8:1-8:12, doi:10.1145/1534530.1534541.","chicago":"Meister, Dirk, and André Brinkmann. “Multi-Level Comparison of Data Deduplication in a Backup Scenario.” In Proc. of the Israeli Experimental Systems Conference (SYSTOR), 8:1-8:12. New York: ACM, 2009. https://doi.org/10.1145/1534530.1534541.","ama":"Meister D, Brinkmann A. Multi-Level Comparison of Data Deduplication in a Backup Scenario. In: Proc. of the Israeli Experimental Systems Conference (SYSTOR). New York: ACM; 2009:8:1-8:12. doi:10.1145/1534530.1534541","apa":"Meister, D., & Brinkmann, A. (2009). Multi-Level Comparison of Data Deduplication in a Backup Scenario. In Proc. of the Israeli Experimental Systems Conference (SYSTOR) (pp. 8:1-8:12). New York: ACM. https://doi.org/10.1145/1534530.1534541","ieee":"D. Meister and A. Brinkmann, “Multi-Level Comparison of Data Deduplication in a Backup Scenario,” in Proc. of the Israeli Experimental Systems Conference (SYSTOR), 2009, pp. 8:1-8:12.","short":"D. Meister, A. Brinkmann, in: Proc. of the Israeli Experimental Systems Conference (SYSTOR), ACM, New York, 2009, pp. 8:1-8:12."},"type":"conference","place":"New York","title":"Multi-Level Comparison of Data Deduplication in a Backup Scenario","user_id":"24135","publication":"Proc. of the Israeli Experimental Systems Conference (SYSTOR)","department":[{"_id":"27"}],"author":[{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publisher":"ACM","date_created":"2018-04-06T15:21:25Z","status":"public"},{"title":"The Gain of Overbooking","user_id":"24135","status":"public","date_created":"2017-11-27T10:22:26Z","author":[{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Brinkmann","first_name":"Andre","full_name":"Brinkmann, Andre"},{"last_name":"Karl","id":"126","first_name":"Holger","full_name":"Karl, Holger"}],"department":[{"_id":"75"},{"_id":"27"}],"publication":"Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers","doi":"10.1007/978-3-642-04633-9_5","date_updated":"2022-01-06T07:03:51Z","_id":"818","year":"2009","citation":{"ieee":"G. Birkenheuer, A. Brinkmann, and H. Karl, “The Gain of Overbooking,” in Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80–100.","short":"G. Birkenheuer, A. Brinkmann, H. Karl, in: Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80–100.","mla":"Birkenheuer, Georg, et al. “The Gain of Overbooking.” Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80–100, doi:10.1007/978-3-642-04633-9_5.","bibtex":"@inproceedings{Birkenheuer_Brinkmann_Karl_2009, title={The Gain of Overbooking}, DOI={10.1007/978-3-642-04633-9_5}, booktitle={Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers}, author={Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}, year={2009}, pages={80–100} }","ama":"Birkenheuer G, Brinkmann A, Karl H. The Gain of Overbooking. In: Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers. ; 2009:80-100. doi:10.1007/978-3-642-04633-9_5","apa":"Birkenheuer, G., Brinkmann, A., & Karl, H. (2009). The Gain of Overbooking. In Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers (pp. 80–100). https://doi.org/10.1007/978-3-642-04633-9_5","chicago":"Birkenheuer, Georg, Andre Brinkmann, and Holger Karl. “The Gain of Overbooking.” In Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 80–100, 2009. https://doi.org/10.1007/978-3-642-04633-9_5."},"type":"conference","page":"80-100"},{"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/FCCM.2009.25","date_updated":"2023-09-26T13:51:44Z","language":[{"iso":"eng"}],"user_id":"15278","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"date_created":"2018-04-16T15:05:52Z","status":"public","keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","publisher":"IEEE Computer Society","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","_id":"2350","page":"275-278","type":"conference","year":"2009","citation":{"mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278."}},{"citation":{"ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009."},"year":"2009","type":"conference","page":"11-18","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:53:11Z","_id":"2262","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","keyword":["EvoCache","evolvable hardware","computer architecture"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-06T15:18:24Z","place":"Los Alamitos, CA, USA","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"title":"EvoCaches: Application-specific Adaptation of Cache Mapping","user_id":"15278"},{"title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","user_id":"15278","extern":"1","place":"Washington, DC, USA","publication_identifier":{"isbn":["978-1-4244-5108-1"]},"status":"public","date_created":"2018-04-16T15:08:07Z","publisher":"IEEE Computer Society","author":[{"full_name":"Beutel, Jan","first_name":"Jan","last_name":"Beutel"},{"last_name":"Gruber","full_name":"Gruber, Stephan","first_name":"Stephan"},{"last_name":"Hasler","full_name":"Hasler, Andi","first_name":"Andi"},{"last_name":"Lim","first_name":"Roman","full_name":"Lim, Roman"},{"last_name":"Meier","first_name":"Andreas","full_name":"Meier, Andreas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Talzi","first_name":"Igor","full_name":"Talzi, Igor"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"},{"first_name":"Christian","full_name":"Tschudin, Christian","last_name":"Tschudin"},{"last_name":"Woehrle","first_name":"Matthias","full_name":"Woehrle, Matthias"},{"last_name":"Yuecel","full_name":"Yuecel, Mustafa","first_name":"Mustafa"}],"quality_controlled":"1","keyword":["WSN","PermaSense"],"publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","department":[{"_id":"27"},{"_id":"518"}],"date_updated":"2023-09-26T13:52:01Z","_id":"2352","citation":{"short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276.","ieee":"J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society; 2009:265-276.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., & Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76."},"year":"2009","type":"conference","page":"265-276","language":[{"iso":"eng"}]},{"place":"Los Alamitos, CA, USA","user_id":"15278","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["IMORC","graphics"],"status":"public","date_created":"2018-04-05T17:11:28Z","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"_id":"2238","date_updated":"2023-09-26T13:52:32Z","doi":"10.1109/ReConFig.2009.32","language":[{"iso":"eng"}],"type":"conference","citation":{"bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124."},"year":"2009","page":"119-124"},{"user_id":"15278","title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE","quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["IMORC","NOC","KNN","accelerator"],"status":"public","date_created":"2018-04-06T15:15:47Z","publication_identifier":{"isbn":["978-1-4244-3892-1"],"issn":["1946-1488"]},"date_updated":"2023-09-26T13:52:52Z","_id":"2261","language":[{"iso":"eng"}],"year":"2009","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344."},"type":"conference","page":"338-344"}]