TY - JOUR AB - The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications AU - Agne, Andreas AU - Happe, Markus AU - Keller, Ariane AU - Lübbers, Enno AU - Plattner, Bernhard AU - Platzner, Marco AU - Plessl, Christian ID - 328 IS - 1 JF - IEEE Micro TI - ReconOS - An Operating System Approach for Reconfigurable Computing VL - 34 ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - JOUR AU - Giefers, Heiner AU - Plessl, Christian AU - Förstner, Jens ID - 1779 IS - 5 JF - ACM SIGARCH Computer Architecture News KW - funding-maxup KW - tet_topic_hpc SN - 0163-5964 TI - Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers VL - 41 ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Gottfried, Viktor AU - Brinkmann, André ID - 1784 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - MCD: Overcoming the Data Download Bottleneck in Data Centers ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Meister, Dirk AU - Nagel, Lars ID - 1788 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Distributing Storage in Cloud Environments ER - TY - BOOK AU - Niehörster, Oliver ID - 1790 SN - 978-3-8440-1735-9 TI - Autonomous Resource Management in Dynamic Data Centers ER - TY - THES AU - Meister, Dirk ID - 1791 TI - Advanced Data Deduplication Techniques and Their Application ER - TY - JOUR AU - Kasap, Server AU - Redif, Soydan ID - 1792 IS - 3 JF - IEEE Trans. on Very Large Scale Integration (VLSI) Systems TI - Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices VL - 22 ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André AU - Süß, Tim ID - 1793 T2 - Proc. USENIX Conference on File and Storage Technologies (FAST) TI - File Recipe Compression in Data Deduplication Systems ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - JOUR AB - Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations. AU - Niehörster, Oliver AU - Simon, Jens AU - Brinkmann, André AU - Keller, Axel AU - Krüger, Jens ID - 1965 IS - 3 JF - Journal of Grid Computing TI - Cost-aware and SLO Fulfilling Software as a Service VL - 10 ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Hartung, Tim AU - Brinkmann, André ID - 2098 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - ESB: Ext2 Split Block Device ER - TY - CONF AU - Meister, Dirk AU - Kaiser, Jürgen AU - Brinkmann, André AU - Kuhn, Michael AU - Kunkel, Julian AU - Cortes, Toni ID - 2099 T2 - Proc. Int. Conf. on Supercomputing (SC) TI - A Study on Data Deduplication in HPC Storage Systems ER -