---
_id: '165'
abstract:
- lang: eng
text: A broad spectrum of applications can be accelerated by offloading computation
intensive parts to reconfigurable hardware. However, to achieve speedups, the
number of loop it- erations (trip count) needs to be sufficiently large to amortize
offloading overheads. Trip counts are frequently not known at compile time, but
only at runtime just before entering a loop. Therefore, we propose to generate
code for both the CPU and the coprocessor, and defer the offloading decision to
the application runtime. We demonstrate how a toolflow, based on the LLVM compiler
framework, can automatically embed dynamic offloading de- cisions into the application
code. We perform in-depth static and dynamic analysis of pop- ular benchmarks,
which confirm the general potential of such an approach. We also pro- pose to
optimize the offloading process by decoupling the runtime decision from the loop
execution (decision slack). The feasibility of our approach is demonstrated by
a toolflow that automatically identifies suitable data-parallel loops and generates
code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow
with representative loops executed for different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding
Dynamic Offloading Decisions into Application Code. Computers and Electrical
Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and
Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers
and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021
bibtex: '@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for
Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021},
journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz,
Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian},
year={2016}, pages={91–111} }'
chicago: 'Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Potential and Methods for Embedding Dynamic Offloading Decisions into Application
Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.'
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for
Embedding Dynamic Offloading Decisions into Application Code,” Computers and
Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.'
mla: Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading
Decisions into Application Code.” Computers and Electrical Engineering,
vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.
short: G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering
55 (2016) 91–111.
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:26:38Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
doi: 10.1016/j.compeleceng.2016.04.021
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:45:47Z
date_updated: 2018-03-21T12:45:47Z
file_id: '1544'
file_name: 165-1-s2.0-S0045790616301021-main.pdf
file_size: 3037854
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:45:47Z
has_accepted_license: '1'
intvolume: ' 55'
language:
- iso: eng
page: 91-111
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Computers and Electrical Engineering
publication_identifier:
issn:
- 0045-7906
publisher: Elsevier
quality_controlled: '1'
status: public
title: Potential and Methods for Embedding Dynamic Offloading Decisions into Application
Code
type: journal_article
user_id: '15278'
volume: 55
year: '2016'
...
---
_id: '168'
abstract:
- lang: eng
text: The use of heterogeneous computing resources, such as Graphic Processing Units
or other specialized coprocessors, has become widespread in recent years because
of their per- formance and energy efficiency advantages. Approaches for managing
and scheduling tasks to heterogeneous resources are still subject to research.
Although queuing systems have recently been extended to support accelerator resources,
a general solution that manages heterogeneous resources at the operating system-
level to exploit a global view of the system state is still missing.In this paper
we present a user space scheduler that enables task scheduling and migration on
heterogeneous processing resources in Linux. Using run queues for available resources
we perform scheduling decisions based on the system state and on task characterization
from earlier measurements. With a pro- gramming pattern that supports the integration
of checkpoints into applications, we preempt tasks and migrate them between three
very different compute resources. Considering static and dynamic workload scenarios,
we show that this approach can gain up to 17% performance, on average 7%, by effectively
avoiding idle resources. We demonstrate that a work-conserving strategy without
migration is no suitable alternative.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling
with task migration for a heterogeneous compute node in the data center. In: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE). EDA Consortium / IEEE; 2016:912-917.'
apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center.
Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 912–917.
bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center},
booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim
and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco},
year={2016}, pages={912–917} }'
chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco
Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous
Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation
& Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium
/ IEEE, 2016.
ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center,”
in Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2016, pp. 912–917.
mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for
a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design,
Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium
/ IEEE, 2016, pp. 912–17.
short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE), EDA Consortium / IEEE, 2016, pp. 912–917.'
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:27:00Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:41:55Z
date_updated: 2018-03-21T12:41:55Z
file_id: '1541'
file_name: 168-07459438.pdf
file_size: 261356
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:41:55Z
has_accepted_license: '1'
language:
- iso: eng
page: 912-917
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Performance-centric scheduling with task migration for a heterogeneous compute
node in the data center
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '171'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application
partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop
on Reconfigurable Computing (WRC). ; 2016.'
apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities
for deferring application partitioning and accelerator synthesis to runtime (extended
abstract). Workshop on Reconfigurable Computing (WRC).
bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for
deferring application partitioning and accelerator synthesis to runtime (extended
abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter,
Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016}
}'
chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl.
“Opportunities for Deferring Application Partitioning and Accelerator Synthesis
to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC),
2016.
ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring
application partitioning and accelerator synthesis to runtime (extended abstract),”
2016.
mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning
and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable
Computing (WRC), 2016.
short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable
Computing (WRC), 2016.'
date_created: 2017-10-17T12:41:25Z
date_updated: 2023-09-26T13:27:21Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:39:46Z
date_updated: 2018-03-21T12:39:46Z
file_id: '1538'
file_name: 171-plessl16_fpl_wrc.pdf
file_size: 54421
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:39:46Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Workshop on Reconfigurable Computing (WRC)
quality_controlled: '1'
status: public
title: Opportunities for deferring application partitioning and accelerator synthesis
to runtime (extended abstract)
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '1769'
abstract:
- lang: eng
text: 'Große zylindrische Stahlprüflinge werden mittels der Methode der finiten
Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ
untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei
Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach
Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.'
author:
- first_name: Sebastian
full_name: Hegler, Sebastian
last_name: Hegler
- first_name: Christoph
full_name: Statz, Christoph
last_name: Statz
- first_name: Marco
full_name: Mütze, Marco
last_name: Mütze
- first_name: Hubert
full_name: Mooshofer, Hubert
last_name: Mooshofer
- first_name: Matthias
full_name: Goldammer, Matthias
last_name: Goldammer
- first_name: Karl
full_name: Fendt, Karl
last_name: Fendt
- first_name: Stefan
full_name: Schwarzer, Stefan
last_name: Schwarzer
- first_name: Kim
full_name: Feldhoff, Kim
last_name: Feldhoff
- first_name: Martin
full_name: Flehmig, Martin
last_name: Flehmig
- first_name: Ulf
full_name: Markwardt, Ulf
last_name: Markwardt
- first_name: Wolfgang
full_name: E. Nagel, Wolfgang
last_name: E. Nagel
- first_name: Maria
full_name: Schütte, Maria
last_name: Schütte
- first_name: Andrea
full_name: Walther, Andrea
last_name: Walther
- first_name: Michael
full_name: Meinel, Michael
last_name: Meinel
- first_name: Achim
full_name: Basermann, Achim
last_name: Basermann
- first_name: Dirk
full_name: Plettemeier, Dirk
last_name: Plettemeier
citation:
ama: Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von
Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte
Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031
apa: Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K.,
… Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm
- Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031
bibtex: '@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et
al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82},
DOI={doi:10.1515/teme-2015-0031},
number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter},
author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer,
Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff,
Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450}
}'
chicago: 'Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias
Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung
von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte
Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.'
ieee: S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm
- Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015.
mla: Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm
- Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50,
doi:doi:10.1515/teme-2015-0031.
short: S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer,
K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M.
Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450.
date_created: 2018-03-23T14:01:39Z
date_updated: 2022-01-06T06:53:17Z
department:
- _id: '27'
- _id: '104'
doi: doi:10.1515/teme-2015-0031
intvolume: ' 82'
issue: '9'
page: 440-450
publication: tm - Technisches Messen
publisher: Walter de Gruyter
status: public
title: Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große
zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung
type: journal_article
user_id: '24135'
volume: 82
year: '2015'
...
---
_id: '1772'
author:
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Xin
full_name: Yao, Xin
last_name: Yao
citation:
ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest
Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20.
https://doi.org/10.1109/MC.2015.205
bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205},
number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen,
Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }'
chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015):
18–20. https://doi.org/10.1109/MC.2015.205.'
ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems
– Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20,
2015.
mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s
Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015,
pp. 18–20, doi:10.1109/MC.2015.205.
short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.
date_created: 2018-03-23T14:06:12Z
date_updated: 2022-01-06T06:53:19Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MC.2015.205
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T15:47:45Z
date_updated: 2018-11-02T15:47:45Z
file_id: '5313'
file_name: 07163237.pdf
file_size: 5605009
relation: main_file
success: 1
file_date_updated: 2018-11-02T15:47:45Z
has_accepted_license: '1'
intvolume: ' 48'
issue: '7'
keyword:
- self-awareness
- self-expression
language:
- iso: eng
page: 18-20
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: IEEE Computer
publisher: IEEE Computer Society
status: public
title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction
type: journal_article
user_id: '16153'
volume: 48
year: '2015'
...
---
_id: '1774'
abstract:
- lang: eng
text: In this article an efficient numerical method to solve multiobjective optimization
problems for fluid flow governed by the Navier Stokes equations is presented.
In order to decrease the computational effort, a reduced order model is introduced
using Proper Orthogonal Decomposition and a corresponding Galerkin Projection.
A global, derivative free multiobjective optimization algorithm is applied to
compute the Pareto set (i.e. the set of optimal compromises) for the concurrent
objectives minimization of flow field fluctuations and control cost. The method
is illustrated for a 2D flow around a cylinder at Re = 100.
author:
- first_name: Sebastian
full_name: Peitz, Sebastian
last_name: Peitz
- first_name: Michael
full_name: Dellnitz, Michael
last_name: Dellnitz
citation:
ama: Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder
Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296
apa: Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow
Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614.
https://doi.org/10.1002/pamm.201510296
bibtex: '@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the
Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296},
number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian
and Dellnitz, Michael}, year={2015}, pages={613–614} }'
chicago: 'Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of
the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1
(2015): 613–14. https://doi.org/10.1002/pamm.201510296.'
ieee: S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around
a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614,
2015.
mla: Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the
Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no.
1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296.
short: S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614.
date_created: 2018-03-23T14:14:24Z
date_updated: 2022-01-06T06:53:19Z
department:
- _id: '27'
- _id: '101'
doi: 10.1002/pamm.201510296
intvolume: ' 15'
issue: '1'
page: 613-614
publication: PAMM
publication_identifier:
issn:
- 1617-7061
publisher: WILEY-VCH Verlag
status: public
title: Multiobjective Optimization of the Flow Around a Cylinder Using Model Order
Reduction
type: journal_article
user_id: '24135'
volume: 15
year: '2015'
...
---
_id: '10624'
abstract:
- lang: eng
text: "The use of heterogeneous computing resources, such as graphics processing
units or other specialized co-processors, has become widespread in recent years
because of their performance and energy efficiency advantages. Operating system
approaches that are limited to optimizing CPU usage are no longer sufficient for
the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling
task preemption on these architectures and migration of tasks between different
resource types at run-time is not only key to improving the performance and energy
consumption but also to enabling automatic scheduling methods for heterogeneous
compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management
of heterogeneous resources and enabling tasks to migrate between diverse hardware.
It provides fundamental work towards future operating systems by discussing implications,
limitations, and chances of the heterogeneity and introducing solutions for energy-
and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous
systems by the use of a centralized scheduler are presented that show benefits
over existing approaches in varying case studies."
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
citation:
ama: 'Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing. Berlin: Logos Verlag Berlin GmbH; 2015.'
apa: 'Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of
Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag
Berlin GmbH}, author={Beisel, Tobias}, year={2015} }'
chicago: 'Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.'
ieee: 'T. Beisel, Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.'
mla: Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous
High-Performance Computing. Logos Verlag Berlin GmbH, 2015.
short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing, Logos Verlag Berlin GmbH, Berlin, 2015.
date_created: 2019-07-10T09:36:58Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
- _id: '27'
- _id: '518'
language:
- iso: eng
page: '183'
place: Berlin
project:
- _id: '30'
grant_number: 01|H11004
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication_identifier:
isbn:
- 978-3-8325-4155-2
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Management and Scheduling of Accelerators for Heterogeneous High-Performance
Computing
type: dissertation
user_id: '3118'
year: '2015'
...
---
_id: '296'
abstract:
- lang: eng
text: FPGAs are known to permit huge gains in performance and efficiency for suitable
applications but still require reduced design efforts and shorter development
cycles for wider adoption. In this work, we compare the resulting performance
of two design concepts that in different ways promise such increased productivity.
As common starting point, we employ a kernel-centric design approach, where computational
hotspots in an application are identified and individually accelerated on FPGA.
By means of a complex stereo matching application, we evaluate two fundamentally
different design philosophies and approaches for implementing the required kernels
on FPGAs. In the first implementation approach, we designed individually specialized
data flow kernels in a spatial programming language for a Maxeler FPGA platform;
in the alternative design approach, we target a vector coprocessor with large
vector lengths, which is implemented as a form of programmable overlay on the
application FPGAs of a Convey HC-1. We assess both approaches in terms of overall
system performance, raw kernel performance, and performance relative to invested
resources. After compensating for the effects of the underlying hardware platforms,
the specialized dataflow kernels on the Maxeler platform are around 3x faster
than kernels executing on the Convey vector coprocessor. In our concrete scenario,
due to trade-offs between reconfiguration overheads and exposed parallelism, the
advantage of specialized dataflow kernels is reduced to around 2.5x.
article_number: '859425'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels
and a Reusable Overlay in a Stereo-Matching Case Study. International Journal
of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International
Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425
bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015},
DOI={10.1155/2015/859425}, number={859425},
journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi},
author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015}
}'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs
between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”
International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized
Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International
Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015,
doi: 10.1155/2015/859425.'
mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and
a Reusable Overlay in a Stereo-Matching Case Study.” International Journal
of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable
Computing (IJRC) 2015 (2015).
date_created: 2017-10-17T12:41:49Z
date_updated: 2023-09-26T13:29:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2015/859425
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:47:56Z
date_updated: 2018-03-20T07:47:56Z
file_id: '1444'
file_name: 296-859425.pdf
file_size: 2993898
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:47:56Z
has_accepted_license: '1'
intvolume: ' 2015'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: International Journal of Reconfigurable Computing (IJRC)
publisher: Hindawi
quality_controlled: '1'
status: public
title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a
Stereo-Matching Case Study
type: journal_article
user_id: '15278'
volume: 2015
year: '2015'
...
---
_id: '303'
abstract:
- lang: eng
text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use
on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling
existentsoftware to automatically utilize accelerators at runtime. BAARis based
on the LLVM Compiler Infrastructure and has aclient-server architecture. The client
runs the program to beaccelerated in an environment which allows program analysisand
profiling. Program parts which are identified as suitable forthe available accelerator
are exported and sent to the server.The server optimizes these program parts for
the acceleratorand provides RPC execution for the client. The client transformsits
program to utilize accelerated execution on the server foroffloaded program parts.
We evaluate our work with a proofof-concept implementation of BAAR that uses an
Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading,
parallelization and vectorization of suitable programparts. The practicality of
BAAR for real-world examples is shownbased on a study of stencil codes. Our results
show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints
over the same code compiled with the Intel Compiler atoptimization level O2 and
running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand
evaluation we outline future directions of research, e.g.,offloading more fine-granular
program parts than functions, amore sophisticated communication mechanism or introducing
onstack-replacement.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on
Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning
Computing Systems (ADAPT). ; 2015.'
apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores. Proceedings of the 5th International Workshop on
Adaptive Self-Tuning Computing Systems (ADAPT).
bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International
Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen,
Marvin and Plessl, Christian}, year={2015} }'
chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores.” In Proceedings of the 5th International
Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration
on Many-Cores,” 2015.
mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores.” Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.'
date_created: 2017-10-17T12:41:51Z
date_updated: 2023-09-26T13:29:59Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
external_id:
arxiv:
- '1412.3906'
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:46:46Z
date_updated: 2019-08-01T09:10:44Z
file_id: '1442'
file_name: 303-plessl15_adapt.pdf
file_size: 1176620
relation: main_file
file_date_updated: 2019-08-01T09:10:44Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning
Computing Systems (ADAPT)
quality_controlled: '1'
status: public
title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1773'
author:
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: J.
full_name: T. Anderson, J.
last_name: T. Anderson
- first_name: A.
full_name: Borga, A.
last_name: Borga
- first_name: H.
full_name: Boterenbrood, H.
last_name: Boterenbrood
- first_name: H.
full_name: Chen, H.
last_name: Chen
- first_name: K.
full_name: Chen, K.
last_name: Chen
- first_name: G.
full_name: Drake, G.
last_name: Drake
- first_name: D.
full_name: Francis, D.
last_name: Francis
- first_name: B.
full_name: Gorini, B.
last_name: Gorini
- first_name: F.
full_name: Lanni, F.
last_name: Lanni
- first_name: Giovanna
full_name: Lehmann-Miotto, Giovanna
last_name: Lehmann-Miotto
- first_name: L.
full_name: Levinson, L.
last_name: Levinson
- first_name: J.
full_name: Narevicius, J.
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A.
full_name: Roich, A.
last_name: Roich
- first_name: S.
full_name: Ryu, S.
last_name: Ryu
- first_name: F.
full_name: P. Schreuder, F.
last_name: P. Schreuder
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J.
full_name: Vermeulen, J.
last_name: Vermeulen
- first_name: J.
full_name: Zhang, J.
last_name: Zhang
citation:
ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015.
doi:10.1145/2675743.2771824'
apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen,
K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson,
L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli,
W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824
bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et
al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project
– Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824},
booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM},
author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H.
and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni,
F. and et al.}, year={2015} }'
chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K.
Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX
Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.
ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in
the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”
2015, doi: 10.1145/2675743.2771824.'
mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS
FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.
short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen,
G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J.
Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen,
J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM,
2015.'
date_created: 2018-03-23T14:09:33Z
date_updated: 2023-09-26T13:31:01Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/2675743.2771824
language:
- iso: eng
publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)
publisher: ACM
quality_controlled: '1'
status: public
title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis
and Optimization of a Memory-Bounded Algorithm
type: conference
user_id: '15278'
year: '2015'
...