--- _id: '46123' article_number: '114513' author: - first_name: Luis full_name: Altenkort, Luis last_name: Altenkort - first_name: Alexander M. full_name: Eller, Alexander M. last_name: Eller - first_name: O. full_name: Kaczmarek, O. last_name: Kaczmarek - first_name: Lukas full_name: Mazur, Lukas id: '90492' last_name: Mazur orcid: ' 0000-0001-6304-7082' - first_name: Guy D. full_name: Moore, Guy D. last_name: Moore - first_name: H.-T. full_name: Shu, H.-T. last_name: Shu citation: ama: 'Altenkort L, Eller AM, Kaczmarek O, Mazur L, Moore GD, Shu H-T. Sphaleron rate from Euclidean lattice correlators: An exploration. Physical Review D. 2021;103(11). doi:10.1103/physrevd.103.114513' apa: 'Altenkort, L., Eller, A. M., Kaczmarek, O., Mazur, L., Moore, G. D., & Shu, H.-T. (2021). Sphaleron rate from Euclidean lattice correlators: An exploration. Physical Review D, 103(11), Article 114513. https://doi.org/10.1103/physrevd.103.114513' bibtex: '@article{Altenkort_Eller_Kaczmarek_Mazur_Moore_Shu_2021, title={Sphaleron rate from Euclidean lattice correlators: An exploration}, volume={103}, DOI={10.1103/physrevd.103.114513}, number={11114513}, journal={Physical Review D}, publisher={American Physical Society (APS)}, author={Altenkort, Luis and Eller, Alexander M. and Kaczmarek, O. and Mazur, Lukas and Moore, Guy D. and Shu, H.-T.}, year={2021} }' chicago: 'Altenkort, Luis, Alexander M. Eller, O. Kaczmarek, Lukas Mazur, Guy D. Moore, and H.-T. Shu. “Sphaleron Rate from Euclidean Lattice Correlators: An Exploration.” Physical Review D 103, no. 11 (2021). https://doi.org/10.1103/physrevd.103.114513.' ieee: 'L. Altenkort, A. M. Eller, O. Kaczmarek, L. Mazur, G. D. Moore, and H.-T. Shu, “Sphaleron rate from Euclidean lattice correlators: An exploration,” Physical Review D, vol. 103, no. 11, Art. no. 114513, 2021, doi: 10.1103/physrevd.103.114513.' mla: 'Altenkort, Luis, et al. “Sphaleron Rate from Euclidean Lattice Correlators: An Exploration.” Physical Review D, vol. 103, no. 11, 114513, American Physical Society (APS), 2021, doi:10.1103/physrevd.103.114513.' short: L. Altenkort, A.M. Eller, O. Kaczmarek, L. Mazur, G.D. Moore, H.-T. Shu, Physical Review D 103 (2021). date_created: 2023-07-24T11:04:17Z date_updated: 2023-07-26T09:22:46Z department: - _id: '27' doi: 10.1103/physrevd.103.114513 extern: '1' intvolume: ' 103' issue: '11' language: - iso: eng publication: Physical Review D publication_identifier: issn: - 2470-0010 - 2470-0029 publication_status: published publisher: American Physical Society (APS) quality_controlled: '1' status: public title: 'Sphaleron rate from Euclidean lattice correlators: An exploration' type: journal_article user_id: '90492' volume: 103 year: '2021' ... --- _id: '46194' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Adesh full_name: Shambhu, Adesh last_name: Shambhu - first_name: Sara full_name: Faghih-Naini, Sara last_name: Faghih-Naini - first_name: Vadym full_name: Aizinger, Vadym last_name: Aizinger citation: ama: 'Kenter T, Shambhu A, Faghih-Naini S, Aizinger V. Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2021. doi:10.1145/3468267.3470617' apa: Kenter, T., Shambhu, A., Faghih-Naini, S., & Aizinger, V. (2021). Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3468267.3470617 bibtex: '@inproceedings{Kenter_Shambhu_Faghih-Naini_Aizinger_2021, title={Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA}, DOI={10.1145/3468267.3470617}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Kenter, Tobias and Shambhu, Adesh and Faghih-Naini, Sara and Aizinger, Vadym}, year={2021} }' chicago: Kenter, Tobias, Adesh Shambhu, Sara Faghih-Naini, and Vadym Aizinger. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2021. https://doi.org/10.1145/3468267.3470617. ieee: 'T. Kenter, A. Shambhu, S. Faghih-Naini, and V. Aizinger, “Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA,” 2021, doi: 10.1145/3468267.3470617.' mla: Kenter, Tobias, et al. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021, doi:10.1145/3468267.3470617. short: 'T. Kenter, A. Shambhu, S. Faghih-Naini, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021.' date_created: 2023-07-28T11:58:14Z date_updated: 2023-07-28T12:03:19Z department: - _id: '27' - _id: '518' doi: 10.1145/3468267.3470617 language: - iso: eng main_file_link: - open_access: '1' url: https://dl.acm.org/doi/pdf/10.1145/3468267.3470617 oa: '1' project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proceedings of the Platform for Advanced Scientific Computing Conference publication_status: published publisher: ACM quality_controlled: '1' status: public title: Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA type: conference user_id: '3145' year: '2021' ... --- _id: '46195' author: - first_name: Martin full_name: Karp, Martin last_name: Karp - first_name: Artur full_name: Podobas, Artur last_name: Podobas - first_name: Niclas full_name: Jansson, Niclas last_name: Jansson - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Philipp full_name: Schlatter, Philipp last_name: Schlatter - first_name: Stefano full_name: Markidis, Stefano last_name: Markidis citation: ama: 'Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116' apa: 'Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116' bibtex: '@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }' chicago: 'Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.' ieee: 'M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.' mla: 'Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.' short: 'M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.' date_created: 2023-07-28T12:04:27Z date_updated: 2023-07-28T12:05:15Z department: - _id: '27' - _id: '518' doi: 10.1109/ipdps49936.2021.00116 language: - iso: eng publication: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) publication_status: published publisher: IEEE quality_controlled: '1' status: public title: 'High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection' type: conference user_id: '3145' year: '2021' ... --- _id: '21587' abstract: - lang: eng text: Solving partial differential equations on unstructured grids is a cornerstone of engineering and scientific computing. Nowadays, heterogeneous parallel platforms with CPUs, GPUs, and FPGAs enable energy-efficient and computationally demanding simulations. We developed the HighPerMeshes C++-embedded Domain-Specific Language (DSL) for bridging the abstraction gap between the mathematical and algorithmic formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different parallel programming and runtime models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPerMeshes DSL, and demonstrate its usage with three examples, a Poisson and monodomain problem, respectively, solved by the continuous finite element method, and the discontinuous Galerkin method for Maxwell’s equation. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. Finally, the achievable performance and scalability are demonstrated for a typical example problem on a multi-core CPU cluster. author: - first_name: Samer full_name: Alhaddad, Samer id: '42456' last_name: Alhaddad - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Stefan full_name: Groth, Stefan last_name: Groth - first_name: Daniel full_name: Grünewald, Daniel last_name: Grünewald - first_name: Yevgen full_name: Grynko, Yevgen id: '26059' last_name: Grynko - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Franz-Josef full_name: Pfreundt, Franz-Josef last_name: Pfreundt - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Merlind full_name: Schotte, Merlind last_name: Schotte - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich - first_name: Martin full_name: Weiser, Martin last_name: Weiser - first_name: Florian full_name: Wende, Florian last_name: Wende citation: ama: 'Alhaddad S, Förstner J, Groth S, et al. HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. In: Euro-Par 2020: Parallel Processing Workshops. ; 2021. doi:10.1007/978-3-030-71593-9_15' apa: 'Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F., Kenter, T., Pfreundt, F.-J., Plessl, C., Schotte, M., Steinke, T., Teich, J., Weiser, M., & Wende, F. (2021). HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. In Euro-Par 2020: Parallel Processing Workshops. https://doi.org/10.1007/978-3-030-71593-9_15' bibtex: '@inbook{Alhaddad_Förstner_Groth_Grünewald_Grynko_Hannig_Kenter_Pfreundt_Plessl_Schotte_et al._2021, place={Cham}, title={HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids}, DOI={10.1007/978-3-030-71593-9_15}, booktitle={Euro-Par 2020: Parallel Processing Workshops}, author={Alhaddad, Samer and Förstner, Jens and Groth, Stefan and Grünewald, Daniel and Grynko, Yevgen and Hannig, Frank and Kenter, Tobias and Pfreundt, Franz-Josef and Plessl, Christian and Schotte, Merlind and et al.}, year={2021} }' chicago: 'Alhaddad, Samer, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, et al. “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids.” In Euro-Par 2020: Parallel Processing Workshops. Cham, 2021. https://doi.org/10.1007/978-3-030-71593-9_15.' ieee: 'S. Alhaddad et al., “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids,” in Euro-Par 2020: Parallel Processing Workshops, Cham, 2021.' mla: 'Alhaddad, Samer, et al. “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids.” Euro-Par 2020: Parallel Processing Workshops, 2021, doi:10.1007/978-3-030-71593-9_15.' short: 'S. Alhaddad, J. Förstner, S. Groth, D. Grünewald, Y. Grynko, F. Hannig, T. Kenter, F.-J. Pfreundt, C. Plessl, M. Schotte, T. Steinke, J. Teich, M. Weiser, F. Wende, in: Euro-Par 2020: Parallel Processing Workshops, Cham, 2021.' date_created: 2021-03-31T19:39:42Z date_updated: 2023-09-26T11:40:25Z ddc: - '004' department: - _id: '61' - _id: '230' - _id: '429' - _id: '27' - _id: '518' doi: 10.1007/978-3-030-71593-9_15 file: - access_level: closed content_type: application/pdf creator: fossie date_created: 2021-03-31T19:42:52Z date_updated: 2021-03-31T19:42:52Z file_id: '21588' file_name: 2021-03 Alhaddad2021_Chapter_HighPerMeshesADomain-SpecificL.pdf file_size: 564398 relation: main_file success: 1 file_date_updated: 2021-03-31T19:42:52Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng place: Cham project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 'Euro-Par 2020: Parallel Processing Workshops' publication_identifier: isbn: - '9783030715922' - '9783030715939' issn: - 0302-9743 - 1611-3349 publication_status: published quality_controlled: '1' status: public title: HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids type: book_chapter user_id: '15278' year: '2021' ... --- _id: '29936' author: - first_name: Arjun full_name: Ramaswami, Arjun id: '49171' last_name: Ramaswami orcid: https://orcid.org/0000-0002-0909-1178 - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Ramaswami A, Kenter T, Kühne T, Plessl C. Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing. In: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing; 2021. doi:10.1007/978-3-030-79025-7_21' apa: Ramaswami, A., Kenter, T., Kühne, T., & Plessl, C. (2021). Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Int. Conf. on Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. https://doi.org/10.1007/978-3-030-79025-7_21 bibtex: '@inbook{Ramaswami_Kenter_Kühne_Plessl_2021, place={Cham}, title={Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing}, DOI={10.1007/978-3-030-79025-7_21}, booktitle={Applied Reconfigurable Computing. Architectures, Tools, and Applications}, publisher={Springer International Publishing}, author={Ramaswami, Arjun and Kenter, Tobias and Kühne, Thomas and Plessl, Christian}, year={2021} }' chicago: 'Ramaswami, Arjun, Tobias Kenter, Thomas Kühne, and Christian Plessl. “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing.” In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Cham: Springer International Publishing, 2021. https://doi.org/10.1007/978-3-030-79025-7_21.' ieee: 'A. Ramaswami, T. Kenter, T. Kühne, and C. Plessl, “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing,” in Applied Reconfigurable Computing. Architectures, Tools, and Applications, Cham: Springer International Publishing, 2021.' mla: Ramaswami, Arjun, et al. “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing.” Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2021, doi:10.1007/978-3-030-79025-7_21. short: 'A. Ramaswami, T. Kenter, T. Kühne, C. Plessl, in: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, Cham, 2021.' conference: name: Int. Conf. on Applied Reconfigurable Computing. Architectures, Tools, and Applications date_created: 2022-02-21T14:22:01Z date_updated: 2023-09-26T11:40:45Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1007/978-3-030-79025-7_21 language: - iso: eng place: Cham publication: Applied Reconfigurable Computing. Architectures, Tools, and Applications publication_identifier: isbn: - '9783030790240' - '9783030790257' issn: - 0302-9743 - 1611-3349 publication_status: published publisher: Springer International Publishing quality_controlled: '1' status: public title: Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing type: book_chapter user_id: '15278' year: '2021' ... --- _id: '24788' author: - first_name: Samer full_name: Alhaddad, Samer id: '42456' last_name: Alhaddad - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Stefan full_name: Groth, Stefan last_name: Groth - first_name: Daniel full_name: Grünewald, Daniel last_name: Grünewald - first_name: Yevgen full_name: Grynko, Yevgen id: '26059' last_name: Grynko - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Franz‐Josef full_name: Pfreundt, Franz‐Josef last_name: Pfreundt - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Merlind full_name: Schotte, Merlind last_name: Schotte - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Jürgen full_name: Teich, Jürgen last_name: Teich - first_name: Martin full_name: Weiser, Martin last_name: Weiser - first_name: Florian full_name: Wende, Florian last_name: Wende citation: ama: 'Alhaddad S, Förstner J, Groth S, et al. The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurrency and Computation: Practice and Experience. Published online 2021:e6616. doi:10.1002/cpe.6616' apa: 'Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F., Kenter, T., Pfreundt, F., Plessl, C., Schotte, M., Steinke, T., Teich, J., Weiser, M., & Wende, F. (2021). The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurrency and Computation: Practice and Experience, e6616. https://doi.org/10.1002/cpe.6616' bibtex: '@article{Alhaddad_Förstner_Groth_Grünewald_Grynko_Hannig_Kenter_Pfreundt_Plessl_Schotte_et al._2021, title={The HighPerMeshes framework for numerical algorithms on unstructured grids}, DOI={10.1002/cpe.6616}, journal={Concurrency and Computation: Practice and Experience}, author={Alhaddad, Samer and Förstner, Jens and Groth, Stefan and Grünewald, Daniel and Grynko, Yevgen and Hannig, Frank and Kenter, Tobias and Pfreundt, Franz‐Josef and Plessl, Christian and Schotte, Merlind and et al.}, year={2021}, pages={e6616} }' chicago: 'Alhaddad, Samer, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, et al. “The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids.” Concurrency and Computation: Practice and Experience, 2021, e6616. https://doi.org/10.1002/cpe.6616.' ieee: 'S. Alhaddad et al., “The HighPerMeshes framework for numerical algorithms on unstructured grids,” Concurrency and Computation: Practice and Experience, p. e6616, 2021, doi: 10.1002/cpe.6616.' mla: 'Alhaddad, Samer, et al. “The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids.” Concurrency and Computation: Practice and Experience, 2021, p. e6616, doi:10.1002/cpe.6616.' short: 'S. Alhaddad, J. Förstner, S. Groth, D. Grünewald, Y. Grynko, F. Hannig, T. Kenter, F. Pfreundt, C. Plessl, M. Schotte, T. Steinke, J. Teich, M. Weiser, F. Wende, Concurrency and Computation: Practice and Experience (2021) e6616.' date_created: 2021-09-22T06:15:50Z date_updated: 2023-09-26T11:42:19Z ddc: - '004' department: - _id: '61' - _id: '230' - _id: '27' - _id: '518' doi: 10.1002/cpe.6616 file: - access_level: open_access content_type: application/pdf creator: fossie date_created: 2021-09-22T06:19:29Z date_updated: 2021-09-22T06:19:29Z file_id: '24789' file_name: 2021-09 Alhaddad - Concurrency... - The HighPerMeshes framework for numerical algorithms on unstructured grids.pdf file_size: 2300152 relation: main_file file_date_updated: 2021-09-22T06:19:29Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng oa: '1' page: e6616 project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing - _id: '33' grant_number: 01|H16005A name: HighPerMeshes publication: 'Concurrency and Computation: Practice and Experience' publication_identifier: issn: - 1532-0626 - 1532-0634 publication_status: published quality_controlled: '1' status: public title: The HighPerMeshes framework for numerical algorithms on unstructured grids type: journal_article user_id: '15278' year: '2021' ... --- _id: '32240' abstract: - lang: eng text:

The effect of traces of ethanol in supercritical carbon dioxide on the mixture's thermodynamic properties is studied by molecular simulations and Taylor dispersion measurements.

author: - first_name: René Spencer full_name: Chatwell, René Spencer last_name: Chatwell - first_name: Gabriela full_name: Guevara-Carrion, Gabriela last_name: Guevara-Carrion - first_name: Yuri full_name: Gaponenko, Yuri last_name: Gaponenko - first_name: Valentina full_name: Shevtsova, Valentina last_name: Shevtsova - first_name: Jadran full_name: Vrabec, Jadran last_name: Vrabec citation: ama: Chatwell RS, Guevara-Carrion G, Gaponenko Y, Shevtsova V, Vrabec J. Diffusion of the carbon dioxide–ethanol mixture in the extended critical region. Physical Chemistry Chemical Physics. 2021;23(4):3106-3115. doi:10.1039/d0cp04985a apa: Chatwell, R. S., Guevara-Carrion, G., Gaponenko, Y., Shevtsova, V., & Vrabec, J. (2021). Diffusion of the carbon dioxide–ethanol mixture in the extended critical region. Physical Chemistry Chemical Physics, 23(4), 3106–3115. https://doi.org/10.1039/d0cp04985a bibtex: '@article{Chatwell_Guevara-Carrion_Gaponenko_Shevtsova_Vrabec_2021, title={Diffusion of the carbon dioxide–ethanol mixture in the extended critical region}, volume={23}, DOI={10.1039/d0cp04985a}, number={4}, journal={Physical Chemistry Chemical Physics}, publisher={Royal Society of Chemistry (RSC)}, author={Chatwell, René Spencer and Guevara-Carrion, Gabriela and Gaponenko, Yuri and Shevtsova, Valentina and Vrabec, Jadran}, year={2021}, pages={3106–3115} }' chicago: 'Chatwell, René Spencer, Gabriela Guevara-Carrion, Yuri Gaponenko, Valentina Shevtsova, and Jadran Vrabec. “Diffusion of the Carbon Dioxide–Ethanol Mixture in the Extended Critical Region.” Physical Chemistry Chemical Physics 23, no. 4 (2021): 3106–15. https://doi.org/10.1039/d0cp04985a.' ieee: 'R. S. Chatwell, G. Guevara-Carrion, Y. Gaponenko, V. Shevtsova, and J. Vrabec, “Diffusion of the carbon dioxide–ethanol mixture in the extended critical region,” Physical Chemistry Chemical Physics, vol. 23, no. 4, pp. 3106–3115, 2021, doi: 10.1039/d0cp04985a.' mla: Chatwell, René Spencer, et al. “Diffusion of the Carbon Dioxide–Ethanol Mixture in the Extended Critical Region.” Physical Chemistry Chemical Physics, vol. 23, no. 4, Royal Society of Chemistry (RSC), 2021, pp. 3106–15, doi:10.1039/d0cp04985a. short: R.S. Chatwell, G. Guevara-Carrion, Y. Gaponenko, V. Shevtsova, J. Vrabec, Physical Chemistry Chemical Physics 23 (2021) 3106–3115. date_created: 2022-06-28T07:23:22Z date_updated: 2023-09-27T10:24:39Z department: - _id: '27' doi: 10.1039/d0cp04985a intvolume: ' 23' issue: '4' keyword: - Physical and Theoretical Chemistry - General Physics and Astronomy language: - iso: eng page: 3106-3115 publication: Physical Chemistry Chemical Physics publication_identifier: issn: - 1463-9076 - 1463-9084 publication_status: published publisher: Royal Society of Chemistry (RSC) quality_controlled: '1' status: public title: Diffusion of the carbon dioxide–ethanol mixture in the extended critical region type: journal_article user_id: '15278' volume: 23 year: '2021' ... --- _id: '29937' author: - first_name: Martin full_name: Karp, Martin last_name: Karp - first_name: Artur full_name: Podobas, Artur last_name: Podobas - first_name: Niclas full_name: Jansson, Niclas last_name: Jansson - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Philipp full_name: Schlatter, Philipp last_name: Schlatter - first_name: Stefano full_name: Markidis, Stefano last_name: Markidis citation: ama: 'Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116' apa: 'Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116' bibtex: '@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }' chicago: 'Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.' ieee: 'M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.' mla: 'Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.' short: 'M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.' date_created: 2022-02-21T14:26:37Z date_updated: 2024-01-22T09:59:13Z department: - _id: '27' - _id: '518' doi: 10.1109/ipdps49936.2021.00116 language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) publication_status: published publisher: IEEE quality_controlled: '1' status: public title: 'High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection' type: conference user_id: '3145' year: '2021' ... --- _id: '18789' author: - first_name: Tobias full_name: Nickchen, Tobias last_name: Nickchen - first_name: Gregor full_name: Engels, Gregor last_name: Engels - first_name: Johannes full_name: Lohn, Johannes last_name: Lohn citation: ama: 'Nickchen T, Engels G, Lohn J. Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain. In: Industrializing Additive Manufacturing. Cham; 2020. doi:10.1007/978-3-030-54334-1_4' apa: Nickchen, T., Engels, G., & Lohn, J. (2020). Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain. In Industrializing Additive Manufacturing. Cham. https://doi.org/10.1007/978-3-030-54334-1_4 bibtex: '@inbook{Nickchen_Engels_Lohn_2020, place={Cham}, title={Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain}, DOI={10.1007/978-3-030-54334-1_4}, booktitle={Industrializing Additive Manufacturing}, author={Nickchen, Tobias and Engels, Gregor and Lohn, Johannes}, year={2020} }' chicago: Nickchen, Tobias, Gregor Engels, and Johannes Lohn. “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain.” In Industrializing Additive Manufacturing. Cham, 2020. https://doi.org/10.1007/978-3-030-54334-1_4. ieee: T. Nickchen, G. Engels, and J. Lohn, “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain,” in Industrializing Additive Manufacturing, Cham, 2020. mla: Nickchen, Tobias, et al. “Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain.” Industrializing Additive Manufacturing, 2020, doi:10.1007/978-3-030-54334-1_4. short: 'T. Nickchen, G. Engels, J. Lohn, in: Industrializing Additive Manufacturing, Cham, 2020.' conference: end_date: 2020-09-03 start_date: 2020-09-01 date_created: 2020-09-01T13:49:42Z date_updated: 2022-01-06T06:53:52Z ddc: - '000' department: - _id: '534' - _id: '624' - _id: '27' - _id: '66' - _id: '219' doi: 10.1007/978-3-030-54334-1_4 language: - iso: eng place: Cham publication: Industrializing Additive Manufacturing publication_identifier: isbn: - '9783030543334' - '9783030543341' publication_status: published status: public title: Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain type: book_chapter user_id: '27340' year: '2020' ... --- _id: '32246' abstract: - lang: eng text:

State-of-the-art methods in materials science such as artificial intelligence and data-driven techniques advance the investigation of photovoltaic materials.

author: - first_name: Hossein full_name: Mirhosseini, Hossein last_name: Mirhosseini - first_name: Ramya full_name: Kormath Madam Raghupathy, Ramya last_name: Kormath Madam Raghupathy - first_name: Sudhir K. full_name: Sahoo, Sudhir K. last_name: Sahoo - first_name: Hendrik full_name: Wiebeler, Hendrik last_name: Wiebeler - first_name: Manjusha full_name: Chugh, Manjusha last_name: Chugh - first_name: Thomas D. full_name: Kühne, Thomas D. last_name: Kühne citation: ama: Mirhosseini H, Kormath Madam Raghupathy R, Sahoo SK, Wiebeler H, Chugh M, Kühne TD. In silico investigation of Cu(In,Ga)Se2-based solar cells. Physical Chemistry Chemical Physics. 2020;22(46):26682-26701. doi:10.1039/d0cp04712k apa: Mirhosseini, H., Kormath Madam Raghupathy, R., Sahoo, S. K., Wiebeler, H., Chugh, M., & Kühne, T. D. (2020). In silico investigation of Cu(In,Ga)Se2-based solar cells. Physical Chemistry Chemical Physics, 22(46), 26682–26701. https://doi.org/10.1039/d0cp04712k bibtex: '@article{Mirhosseini_Kormath Madam Raghupathy_Sahoo_Wiebeler_Chugh_Kühne_2020, title={In silico investigation of Cu(In,Ga)Se2-based solar cells}, volume={22}, DOI={10.1039/d0cp04712k}, number={46}, journal={Physical Chemistry Chemical Physics}, publisher={Royal Society of Chemistry (RSC)}, author={Mirhosseini, Hossein and Kormath Madam Raghupathy, Ramya and Sahoo, Sudhir K. and Wiebeler, Hendrik and Chugh, Manjusha and Kühne, Thomas D.}, year={2020}, pages={26682–26701} }' chicago: 'Mirhosseini, Hossein, Ramya Kormath Madam Raghupathy, Sudhir K. Sahoo, Hendrik Wiebeler, Manjusha Chugh, and Thomas D. Kühne. “In Silico Investigation of Cu(In,Ga)Se2-Based Solar Cells.” Physical Chemistry Chemical Physics 22, no. 46 (2020): 26682–701. https://doi.org/10.1039/d0cp04712k.' ieee: 'H. Mirhosseini, R. Kormath Madam Raghupathy, S. K. Sahoo, H. Wiebeler, M. Chugh, and T. D. Kühne, “In silico investigation of Cu(In,Ga)Se2-based solar cells,” Physical Chemistry Chemical Physics, vol. 22, no. 46, pp. 26682–26701, 2020, doi: 10.1039/d0cp04712k.' mla: Mirhosseini, Hossein, et al. “In Silico Investigation of Cu(In,Ga)Se2-Based Solar Cells.” Physical Chemistry Chemical Physics, vol. 22, no. 46, Royal Society of Chemistry (RSC), 2020, pp. 26682–701, doi:10.1039/d0cp04712k. short: H. Mirhosseini, R. Kormath Madam Raghupathy, S.K. Sahoo, H. Wiebeler, M. Chugh, T.D. Kühne, Physical Chemistry Chemical Physics 22 (2020) 26682–26701. date_created: 2022-06-28T08:02:39Z date_updated: 2022-06-28T08:03:05Z department: - _id: '27' doi: 10.1039/d0cp04712k intvolume: ' 22' issue: '46' keyword: - Physical and Theoretical Chemistry - General Physics and Astronomy language: - iso: eng page: 26682-26701 project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Physical Chemistry Chemical Physics publication_identifier: issn: - 1463-9076 - 1463-9084 publication_status: published publisher: Royal Society of Chemistry (RSC) status: public title: In silico investigation of Cu(In,Ga)Se2-based solar cells type: journal_article user_id: '15278' volume: 22 year: '2020' ... --- _id: '32242' abstract: - lang: eng text: "We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms." author: - first_name: Viktor full_name: Bengs, Viktor last_name: Bengs - first_name: Eyke full_name: Hüllermeier, Eyke last_name: Hüllermeier citation: ama: Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020. apa: Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813. bibtex: '@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }' chicago: Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020. ieee: V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020. mla: Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020. short: V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020). date_created: 2022-06-28T07:26:54Z date_updated: 2022-06-28T07:27:19Z department: - _id: '27' external_id: arxiv: - '2011.00813' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2011.00813 status: public title: Multi-Armed Bandits with Censored Consumption of Resources type: preprint user_id: '15278' year: '2020' ... --- _id: '16277' abstract: - lang: eng text: CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension. article_number: '194103' author: - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Marcella full_name: Iannuzzi, Marcella last_name: Iannuzzi - first_name: Mauro Del full_name: Ben, Mauro Del last_name: Ben - first_name: Vladimir V. full_name: Rybkin, Vladimir V. last_name: Rybkin - first_name: Patrick full_name: Seewald, Patrick last_name: Seewald - first_name: Frederick full_name: Stein, Frederick last_name: Stein - first_name: Teodoro full_name: Laino, Teodoro last_name: Laino - first_name: Rustam Z. full_name: Khaliullin, Rustam Z. last_name: Khaliullin - first_name: Ole full_name: Schütt, Ole last_name: Schütt - first_name: Florian full_name: Schiffmann, Florian last_name: Schiffmann - first_name: Dorothea full_name: Golze, Dorothea last_name: Golze - first_name: Jan full_name: Wilhelm, Jan last_name: Wilhelm - first_name: Sergey full_name: Chulkov, Sergey last_name: Chulkov - first_name: Mohammad Hossein Bani-Hashemian full_name: Mohammad Hossein Bani-Hashemian, Mohammad Hossein Bani-Hashemian last_name: Mohammad Hossein Bani-Hashemian - first_name: Valéry full_name: Weber, Valéry last_name: Weber - first_name: Urban full_name: Borstnik, Urban last_name: Borstnik - first_name: Mathieu full_name: Taillefumier, Mathieu last_name: Taillefumier - first_name: Alice Shoshana full_name: Jakobovits, Alice Shoshana last_name: Jakobovits - first_name: Alfio full_name: Lazzaro, Alfio last_name: Lazzaro - first_name: Hans full_name: Pabst, Hans last_name: Pabst - first_name: Tiziano full_name: Müller, Tiziano last_name: Müller - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Manuel full_name: Guidon, Manuel last_name: Guidon - first_name: Samuel full_name: Andermatt, Samuel last_name: Andermatt - first_name: Nico full_name: Holmberg, Nico last_name: Holmberg - first_name: Gregory K. full_name: Schenter, Gregory K. last_name: Schenter - first_name: Anna full_name: Hehn, Anna last_name: Hehn - first_name: Augustin full_name: Bussy, Augustin last_name: Bussy - first_name: Fabian full_name: Belleflamme, Fabian last_name: Belleflamme - first_name: Gloria full_name: Tabacchi, Gloria last_name: Tabacchi - first_name: Andreas full_name: Glöß, Andreas last_name: Glöß - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Iain full_name: Bethune, Iain last_name: Bethune - first_name: Christopher J. full_name: Mundy, Christopher J. last_name: Mundy - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Matt full_name: Watkins, Matt last_name: Watkins - first_name: Joost full_name: VandeVondele, Joost last_name: VandeVondele - first_name: Matthias full_name: Krack, Matthias last_name: Krack - first_name: Jürg full_name: Hutter, Jürg last_name: Hutter citation: ama: 'Kühne T, Iannuzzi M, Ben MD, et al. CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics. 2020;152(19). doi:10.1063/5.0007045' apa: 'Kühne, T., Iannuzzi, M., Ben, M. D., Rybkin, V. V., Seewald, P., Stein, F., Laino, T., Khaliullin, R. Z., Schütt, O., Schiffmann, F., Golze, D., Wilhelm, J., Chulkov, S., Mohammad Hossein Bani-Hashemian, M. H. B.-H., Weber, V., Borstnik, U., Taillefumier, M., Jakobovits, A. S., Lazzaro, A., … Hutter, J. (2020). CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics, 152(19), Article 194103. https://doi.org/10.1063/5.0007045' bibtex: '@article{Kühne_Iannuzzi_Ben_Rybkin_Seewald_Stein_Laino_Khaliullin_Schütt_Schiffmann_et al._2020, title={CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations}, volume={152}, DOI={10.1063/5.0007045}, number={19194103}, journal={The Journal of Chemical Physics}, author={Kühne, Thomas and Iannuzzi, Marcella and Ben, Mauro Del and Rybkin, Vladimir V. and Seewald, Patrick and Stein, Frederick and Laino, Teodoro and Khaliullin, Rustam Z. and Schütt, Ole and Schiffmann, Florian and et al.}, year={2020} }' chicago: 'Kühne, Thomas, Marcella Iannuzzi, Mauro Del Ben, Vladimir V. Rybkin, Patrick Seewald, Frederick Stein, Teodoro Laino, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics 152, no. 19 (2020). https://doi.org/10.1063/5.0007045.' ieee: 'T. Kühne et al., “CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations,” The Journal of Chemical Physics, vol. 152, no. 19, Art. no. 194103, 2020, doi: 10.1063/5.0007045.' mla: 'Kühne, Thomas, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics, vol. 152, no. 19, 194103, 2020, doi:10.1063/5.0007045.' short: T. Kühne, M. Iannuzzi, M.D. Ben, V.V. Rybkin, P. Seewald, F. Stein, T. Laino, R.Z. Khaliullin, O. Schütt, F. Schiffmann, D. Golze, J. Wilhelm, S. Chulkov, M.H.B.-H. Mohammad Hossein Bani-Hashemian, V. Weber, U. Borstnik, M. Taillefumier, A.S. Jakobovits, A. Lazzaro, H. Pabst, T. Müller, R. Schade, M. Guidon, S. Andermatt, N. Holmberg, G.K. Schenter, A. Hehn, A. Bussy, F. Belleflamme, G. Tabacchi, A. Glöß, M. Lass, I. Bethune, C.J. Mundy, C. Plessl, M. Watkins, J. VandeVondele, M. Krack, J. Hutter, The Journal of Chemical Physics 152 (2020). date_created: 2020-03-10T15:12:31Z date_updated: 2023-08-02T14:56:21Z ddc: - '540' department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1063/5.0007045 external_id: arxiv: - '2003.03868' file: - access_level: closed content_type: application/pdf creator: lass date_created: 2020-05-25T15:21:56Z date_updated: 2020-05-25T15:21:56Z file_id: '17061' file_name: 5.0007045.pdf file_size: 4887650 relation: main_file success: 1 file_date_updated: 2020-05-25T15:21:56Z has_accepted_license: '1' intvolume: ' 152' issue: '19' language: - iso: eng main_file_link: - open_access: '1' url: https://aip.scitation.org/doi/pdf/10.1063/5.0007045?download=true oa: '1' project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: The Journal of Chemical Physics publication_status: published quality_controlled: '1' status: public title: 'CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations' type: journal_article user_id: '75963' volume: 152 year: '2020' ... --- _id: '16898' abstract: - lang: eng text: "Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084' apa: Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084 bibtex: '@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }' chicago: 'Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.' ieee: 'M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.' mla: Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084. short: 'M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.' conference: location: Atlanta, GA, US name: 'SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)' date_created: 2020-04-28T14:44:21Z date_updated: 2023-08-02T14:55:59Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1109/SC41405.2020.00084 external_id: arxiv: - '2004.10811' language: - iso: eng main_file_link: - url: https://ieeexplore.ieee.org/document/9355245 page: 1127-1140 place: Los Alamitos, CA, USA project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC) publisher: IEEE Computer Society quality_controlled: '1' status: public title: A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K type: conference user_id: '75963' year: '2020' ... --- _id: '21632' abstract: - lang: eng text: FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. author: - first_name: Marius full_name: Meyer, Marius id: '40778' last_name: Meyer - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007' apa: Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007 bibtex: '@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }' chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007. ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.' mla: Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007. short: 'M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.' date_created: 2021-04-16T10:17:22Z date_updated: 2023-09-26T11:42:53Z department: - _id: '27' - _id: '518' doi: 10.1109/h2rc51942.2020.00007 keyword: - FPGA - OpenCL - High Level Synthesis - HPC benchmarking language: - iso: eng main_file_link: - url: https://ieeexplore.ieee.org/document/9306963 project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) publication_identifier: isbn: - '9781665415927' publication_status: published quality_controlled: '1' related_material: link: - description: Official repository of the benchmark suite on GitHub relation: supplementary_material url: https://github.com/pc2/HPCC_FPGA status: public title: Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite type: conference user_id: '15278' year: '2020' ... --- _id: '12878' abstract: - lang: eng text: In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation. article_number: '39' author: - first_name: Varadarajan full_name: Rengaraj, Varadarajan last_name: Rengaraj - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne citation: ama: Rengaraj V, Lass M, Plessl C, Kühne T. Accurate Sampling with Noisy Forces from Approximate Computing. Computation. 2020;8(2). doi:10.3390/computation8020039 apa: Rengaraj, V., Lass, M., Plessl, C., & Kühne, T. (2020). Accurate Sampling with Noisy Forces from Approximate Computing. Computation, 8(2), Article 39. https://doi.org/10.3390/computation8020039 bibtex: '@article{Rengaraj_Lass_Plessl_Kühne_2020, title={Accurate Sampling with Noisy Forces from Approximate Computing}, volume={8}, DOI={10.3390/computation8020039}, number={239}, journal={Computation}, publisher={MDPI}, author={Rengaraj, Varadarajan and Lass, Michael and Plessl, Christian and Kühne, Thomas}, year={2020} }' chicago: Rengaraj, Varadarajan, Michael Lass, Christian Plessl, and Thomas Kühne. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation 8, no. 2 (2020). https://doi.org/10.3390/computation8020039. ieee: 'V. Rengaraj, M. Lass, C. Plessl, and T. Kühne, “Accurate Sampling with Noisy Forces from Approximate Computing,” Computation, vol. 8, no. 2, Art. no. 39, 2020, doi: 10.3390/computation8020039.' mla: Rengaraj, Varadarajan, et al. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation, vol. 8, no. 2, 39, MDPI, 2020, doi:10.3390/computation8020039. short: V. Rengaraj, M. Lass, C. Plessl, T. Kühne, Computation 8 (2020). date_created: 2019-07-23T12:03:07Z date_updated: 2023-09-26T11:43:52Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.3390/computation8020039 external_id: arxiv: - '1907.08497' intvolume: ' 8' issue: '2' language: - iso: eng main_file_link: - open_access: '1' url: https://www.mdpi.com/2079-3197/8/2/39/pdf oa: '1' project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing publication: Computation publisher: MDPI quality_controlled: '1' status: public title: Accurate Sampling with Noisy Forces from Approximate Computing type: journal_article user_id: '15278' volume: 8 year: '2020' ... --- _id: '7689' article_type: original author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Riebler H, Vaz GF, Kenter T, Plessl C. Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans Archit Code Optim (TACO). 2019;16(2):14:1–14:26. doi:10.1145/3319423 apa: Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2019). Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans. Archit. Code Optim. (TACO), 16(2), 14:1–14:26. https://doi.org/10.1145/3319423 bibtex: '@article{Riebler_Vaz_Kenter_Plessl_2019, title={Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}, volume={16}, DOI={10.1145/3319423}, number={2}, journal={ACM Trans. Archit. Code Optim. (TACO)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2019}, pages={14:1–14:26} }' chicago: 'Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO) 16, no. 2 (2019): 14:1–14:26. https://doi.org/10.1145/3319423.' ieee: H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019. mla: Riebler, Heinrich, et al. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:10.1145/3319423. short: H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, ACM Trans. Archit. Code Optim. (TACO) 16 (2019) 14:1–14:26. date_created: 2019-02-13T15:01:43Z date_updated: 2022-01-06T07:03:44Z ddc: - '000' department: - _id: '27' - _id: '518' doi: 10.1145/3319423 file: - access_level: closed content_type: application/pdf creator: deffel date_created: 2019-02-13T14:59:07Z date_updated: 2019-02-13T14:59:07Z file_id: '7695' file_name: htrop19_taco.pdf file_size: 872822 relation: main_file file_date_updated: 2019-02-13T14:59:07Z has_accepted_license: '1' intvolume: ' 16' issue: '2' keyword: - htrop language: - iso: eng page: 14:1–14:26 project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 publication: ACM Trans. Archit. Code Optim. (TACO) publication_status: published publisher: ACM quality_controlled: '1' status: public title: Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL type: journal_article user_id: '16153' volume: 16 year: '2019' ... --- _id: '15478' abstract: - lang: eng text: Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS. author: - first_name: Paolo full_name: Gorlani, Paolo id: '72045' last_name: Gorlani - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020' apa: Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020 bibtex: '@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }' chicago: Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020. ieee: P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019. mla: Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020. short: 'P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.' conference: name: International Conference on Field-Programmable Technology (FPT) date_created: 2020-01-09T12:54:48Z date_updated: 2022-01-06T06:52:26Z ddc: - '004' department: - _id: '27' - _id: '518' doi: 10.1109/ICFPT47387.2019.00020 file: - access_level: closed content_type: application/pdf creator: plessl date_created: 2020-01-09T12:53:57Z date_updated: 2020-01-09T12:53:57Z file_id: '15479' file_name: gorlani19_fpt.pdf file_size: 250559 relation: main_file success: 1 file_date_updated: 2020-01-09T12:53:57Z has_accepted_license: '1' language: - iso: eng project: - _id: '33' grant_number: 01|H16005 name: HighPerMeshes - _id: '32' grant_number: PL 595/2-1 name: Performance and Efficiency in HPC with Custom Computing publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) publisher: IEEE quality_controlled: '1' status: public title: OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs type: conference user_id: '3145' year: '2019' ... --- _id: '34167' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler citation: ama: Riebler H. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs.; 2019. doi:10.17619/UNIPB/1-830 apa: Riebler, H. (2019). Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. https://doi.org/10.17619/UNIPB/1-830 bibtex: '@book{Riebler_2019, title={Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs}, DOI={10.17619/UNIPB/1-830}, author={Riebler, Heinrich}, year={2019} }' chicago: Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019. https://doi.org/10.17619/UNIPB/1-830. ieee: H. Riebler, Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. 2019. mla: Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs. 2019, doi:10.17619/UNIPB/1-830. short: H. Riebler, Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019. date_created: 2022-11-30T14:36:04Z date_updated: 2022-11-30T14:44:15Z department: - _id: '27' doi: 10.17619/UNIPB/1-830 language: - iso: eng project: - _id: '1' name: 'SFB 901: SFB 901' - _id: '4' name: 'SFB 901 - C: SFB 901 - Project Area C' - _id: '14' name: 'SFB 901 - C2: SFB 901 - Subproject C2' status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs type: dissertation user_id: '15504' year: '2019' ... --- _id: '21' abstract: - lang: eng text: "We address the general mathematical problem of computing the inverse p-th\r\nroot of a given matrix in an efficient way. A new method to construct iteration\r\nfunctions that allow calculating arbitrary p-th roots and their inverses of\r\nsymmetric positive definite matrices is presented. We show that the order of\r\nconvergence is at least quadratic and that adaptively adjusting a parameter q\r\nalways leads to an even faster convergence. In this way, a better performance\r\nthan with previously known iteration schemes is achieved. The efficiency of the\r\niterative functions is demonstrated for various matrices with different\r\ndensities, condition numbers and spectral radii." author: - first_name: Dorothee full_name: Richters, Dorothee last_name: Richters - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Andrea full_name: Walther, Andrea last_name: Walther - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne citation: ama: Richters D, Lass M, Walther A, Plessl C, Kühne T. A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics. 2019;25(2):564-585. doi:10.4208/cicp.OA-2018-0053 apa: Richters, D., Lass, M., Walther, A., Plessl, C., & Kühne, T. (2019). A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics, 25(2), 564–585. https://doi.org/10.4208/cicp.OA-2018-0053 bibtex: '@article{Richters_Lass_Walther_Plessl_Kühne_2019, title={A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices}, volume={25}, DOI={10.4208/cicp.OA-2018-0053}, number={2}, journal={Communications in Computational Physics}, publisher={Global Science Press}, author={Richters, Dorothee and Lass, Michael and Walther, Andrea and Plessl, Christian and Kühne, Thomas}, year={2019}, pages={564–585} }' chicago: 'Richters, Dorothee, Michael Lass, Andrea Walther, Christian Plessl, and Thomas Kühne. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics 25, no. 2 (2019): 564–85. https://doi.org/10.4208/cicp.OA-2018-0053.' ieee: 'D. Richters, M. Lass, A. Walther, C. Plessl, and T. Kühne, “A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices,” Communications in Computational Physics, vol. 25, no. 2, pp. 564–585, 2019, doi: 10.4208/cicp.OA-2018-0053.' mla: Richters, Dorothee, et al. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics, vol. 25, no. 2, Global Science Press, 2019, pp. 564–85, doi:10.4208/cicp.OA-2018-0053. short: D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics 25 (2019) 564–585. date_created: 2017-07-25T14:48:26Z date_updated: 2023-09-26T11:45:02Z department: - _id: '27' - _id: '518' - _id: '304' - _id: '104' doi: 10.4208/cicp.OA-2018-0053 external_id: arxiv: - '1703.02456' intvolume: ' 25' issue: '2' language: - iso: eng page: 564-585 project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Communications in Computational Physics publisher: Global Science Press quality_controlled: '1' status: public title: A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices type: journal_article user_id: '15278' volume: 25 year: '2019' ... --- _id: '12871' author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w apa: Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik Spektrum. https://doi.org/10.1007/s00287-019-01187-w bibtex: '@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }' chicago: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w. ieee: 'M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.' mla: Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w. short: M. Platzner, C. Plessl, Informatik Spektrum (2019). date_created: 2019-07-22T12:42:44Z date_updated: 2023-09-26T11:45:57Z ddc: - '004' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/s00287-019-01187-w file: - access_level: open_access content_type: application/pdf creator: plessl date_created: 2019-07-22T12:45:02Z date_updated: 2019-07-22T12:45:02Z file_id: '12872' file_name: plessl19_informatik_spektrum.pdf file_size: 248360 relation: main_file file_date_updated: 2019-07-22T12:45:02Z has_accepted_license: '1' language: - iso: ger oa: '1' publication: Informatik Spektrum publication_identifier: issn: - 0170-6012 - 1432-122X publication_status: published quality_controlled: '1' status: public title: FPGAs im Rechenzentrum type: journal_article user_id: '15278' year: '2019' ... --- _id: '20' abstract: - lang: eng text: "Approximate computing has shown to provide new ways to improve performance\r\nand power consumption of error-resilient applications. While many of these\r\napplications can be found in image processing, data classification or machine\r\nlearning, we demonstrate its suitability to a problem from scientific\r\ncomputing. Utilizing the self-correcting behavior of iterative algorithms, we\r\nshow that approximate computing can be applied to the calculation of inverse\r\nmatrix p-th roots which are required in many applications in scientific\r\ncomputing. Results show great opportunities to reduce the computational effort\r\nand bandwidth required for the execution of the discussed algorithm, especially\r\nwhen targeting special accelerator hardware." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Lass M, Kühne T, Plessl C. Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters. 2018;10(2):33-36. doi:10.1109/LES.2017.2760923 apa: Lass, M., Kühne, T., & Plessl, C. (2018). Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters, 10(2), 33–36. https://doi.org/10.1109/LES.2017.2760923 bibtex: '@article{Lass_Kühne_Plessl_2018, title={Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots}, volume={10}, DOI={10.1109/LES.2017.2760923}, number={2}, journal={Embedded Systems Letters}, publisher={IEEE}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2018}, pages={33–36} }' chicago: 'Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters 10, no. 2 (2018): 33–36. https://doi.org/10.1109/LES.2017.2760923.' ieee: M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” Embedded Systems Letters, vol. 10, no. 2, pp. 33–36, 2018. mla: Lass, Michael, et al. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters, vol. 10, no. 2, IEEE, 2018, pp. 33–36, doi:10.1109/LES.2017.2760923. short: M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters 10 (2018) 33–36. date_created: 2017-07-25T14:41:08Z date_updated: 2022-01-06T06:54:18Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1109/LES.2017.2760923 external_id: arxiv: - '1703.02283' intvolume: ' 10' issue: '2' language: - iso: eng page: ' 33-36' project: - _id: '32' grant_number: PL 595/2-1 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Embedded Systems Letters publication_identifier: eissn: - 1943-0671 issn: - 1943-0663 publication_status: published publisher: IEEE status: public title: Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots type: journal_article user_id: '16153' volume: 10 year: '2018' ... --- _id: '22' abstract: - lang: eng text: This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation. author: - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller citation: ama: 'Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8' apa: 'Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8' bibtex: '@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }' chicago: Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8. ieee: A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151. mla: Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8. short: 'A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151.' conference: end_date: 2017-06-02 location: Orlando, FL, USA name: 21st Workshop on Job Scheduling Strategies for Parallel Processing start_date: 2017-06-02 date_created: 2017-07-25T14:54:08Z date_updated: 2022-01-06T06:55:22Z department: - _id: '27' doi: 10.1007/978-3-319-77398-8_8 editor: - first_name: D. full_name: Klusáček, D. last_name: Klusáček - first_name: W. full_name: Cirne, W. last_name: Cirne - first_name: N. full_name: Desai, N. last_name: Desai intvolume: ' 10773' keyword: - Scheduling Planning Mapping Workload management language: - iso: eng page: 132-151 publication: Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) publication_identifier: isbn: - 978-3-319-77398-8 - 978-3-319-77397-1 publication_status: published publisher: Springer series_title: Lecture Notes in Computer Science status: public title: A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems type: conference user_id: '15274' volume: 10773 year: '2018' ... --- _id: '6516' author: - first_name: Jan Cedric full_name: Mertens, Jan Cedric last_name: Mertens - first_name: Alexander full_name: Boschmann, Alexander last_name: Boschmann - first_name: M. full_name: Schmidt, M. last_name: Schmidt - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Mertens JC, Boschmann A, Schmidt M, Plessl C. Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering. 2018;21(4):441-451. doi:10.1007/s12283-018-0291-0 apa: Mertens, J. C., Boschmann, A., Schmidt, M., & Plessl, C. (2018). Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering, 21(4), 441–451. https://doi.org/10.1007/s12283-018-0291-0 bibtex: '@article{Mertens_Boschmann_Schmidt_Plessl_2018, title={Sprint diagnostic with GPS and inertial sensor fusion}, volume={21}, DOI={10.1007/s12283-018-0291-0}, number={4}, journal={Sports Engineering}, publisher={Springer Nature}, author={Mertens, Jan Cedric and Boschmann, Alexander and Schmidt, M. and Plessl, Christian}, year={2018}, pages={441–451} }' chicago: 'Mertens, Jan Cedric, Alexander Boschmann, M. Schmidt, and Christian Plessl. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering 21, no. 4 (2018): 441–51. https://doi.org/10.1007/s12283-018-0291-0.' ieee: J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” Sports Engineering, vol. 21, no. 4, pp. 441–451, 2018. mla: Mertens, Jan Cedric, et al. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering, vol. 21, no. 4, Springer Nature, 2018, pp. 441–51, doi:10.1007/s12283-018-0291-0. short: J.C. Mertens, A. Boschmann, M. Schmidt, C. Plessl, Sports Engineering 21 (2018) 441–451. date_created: 2019-01-08T17:44:43Z date_updated: 2022-01-06T07:03:09Z ddc: - '000' department: - _id: '27' - _id: '518' doi: 10.1007/s12283-018-0291-0 file: - access_level: closed content_type: application/pdf creator: plessl date_created: 2019-01-08T17:47:06Z date_updated: 2019-01-08T17:47:06Z file_id: '6517' file_name: plessl18_sportseng.pdf file_size: 2141021 relation: main_file file_date_updated: 2019-01-08T17:47:06Z has_accepted_license: '1' intvolume: ' 21' issue: '4' language: - iso: eng page: 441-451 publication: Sports Engineering publication_identifier: issn: - 1369-7072 - 1460-2687 publication_status: published publisher: Springer Nature quality_controlled: '1' status: public title: Sprint diagnostic with GPS and inertial sensor fusion type: journal_article user_id: '16153' volume: 21 year: '2018' ... --- _id: '13348' article_number: '146' author: - first_name: Samuel M. H. full_name: Luk, Samuel M. H. last_name: Luk - first_name: P. full_name: Lewandowski, P. last_name: Lewandowski - first_name: N. H. full_name: Kwong, N. H. last_name: Kwong - first_name: E. full_name: Baudin, E. last_name: Baudin - first_name: O. full_name: Lafont, O. last_name: Lafont - first_name: J. full_name: Tignon, J. last_name: Tignon - first_name: P. T. full_name: Leung, P. T. last_name: Leung - first_name: Ch. K. P. full_name: Chan, Ch. K. P. last_name: Chan - first_name: M. full_name: Babilon, M. last_name: Babilon - first_name: Stefan full_name: Schumacher, Stefan id: '27271' last_name: Schumacher orcid: 0000-0003-4042-4951 - first_name: R. full_name: Binder, R. last_name: Binder citation: ama: Luk SMH, Lewandowski P, Kwong NH, et al. Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities. Journal of the Optical Society of America B. 2018;35(1). doi:10.1364/josab.35.000146 apa: Luk, S. M. H., Lewandowski, P., Kwong, N. H., Baudin, E., Lafont, O., Tignon, J., Leung, P. T., Chan, Ch. K. P., Babilon, M., Schumacher, S., & Binder, R. (2018). Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities. Journal of the Optical Society of America B, 35(1), Article 146. https://doi.org/10.1364/josab.35.000146 bibtex: '@article{Luk_Lewandowski_Kwong_Baudin_Lafont_Tignon_Leung_Chan_Babilon_Schumacher_et al._2018, title={Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities}, volume={35}, DOI={10.1364/josab.35.000146}, number={1146}, journal={Journal of the Optical Society of America B}, author={Luk, Samuel M. H. and Lewandowski, P. and Kwong, N. H. and Baudin, E. and Lafont, O. and Tignon, J. and Leung, P. T. and Chan, Ch. K. P. and Babilon, M. and Schumacher, Stefan and et al.}, year={2018} }' chicago: Luk, Samuel M. H., P. Lewandowski, N. H. Kwong, E. Baudin, O. Lafont, J. Tignon, P. T. Leung, et al. “Theory of Optically Controlled Anisotropic Polariton Transport in Semiconductor Double Microcavities.” Journal of the Optical Society of America B 35, no. 1 (2018). https://doi.org/10.1364/josab.35.000146. ieee: 'S. M. H. Luk et al., “Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities,” Journal of the Optical Society of America B, vol. 35, no. 1, Art. no. 146, 2018, doi: 10.1364/josab.35.000146.' mla: Luk, Samuel M. H., et al. “Theory of Optically Controlled Anisotropic Polariton Transport in Semiconductor Double Microcavities.” Journal of the Optical Society of America B, vol. 35, no. 1, 146, 2018, doi:10.1364/josab.35.000146. short: S.M.H. Luk, P. Lewandowski, N.H. Kwong, E. Baudin, O. Lafont, J. Tignon, P.T. Leung, Ch.K.P. Chan, M. Babilon, S. Schumacher, R. Binder, Journal of the Optical Society of America B 35 (2018). date_created: 2019-09-19T13:50:06Z date_updated: 2023-02-10T15:02:47Z department: - _id: '15' - _id: '170' - _id: '297' - _id: '230' - _id: '429' - _id: '27' doi: 10.1364/josab.35.000146 intvolume: ' 35' issue: '1' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Journal of the Optical Society of America B publication_identifier: issn: - 0740-3224 - 1520-8540 publication_status: published status: public title: Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities type: journal_article user_id: '14931' volume: 35 year: '2018' ... --- _id: '1588' abstract: - lang: eng text: The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gopinath full_name: Mahale, Gopinath last_name: Mahale - first_name: Samer full_name: Alhaddad, Samer id: '42456' last_name: Alhaddad - first_name: Yevgen full_name: Grynko, Yevgen id: '26059' last_name: Grynko - first_name: Christian full_name: Schmitt, Christian last_name: Schmitt - first_name: Ayesha full_name: Afzal, Ayesha last_name: Afzal - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037' apa: Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037 bibtex: '@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }' chicago: Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037. ieee: 'T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.' mla: Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037. short: 'T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.' conference: name: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) date_created: 2018-03-22T10:48:01Z date_updated: 2023-09-26T11:47:52Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '61' doi: 10.1109/FCCM.2018.00037 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T14:45:05Z date_updated: 2018-11-02T14:45:05Z file_id: '5282' file_name: 08457652.pdf file_size: 269130 relation: main_file success: 1 file_date_updated: 2018-11-02T14:45:05Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng project: - _id: '33' grant_number: 01|H16005A name: HighPerMeshes - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) publisher: IEEE quality_controlled: '1' status: public title: OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes type: conference user_id: '15278' year: '2018' ... --- _id: '1590' abstract: - lang: eng text: "We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Stephan full_name: Mohr, Stephan last_name: Mohr - first_name: Hendrik full_name: Wiebeler, Hendrik last_name: Wiebeler - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231' apa: Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231 bibtex: '@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }' chicago: 'Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.' ieee: 'M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.' mla: Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231. short: 'M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.' conference: end_date: 2018-07-04 location: Basel, Switzerland name: Platform for Advanced Scientific Computing Conference (PASC) start_date: 2018-07-02 date_created: 2018-03-22T10:53:01Z date_updated: 2023-09-26T11:48:12Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1145/3218176.3218231 external_id: arxiv: - '1710.10899' keyword: - approximate computing - linear algebra - matrix inversion - matrix p-th roots - numeric algorithm - parallel computing language: - iso: eng place: New York, NY, USA project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proc. Platform for Advanced Scientific Computing (PASC) Conference publication_identifier: isbn: - 978-1-4503-5891-0/18/07 publisher: ACM quality_controlled: '1' status: public title: A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices type: conference user_id: '15278' year: '2018' ... --- _id: '1204' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534' apa: Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534 bibtex: '@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534. ieee: 'H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.' mla: Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534. short: 'H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.' date_created: 2018-03-08T14:45:18Z date_updated: 2023-09-26T11:47:23Z ddc: - '000' department: - _id: '27' - _id: '518' doi: 10.1145/3178487.3178534 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T14:43:37Z date_updated: 2018-11-02T14:43:37Z file_id: '5281' file_name: p417-riebler.pdf file_size: 447769 relation: main_file success: 1 file_date_updated: 2018-11-02T14:43:37Z has_accepted_license: '1' keyword: - htrop language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) publication_identifier: isbn: - '9781450349826' publication_status: published publisher: ACM quality_controlled: '1' status: public title: Automated Code Acceleration Targeting Heterogeneous OpenCL Devices type: conference user_id: '15278' year: '2018' ... --- _id: '18' abstract: - lang: eng text: "Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis." author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Robert full_name: Mittendorf, Robert last_name: Mittendorf - first_name: Thomas full_name: Löcke, Thomas last_name: Löcke - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687 apa: Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23. https://doi.org/10.1145/3053687 bibtex: '@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={10.1145/3053687}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }' chicago: 'Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.' ieee: 'H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi: 10.1145/3053687.' mla: Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687. short: H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23. date_created: 2017-07-25T14:17:32Z date_updated: 2023-09-26T13:23:58Z ddc: - '000' department: - _id: '27' - _id: '518' doi: 10.1145/3053687 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T16:04:14Z date_updated: 2018-11-02T16:04:14Z file_id: '5322' file_name: a24-riebler.pdf file_size: 2131617 relation: main_file success: 1 file_date_updated: 2018-11-02T16:04:14Z has_accepted_license: '1' intvolume: ' 10' issue: '3' keyword: - coldboot language: - iso: eng page: 24:1-24:23 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS) publication_identifier: issn: - 1936-7406 publication_status: published publisher: Association for Computing Machinery (ACM) quality_controlled: '1' status: public title: Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs type: journal_article user_id: '15278' volume: 10 year: '2017' ... --- _id: '1592' abstract: - lang: eng text: Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844' apa: Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844 bibtex: '@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }' chicago: Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844. ieee: 'T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.' mla: Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844. short: 'T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.' date_created: 2018-03-22T11:10:23Z date_updated: 2023-09-26T13:24:38Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '61' doi: 10.23919/FPL.2017.8056844 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:02:28Z date_updated: 2018-11-02T15:02:28Z file_id: '5291' file_name: 08056844.pdf file_size: 230235 relation: main_file success: 1 file_date_updated: 2018-11-02T15:02:28Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '33' grant_number: 01|H16005A name: HighPerMeshes - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Flexible FPGA design for FDTD using OpenCL type: conference user_id: '15278' year: '2017' ... --- _id: '1589' article_number: '082003' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli citation: ama: 'Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series. 2017;898. doi:10.1088/1742-6596/898/8/082003' apa: 'Schumacher, J., Plessl, C., & Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series, 898, Article 082003. https://doi.org/10.1088/1742-6596/898/8/082003' bibtex: '@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={10.1088/1742-6596/898/8/082003}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }' chicago: 'Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series 898 (2017). https://doi.org/10.1088/1742-6596/898/8/082003.' ieee: 'J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi: 10.1088/1742-6596/898/8/082003.' mla: 'Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series, vol. 898, 082003, IOP Publishing, 2017, doi:10.1088/1742-6596/898/8/082003.' short: 'J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017).' date_created: 2018-03-22T10:51:20Z date_updated: 2023-09-26T13:24:19Z department: - _id: '27' - _id: '518' doi: 10.1088/1742-6596/898/8/082003 intvolume: ' 898' language: - iso: eng publication: 'Journal of Physics: Conference Series' publisher: IOP Publishing quality_controlled: '1' status: public title: High-Throughput and Low-Latency Network Communication with NetIO type: journal_article user_id: '15278' volume: 898 year: '2017' ... --- _id: '33' abstract: - lang: eng text: Lightweight materials play an ever growing role in today's world. Saving on the mass of a machine will usually translate into a lower energy consumption. However, lightweight applications are prone to develop performance problems due to vibration induced by the operation of the machine. The Fraunhofer Institute for Manufacturing Technology and Advanced Materials in Dresden conducts research into the damping properties of composite materials. They are experimenting with hollow, particle filled spheres embedded in the lightweight material. Such a system is the technical motivation of this thesis. Ultimately, a numerical experiment to derive the coefficient of restitution is required. The simulation developed in this thesis is based on a discrete element method to track the individual particle and sphere trajectories. Based on a potential based approach for the particle interactions deployed in molecular dynamics, the behavior of the particles can be controlled effectively. The simulated volume is using reflecting boundaries and encloses the hollow sphere. In this work, a highly flexible memory structure was used with a linked cell approach to cope with the highly flexible mass of particles. This allows for a linear complexity of the method in regard to the particle number by reducing the computational overhead of the interaction computation. Multiple numerical experiments show the great effect the particles have on the damping behavior of the system. - lang: ger text: In vielen technischen Anwendungen spielt heute der Leichtbau eine große Rolle, denn durch Gewichtseinsparungen lässt sich auch Energie einsparen. Allerdings birgt der Leichtbau die Gefahr einer erhöhten Störanfälligkeit gegenüber Vibrationen, die durch die Operation von Maschinen entstehen können. Das Fraunhofer Institut für Fertigungstechnik und Angewandte Materialforschung in Dresden beschäftigt sich mit den Möglichkeiten einer Schwingungsdämpfung durch Verbundwerkstoffe. Dabei wird in die Leichtbaustruktur eine Vielzahl von Hohlkugeln eingebracht, die mit Keramikpartikeln gefüllt sind. Diese Fragestellung bildet die technische Motivation für diese Arbeit. Ziel ist, ein Experiment zur Bestimmung des Restitutionskoeffizienten numerisch nachzubilden. Die Simulation basiert auf einer Diskreten Elemente Methode um die Trajektorien der einzelnen Partikel und der Kugel berechnen zu können. Basierend auf einem Potentialansatz für die Interaktionsberechnung in der Molekulardynamik kann das Reibungsverhalten vielfältig angepasst werden. Das Simulationsvolumen wird durch reflektierende Randbedingungen abgeschlossen und umfasst die Kugelhülle. Dazu kam eine hochflexible Speicherstruktur zum Einsatz, um die heterogene Verteilung der Partikel im Raum mit einer effizienten Linked Cell Methode abbilden zu können. Dadurch wird eine in der Partikelzahl lineare Komplexität erreicht. Umfangreiche numerische Experimente zeigen den großen Effekt der Partikelfüllung auf das Dämpfungsverhalten. author: - first_name: Tobias full_name: Steinle, Tobias last_name: Steinle citation: ama: Steinle T. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials.; 2016. apa: Steinle, T. (2016). Modeling and simulation of metallic, particle-damped spheres for lightweight materials. bibtex: '@book{Steinle_2016, title={Modeling and simulation of metallic, particle-damped spheres for lightweight materials}, author={Steinle, Tobias}, year={2016} }' chicago: Steinle, Tobias. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials, 2016. ieee: T. Steinle, Modeling and simulation of metallic, particle-damped spheres for lightweight materials. 2016. mla: Steinle, Tobias. Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials. 2016. short: T. Steinle, Modeling and Simulation of Metallic, Particle-Damped Spheres for Lightweight Materials, 2016. date_created: 2017-07-26T15:19:44Z date_updated: 2022-01-06T06:59:09Z department: - _id: '27' - _id: '104' - _id: '155' language: - iso: eng main_file_link: - url: http://nbn-resolving.de/urn:nbn:de:hbz:466:2-24042 status: public supervisor: - first_name: Andrea full_name: Walther, Andrea last_name: Walther - first_name: Jadran full_name: Vrabec, Jadran last_name: Vrabec title: Modeling and simulation of metallic, particle-damped spheres for lightweight materials type: dissertation user_id: '24135' year: '2016' ... --- _id: '34' author: - first_name: Michael full_name: Dellnitz, Michael last_name: Dellnitz - first_name: Julian full_name: Eckstein, Julian last_name: Eckstein - first_name: Kathrin full_name: Flaßkamp, Kathrin last_name: Flaßkamp - first_name: Patrick full_name: Friedel, Patrick last_name: Friedel - first_name: Christian full_name: Horenkamp, Christian last_name: Horenkamp - first_name: Ulrich full_name: Köhler, Ulrich last_name: Köhler - first_name: Sina full_name: Ober-Blöbaum, Sina last_name: Ober-Blöbaum - first_name: Sebastian full_name: Peitz, Sebastian last_name: Peitz - first_name: Sebastian full_name: Tiemeyer, Sebastian last_name: Tiemeyer citation: ama: 'Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87' apa: 'Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87' bibtex: '@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }' chicago: 'Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.' ieee: M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641. mla: Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87. short: 'M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.' date_created: 2017-07-26T15:25:33Z date_updated: 2022-01-06T06:59:14Z department: - _id: '27' - _id: '101' doi: 10.1007/978-3-319-23413-7_87 intvolume: ' 22' page: 633-641 place: Cham publication: Progress in Industrial Mathematics at ECMI publication_identifier: issn: - 2212-0173 publisher: Springer International Publishing series_title: Mathematics in Industry status: public title: Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control type: conference user_id: '24135' volume: 22 year: '2016' ... --- _id: '19' abstract: - lang: eng text: "Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Dominik full_name: Leibenger, Dominik last_name: Leibenger - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge citation: ama: 'Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11' apa: Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11 bibtex: '@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }' chicago: Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11. ieee: M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016. mla: Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11. short: 'M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.' date_created: 2017-07-25T14:36:16Z date_updated: 2022-01-06T06:53:56Z department: - _id: '27' - _id: '518' doi: 10.1109/lcn.2016.11 keyword: - access control - distributed version control systems - mercurial - peer-to-peer - convergent encryption - confidentiality - authenticity language: - iso: eng publication: Proc. 41st Conference on Local Computer Networks (LCN) publication_identifier: isbn: - 978-1-5090-2054-6 publication_status: published publisher: IEEE status: public title: Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension type: conference user_id: '24135' year: '2016' ... --- _id: '161' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter citation: ama: Kenter T. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn; 2016. apa: Kenter, T. (2016). Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn. bibtex: '@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016} }' chicago: Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016. ieee: T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016. mla: Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016. short: T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing, Universität Paderborn, 2016. date_created: 2017-10-17T12:41:23Z date_updated: 2022-01-06T06:52:43Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:46:48Z date_updated: 2018-03-21T12:46:48Z file_id: '1545' file_name: 161kenter16_diss_submission_print_16-08-26.pdf file_size: 5039555 relation: main_file success: 1 file_date_updated: 2018-03-21T12:46:48Z has_accepted_license: '1' project: - _id: '1' name: SFB 901 - _id: '14' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publisher: Universität Paderborn status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Reconfigurable Accelerators in the World of General-Purpose Computing type: dissertation user_id: '3145' year: '2016' ... --- _id: '29' abstract: - lang: eng text: In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers citation: ama: 'Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13' apa: Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13 bibtex: '@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }' chicago: 'Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.' ieee: 'A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.' mla: Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13. short: 'A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.' date_created: 2017-07-26T15:07:06Z date_updated: 2023-09-26T13:25:38Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-26408-0_13 editor: - first_name: Dirk full_name: Koch, Dirk last_name: Koch - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Daniel full_name: Ziener, Daniel last_name: Ziener language: - iso: eng page: 227-244 place: Cham project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: FPGAs for Software Programmers publication_identifier: isbn: - 978-3-319-26406-6 - 978-3-319-26408-0 publication_status: published publisher: Springer International Publishing quality_controlled: '1' status: public title: ReconOS type: book_chapter user_id: '15278' year: '2016' ... --- _id: '31' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Ettore M. G. full_name: Trainiti, Ettore M. G. last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. ieee: H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016. mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.' date_created: 2017-07-26T15:16:31Z date_updated: 2023-09-26T13:25:59Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: deffel date_created: 2019-01-11T11:56:55Z date_updated: 2019-01-11T11:56:55Z file_id: '6626' file_name: wrc_upb_polimi_final.pdf file_size: 394563 relation: main_file success: 1 file_date_updated: 2019-01-11T11:56:55Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC) quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '24' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.' apa: Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). bibtex: '@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. ieee: T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016. mla: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. short: 'T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.' date_created: 2017-07-26T15:00:43Z date_updated: 2023-09-26T13:26:17Z ddc: - '004' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: kenter date_created: 2018-11-14T12:38:45Z date_updated: 2018-11-14T12:38:45Z file_id: '5602' file_name: paper_26.pdf file_size: 129552 relation: main_file success: 1 file_date_updated: 2018-11-14T12:38:45Z has_accepted_license: '1' language: - iso: eng project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) quality_controlled: '1' status: public title: Microdisk Cavity FDTD Simulation on FPGA using OpenCL type: conference user_id: '15278' year: '2016' ... --- _id: '25' author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.' apa: Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC). bibtex: '@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }' chicago: Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016. ieee: M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016. mla: Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016. short: 'M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.' date_created: 2017-07-26T15:02:20Z date_updated: 2023-09-26T13:25:17Z department: - _id: '27' - _id: '518' - _id: '304' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Workshop on Approximate Computing (AC) quality_controlled: '1' status: public title: Using Approximate Computing in Scientific Codes type: conference user_id: '15278' year: '2016' ... --- _id: '138' abstract: - lang: eng text: Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: 'Ettore M. G. ' full_name: 'Trainiti, Ettore M. G. ' last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Emanuele full_name: Del Sozzo, Emanuele last_name: Del Sozzo - first_name: 'Marco D. ' full_name: 'Santambrogio, Marco D. ' last_name: Santambrogio - first_name: Christina full_name: Bolchini, Christina last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545 bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545. ieee: 'H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.' mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.' date_created: 2017-10-17T12:41:18Z date_updated: 2023-09-26T13:28:11Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1109/RTSI.2016.7740545 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:01:09Z date_updated: 2018-03-21T13:01:09Z file_id: '1560' file_name: 138-07740545.pdf file_size: 184334 relation: main_file success: 1 file_date_updated: 2018-03-21T13:01:09Z has_accepted_license: '1' language: - iso: eng page: 1-5 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI) publisher: IEEE quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '156' abstract: - lang: eng text: Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8' apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8 bibtex: '@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }' chicago: 'Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.' ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.' mla: Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8. short: 'A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.' date_created: 2017-10-17T12:41:22Z date_updated: 2023-09-26T13:27:44Z ddc: - '040' department: - _id: '518' - _id: '27' - _id: '78' doi: 10.1007/978-3-319-39675-0_8 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-11-14T13:20:32Z date_updated: 2018-11-14T13:20:32Z file_id: '5613' file_name: chapter8.pdf file_size: 833054 relation: main_file success: 1 file_date_updated: 2018-11-14T13:20:32Z has_accepted_license: '1' language: - iso: eng page: 145-165 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Self-aware Computing Systems publisher: Springer International Publishing quality_controlled: '1' series_title: Natural Computing Series (NCS) status: public title: Self-aware Compute Nodes type: book_chapter user_id: '15278' year: '2016' ... --- _id: '165' abstract: - lang: eng text: A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes. author: - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021 apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021 bibtex: '@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }' chicago: 'Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.' ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.' mla: Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021. short: G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111. date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:26:38Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1016/j.compeleceng.2016.04.021 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:45:47Z date_updated: 2018-03-21T12:45:47Z file_id: '1544' file_name: 165-1-s2.0-S0045790616301021-main.pdf file_size: 3037854 relation: main_file success: 1 file_date_updated: 2018-03-21T12:45:47Z has_accepted_license: '1' intvolume: ' 55' language: - iso: eng page: 91-111 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Computers and Electrical Engineering publication_identifier: issn: - 0045-7906 publisher: Elsevier quality_controlled: '1' status: public title: Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code type: journal_article user_id: '15278' volume: 55 year: '2016' ... --- _id: '168' abstract: - lang: eng text: The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.' apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917. bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }' chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016. ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917. mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17. short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.' date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:27:00Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:41:55Z date_updated: 2018-03-21T12:41:55Z file_id: '1541' file_name: 168-07459438.pdf file_size: 261356 relation: main_file success: 1 file_date_updated: 2018-03-21T12:41:55Z has_accepted_license: '1' language: - iso: eng page: 912-917 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Performance-centric scheduling with task migration for a heterogeneous compute node in the data center type: conference user_id: '15278' year: '2016' ... --- _id: '171' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.' apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC). bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016. ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016. mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016. short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.' date_created: 2017-10-17T12:41:25Z date_updated: 2023-09-26T13:27:21Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:39:46Z date_updated: 2018-03-21T12:39:46Z file_id: '1538' file_name: 171-plessl16_fpl_wrc.pdf file_size: 54421 relation: main_file success: 1 file_date_updated: 2018-03-21T12:39:46Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Workshop on Reconfigurable Computing (WRC) quality_controlled: '1' status: public title: Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) type: conference user_id: '15278' year: '2016' ... --- _id: '1769' abstract: - lang: eng text: 'Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.' author: - first_name: Sebastian full_name: Hegler, Sebastian last_name: Hegler - first_name: Christoph full_name: Statz, Christoph last_name: Statz - first_name: Marco full_name: Mütze, Marco last_name: Mütze - first_name: Hubert full_name: Mooshofer, Hubert last_name: Mooshofer - first_name: Matthias full_name: Goldammer, Matthias last_name: Goldammer - first_name: Karl full_name: Fendt, Karl last_name: Fendt - first_name: Stefan full_name: Schwarzer, Stefan last_name: Schwarzer - first_name: Kim full_name: Feldhoff, Kim last_name: Feldhoff - first_name: Martin full_name: Flehmig, Martin last_name: Flehmig - first_name: Ulf full_name: Markwardt, Ulf last_name: Markwardt - first_name: Wolfgang full_name: E. Nagel, Wolfgang last_name: E. Nagel - first_name: Maria full_name: Schütte, Maria last_name: Schütte - first_name: Andrea full_name: Walther, Andrea last_name: Walther - first_name: Michael full_name: Meinel, Michael last_name: Meinel - first_name: Achim full_name: Basermann, Achim last_name: Basermann - first_name: Dirk full_name: Plettemeier, Dirk last_name: Plettemeier citation: ama: Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031 apa: Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K., … Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm - Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031 bibtex: '@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82}, DOI={doi:10.1515/teme-2015-0031}, number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter}, author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer, Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff, Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450} }' chicago: 'Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.' ieee: S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm - Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015. mla: Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50, doi:doi:10.1515/teme-2015-0031. short: S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450. date_created: 2018-03-23T14:01:39Z date_updated: 2022-01-06T06:53:17Z department: - _id: '27' - _id: '104' doi: doi:10.1515/teme-2015-0031 intvolume: ' 82' issue: '9' page: 440-450 publication: tm - Technisches Messen publisher: Walter de Gruyter status: public title: Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung type: journal_article user_id: '24135' volume: 82 year: '2015' ... --- _id: '1772' author: - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Xin full_name: Yao, Xin last_name: Yao citation: ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205 apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205 bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }' chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.' ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015. mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205. short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20. date_created: 2018-03-23T14:06:12Z date_updated: 2022-01-06T06:53:19Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/MC.2015.205 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:47:45Z date_updated: 2018-11-02T15:47:45Z file_id: '5313' file_name: 07163237.pdf file_size: 5605009 relation: main_file success: 1 file_date_updated: 2018-11-02T15:47:45Z has_accepted_license: '1' intvolume: ' 48' issue: '7' keyword: - self-awareness - self-expression language: - iso: eng page: 18-20 project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: IEEE Computer publisher: IEEE Computer Society status: public title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction type: journal_article user_id: '16153' volume: 48 year: '2015' ... --- _id: '1774' abstract: - lang: eng text: In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100. author: - first_name: Sebastian full_name: Peitz, Sebastian last_name: Peitz - first_name: Michael full_name: Dellnitz, Michael last_name: Dellnitz citation: ama: Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296 apa: Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614. https://doi.org/10.1002/pamm.201510296 bibtex: '@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296}, number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian and Dellnitz, Michael}, year={2015}, pages={613–614} }' chicago: 'Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1 (2015): 613–14. https://doi.org/10.1002/pamm.201510296.' ieee: S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614, 2015. mla: Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no. 1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296. short: S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614. date_created: 2018-03-23T14:14:24Z date_updated: 2022-01-06T06:53:19Z department: - _id: '27' - _id: '101' doi: 10.1002/pamm.201510296 intvolume: ' 15' issue: '1' page: 613-614 publication: PAMM publication_identifier: issn: - 1617-7061 publisher: WILEY-VCH Verlag status: public title: Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction type: journal_article user_id: '24135' volume: 15 year: '2015' ... --- _id: '10624' abstract: - lang: eng text: "The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies." author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel citation: ama: 'Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.' apa: 'Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.' bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }' chicago: 'Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.' ieee: 'T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.' mla: Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015. short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015. date_created: 2019-07-10T09:36:58Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' - _id: '27' - _id: '518' language: - iso: eng page: '183' place: Berlin project: - _id: '30' grant_number: 01|H11004 name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication_identifier: isbn: - 978-3-8325-4155-2 publisher: Logos Verlag Berlin GmbH status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing type: dissertation user_id: '3118' year: '2015' ... --- _id: '296' abstract: - lang: eng text: FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x. article_number: '859425' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425 apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425 bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425.' mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425. short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015). date_created: 2017-10-17T12:41:49Z date_updated: 2023-09-26T13:29:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2015/859425 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:47:56Z date_updated: 2018-03-20T07:47:56Z file_id: '1444' file_name: 296-859425.pdf file_size: 2993898 relation: main_file success: 1 file_date_updated: 2018-03-20T07:47:56Z has_accepted_license: '1' intvolume: ' 2015' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: International Journal of Reconfigurable Computing (IJRC) publisher: Hindawi quality_controlled: '1' status: public title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study type: journal_article user_id: '15278' volume: 2015 year: '2015' ... --- _id: '303' abstract: - lang: eng text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.' apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }' chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015. mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.' date_created: 2017-10-17T12:41:51Z date_updated: 2023-09-26T13:29:59Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' external_id: arxiv: - '1412.3906' file: - access_level: open_access content_type: application/pdf creator: florida date_created: 2018-03-20T07:46:46Z date_updated: 2019-08-01T09:10:44Z file_id: '1442' file_name: 303-plessl15_adapt.pdf file_size: 1176620 relation: main_file file_date_updated: 2019-08-01T09:10:44Z has_accepted_license: '1' language: - iso: eng oa: '1' project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) quality_controlled: '1' status: public title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores type: conference user_id: '15278' year: '2015' ... --- _id: '1773' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: J. full_name: T. Anderson, J. last_name: T. Anderson - first_name: A. full_name: Borga, A. last_name: Borga - first_name: H. full_name: Boterenbrood, H. last_name: Boterenbrood - first_name: H. full_name: Chen, H. last_name: Chen - first_name: K. full_name: Chen, K. last_name: Chen - first_name: G. full_name: Drake, G. last_name: Drake - first_name: D. full_name: Francis, D. last_name: Francis - first_name: B. full_name: Gorini, B. last_name: Gorini - first_name: F. full_name: Lanni, F. last_name: Lanni - first_name: Giovanna full_name: Lehmann-Miotto, Giovanna last_name: Lehmann-Miotto - first_name: L. full_name: Levinson, L. last_name: Levinson - first_name: J. full_name: Narevicius, J. last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A. full_name: Roich, A. last_name: Roich - first_name: S. full_name: Ryu, S. last_name: Ryu - first_name: F. full_name: P. Schreuder, F. last_name: P. Schreuder - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J. full_name: Vermeulen, J. last_name: Vermeulen - first_name: J. full_name: Zhang, J. last_name: Zhang citation: ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824' apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824 bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }' chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824. ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.' mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824. short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.' date_created: 2018-03-23T14:09:33Z date_updated: 2023-09-26T13:31:01Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/2675743.2771824 language: - iso: eng publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) publisher: ACM quality_controlled: '1' status: public title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm type: conference user_id: '15278' year: '2015' ... --- _id: '1768' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Peter J. full_name: Schreier, Peter J. last_name: Schreier citation: ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z' apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z' bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }' chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.' ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.' mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.' short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399. date_created: 2018-03-23T13:58:34Z date_updated: 2023-09-26T13:30:22Z department: - _id: '27' - _id: '518' - _id: '263' - _id: '78' doi: 10.1007/s00287-015-0911-z issue: '5' keyword: - approximate computing - survey language: - iso: eng page: 396-399 publication: Informatik Spektrum publisher: Springer quality_controlled: '1' status: public title: 'Aktuelles Schlagwort: Approximate Computing' type: journal_article user_id: '15278' year: '2015' ... --- _id: '238' abstract: - lang: eng text: In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124' apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124 bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }' chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124. ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.' mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124. short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.' date_created: 2017-10-17T12:41:38Z date_updated: 2023-09-26T13:31:44Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.7873/DATE.2015.1124 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T10:29:49Z date_updated: 2018-03-21T10:29:49Z file_id: '1500' file_name: 238-plessl15_date.pdf file_size: 380552 relation: main_file success: 1 file_date_updated: 2018-03-21T10:29:49Z has_accepted_license: '1' language: - iso: eng page: 1078-1083 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Transparent offloading of computational hotspots from binary code to Xeon Phi type: conference user_id: '15278' year: '2015' ... --- _id: '1775' abstract: - lang: eng text: The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed. article_number: '082050' author: - first_name: J full_name: Anderson, J last_name: Anderson - first_name: A full_name: Borga, A last_name: Borga - first_name: H full_name: Boterenbrood, H last_name: Boterenbrood - first_name: H full_name: Chen, H last_name: Chen - first_name: K full_name: Chen, K last_name: Chen - first_name: G full_name: Drake, G last_name: Drake - first_name: D full_name: Francis, D last_name: Francis - first_name: B full_name: Gorini, B last_name: Gorini - first_name: F full_name: Lanni, F last_name: Lanni - first_name: G full_name: Lehmann Miotto, G last_name: Lehmann Miotto - first_name: L full_name: Levinson, L last_name: Levinson - first_name: J full_name: Narevicius, J last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A full_name: Roich, A last_name: Roich - first_name: S full_name: Ryu, S last_name: Ryu - first_name: F full_name: Schreuder, F last_name: Schreuder - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J full_name: Vermeulen, J last_name: Vermeulen - first_name: J full_name: Zhang, J last_name: Zhang citation: ama: 'Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050' apa: 'Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050' bibtex: '@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }' chicago: 'Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series 664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.' ieee: 'J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.' mla: 'Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.' short: 'J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015).' date_created: 2018-03-23T14:19:27Z date_updated: 2023-09-26T13:31:23Z department: - _id: '27' - _id: '518' doi: 10.1088/1742-6596/664/8/082050 intvolume: ' 664' language: - iso: eng publication: 'Journal of Physics: Conference Series' publisher: IOP Publishing quality_controlled: '1' status: public title: 'FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades' type: journal_article user_id: '15278' volume: 664 year: '2015' ... --- _id: '1781' abstract: - lang: eng text: In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment. author: - first_name: Tobias full_name: Steinle, Tobias last_name: Steinle - first_name: Jadran full_name: Vrabec, Jadran last_name: Vrabec - first_name: Andrea full_name: Walther, Andrea last_name: Walther citation: ama: 'Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19' apa: Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19 bibtex: '@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }' chicago: Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19. ieee: T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243. mla: Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19. short: 'T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.' date_created: 2018-03-26T13:47:16Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '104' - _id: '155' doi: 10.1007/978-3-319-09063-4_19 editor: - first_name: Hans Georg full_name: Bock, Hans Georg last_name: Bock - first_name: Xuan Phu full_name: Hoang, Xuan Phu last_name: Hoang - first_name: Rolf full_name: Rannacher, Rolf last_name: Rannacher - first_name: Johannes P. full_name: Schlöder, Johannes P. last_name: Schlöder page: 233-243 publication: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) publication_identifier: isbn: - 978-3-319-09063-4 publisher: Springer International Publishing status: public title: Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres type: conference user_id: '24135' year: '2014' ... --- _id: '1782' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2' apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2' bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }' chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.' ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25. mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2. short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.' date_created: 2018-03-26T13:50:37Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '78' doi: 10.1007/978-3-319-09165-5_2 issue: '8427' page: 14-25 place: Switzerland publication: Proc. Conf. on Computers and Games (CG) publisher: Springer series_title: Lecture Notes in Computer Science status: public title: On Semeai Detection in Monte-Carlo Go type: conference user_id: '24135' year: '2014' ... --- _id: '335' abstract: - lang: eng text: Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf. author: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.' apa: 'Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Wilhelm Fink.' bibtex: '@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }' chicago: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.' ieee: 'M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.' mla: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.' short: 'M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.' date_created: 2017-10-17T12:41:57Z date_updated: 2023-09-26T13:32:49Z ddc: - '040' department: - _id: '518' - _id: '27' - _id: '78' editor: - first_name: Jörn full_name: Künsemöller, Jörn last_name: Künsemöller - first_name: Norber Otto full_name: Eke, Norber Otto last_name: Eke - first_name: Lioba full_name: Foit, Lioba last_name: Foit - first_name: Timo full_name: Kaerlein, Timo last_name: Kaerlein file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:29:58Z date_updated: 2018-03-20T07:29:58Z file_id: '1424' file_name: 335-2014_plessl_automatismen.pdf file_size: 2848154 relation: main_file success: 1 file_date_updated: 2018-03-20T07:29:58Z has_accepted_license: '1' language: - iso: ger page: 123-144 place: Paderborn project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: 'Logiken strukturbildender Prozesse: Automatismen' publication_identifier: isbn: - 978-3-7705-5730-1 publication_status: published publisher: Wilhelm Fink quality_controlled: '1' series_title: Schriftenreihe des Graduiertenkollegs "Automatismen" status: public title: Verschiebungen an der Grenze zwischen Hardware und Software type: book_chapter user_id: '15278' year: '2014' ... --- _id: '388' abstract: - lang: eng text: In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13' apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13' bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.' ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.' mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.' short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.' date_created: 2017-10-17T12:42:07Z date_updated: 2023-09-26T13:34:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-05960-0_13 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:02:02Z date_updated: 2018-03-20T07:02:02Z file_id: '1387' file_name: 388-plessl14_arc.pdf file_size: 330193 relation: main_file success: 1 file_date_updated: 2018-03-20T07:02:02Z has_accepted_license: '1' intvolume: ' 8405' language: - iso: eng page: 144-155 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: 'Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)' publisher: Springer International Publishing quality_controlled: '1' series_title: Lecture Notes in Computer Science (LNCS) status: public title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer type: conference user_id: '15278' volume: 8405 year: '2014' ... --- _id: '363' abstract: - lang: eng text: Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001 apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001 bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }' chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.' ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.' mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001. short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919. date_created: 2017-10-17T12:42:02Z date_updated: 2023-09-26T13:33:06Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2013.12.001 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:20:31Z date_updated: 2018-03-20T07:20:31Z file_id: '1408' file_name: 363-plessl13_micpro.pdf file_size: 1499996 relation: main_file success: 1 file_date_updated: 2018-03-20T07:20:31Z has_accepted_license: '1' intvolume: ' 38' issue: 8, Part B language: - iso: eng page: 911-919 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Microprocessors and Microsystems publisher: Elsevier quality_controlled: '1' status: public title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators type: journal_article user_id: '15278' volume: 38 year: '2014' ... --- _id: '377' abstract: - lang: eng text: In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge citation: ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67' apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67 bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }' chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67. ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.' mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67. short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.' date_created: 2017-10-17T12:42:05Z date_updated: 2023-09-26T13:33:50Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FCCM.2014.67 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:14:20Z date_updated: 2018-03-20T07:14:20Z file_id: '1397' file_name: 377-FCCM14.pdf file_size: 1003907 relation: main_file success: 1 file_date_updated: 2018-03-20T07:14:20Z has_accepted_license: '1' keyword: - coldboot language: - iso: eng page: 222-229 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM) publisher: IEEE quality_controlled: '1' status: public title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs type: conference user_id: '15278' year: '2014' ... --- _id: '365' abstract: - lang: eng text: Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems. article_number: '13' author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596 apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596 bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }' chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596. ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.' mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596. short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014). date_created: 2017-10-17T12:42:03Z date_updated: 2023-09-26T13:33:31Z ddc: - '040' department: - _id: '27' - _id: '78' - _id: '518' doi: 10.1145/2617596 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:19:19Z date_updated: 2018-03-20T07:19:19Z file_id: '1406' file_name: 365-plessl14_trets_01.pdf file_size: 916052 relation: main_file success: 1 file_date_updated: 2018-03-20T07:19:19Z has_accepted_license: '1' intvolume: ' 7' issue: '2' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS) publisher: ACM quality_controlled: '1' status: public title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores type: journal_article user_id: '15278' volume: 7 year: '2014' ... --- _id: '328' abstract: - lang: eng text: The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Ariane full_name: Keller, Ariane last_name: Keller - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Bernhard full_name: Plattner, Bernhard last_name: Plattner - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110 apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110 bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }' chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.' ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.' mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110. short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71. date_created: 2017-10-17T12:41:55Z date_updated: 2023-09-26T13:32:31Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/MM.2013.110 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:31:40Z date_updated: 2018-03-20T07:31:40Z file_id: '1426' file_name: 328-plessl14_micro_01.pdf file_size: 1877185 relation: main_file success: 1 file_date_updated: 2018-03-20T07:31:40Z has_accepted_license: '1' intvolume: ' 34' issue: '1' language: - iso: eng page: 60-71 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: IEEE Micro publisher: IEEE quality_controlled: '1' status: public title: ReconOS - An Operating System Approach for Reconfigurable Computing type: journal_article user_id: '15278' volume: 34 year: '2014' ... --- _id: '1778' author: - first_name: Gianluca full_name: C. Durelli, Gianluca last_name: C. Durelli - first_name: Marcello full_name: Pogliani, Marcello last_name: Pogliani - first_name: Antonio full_name: Miele, Antonio last_name: Miele - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Marco full_name: D. Santambrogio, Marco last_name: D. Santambrogio - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27' apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27' bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }' chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.' ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.' mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.' short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.' date_created: 2018-03-26T13:40:14Z date_updated: 2023-09-26T13:35:40Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ISPA.2014.27 language: - iso: eng page: 142-149 project: - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) publisher: IEEE quality_controlled: '1' status: public title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach' type: conference user_id: '15278' year: '2014' ... --- _id: '439' abstract: - lang: eng text: Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. author: - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509' apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509 bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }' chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509. ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.' mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509. short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.' date_created: 2017-10-17T12:42:17Z date_updated: 2023-09-26T13:37:02Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2014.7032509 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:29:52Z date_updated: 2018-03-16T11:29:52Z file_id: '1353' file_name: 439-plessl14a_reconfig.pdf file_size: 557362 relation: main_file success: 1 file_date_updated: 2018-03-16T11:29:52Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Deferring Accelerator Offloading Decisions to Application Runtime type: conference user_id: '15278' year: '2014' ... --- _id: '406' abstract: - lang: eng text: Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535' apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535 bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.' mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535. short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.' date_created: 2017-10-17T12:42:11Z date_updated: 2023-09-26T13:36:40Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2014.7032535 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:37:42Z date_updated: 2018-03-16T11:37:42Z file_id: '1366' file_name: 406-ReConFig14.pdf file_size: 932852 relation: main_file success: 1 file_date_updated: 2018-03-16T11:37:42Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching type: conference user_id: '15278' year: '2014' ... --- _id: '1780' author: - first_name: Gianluca full_name: C. Durelli, Gianluca last_name: C. Durelli - first_name: Marcello full_name: Copolla, Marcello last_name: Copolla - first_name: Karim full_name: Djafarian, Karim last_name: Djafarian - first_name: George full_name: Koranaros, George last_name: Koranaros - first_name: Antonio full_name: Miele, Antonio last_name: Miele - first_name: Michele full_name: Paolino, Michele last_name: Paolino - first_name: Oliver full_name: Pell, Oliver last_name: Pell - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: D. Santambrogio, Marco last_name: D. Santambrogio - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38' apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38' bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }' chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.' ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.' mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.' short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.' date_created: 2018-03-26T13:45:35Z date_updated: 2023-09-26T13:36:20Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-05960-0_38 language: - iso: eng project: - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)' publisher: Springer quality_controlled: '1' status: public title: 'SAVE: Towards efficient resource management in heterogeneous system architectures' type: conference user_id: '15278' year: '2014' ... --- _id: '1779' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372 apa: Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372 bibtex: '@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }' chicago: 'Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.' ieee: 'H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.' mla: Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372. short: H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70. date_created: 2018-03-26T13:42:34Z date_updated: 2023-09-26T13:35:58Z department: - _id: '27' - _id: '518' - _id: '61' - _id: '78' doi: 10.1145/2641361.2641372 intvolume: ' 41' issue: '5' keyword: - funding-maxup - tet_topic_hpc language: - iso: eng page: 65-70 publication: ACM SIGARCH Computer Architecture News publication_identifier: issn: - 0163-5964 publisher: ACM quality_controlled: '1' status: public title: Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers type: journal_article user_id: '15278' volume: 41 year: '2014' ... --- _id: '1784' author: - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Viktor full_name: Gottfried, Viktor last_name: Gottfried - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97. doi:10.1109/NAS.2013.18' apa: 'Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/NAS.2013.18' bibtex: '@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers}, DOI={10.1109/NAS.2013.18}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor and Brinkmann, André}, year={2013}, pages={88–97} }' chicago: 'Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.' ieee: 'J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2013, pp. 88–97.' mla: 'Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.' short: 'J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington DC, USA, 2013, pp. 88–97.' date_created: 2018-03-26T14:43:38Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' doi: 10.1109/NAS.2013.18 page: 88-97 place: Washington DC, USA publication: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) publisher: IEEE Computer Society status: public title: 'MCD: Overcoming the Data Download Bottleneck in Data Centers' type: conference user_id: '24135' year: '2013' ... --- _id: '1786' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530' apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530 bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }' chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530. ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013. mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530. short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.' date_created: 2018-03-26T14:48:53Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '78' doi: 10.1109/SIU.2013.6531530 publication: Proc. IEEE Signal Processing and Communications Conf. (SUI) publisher: IEEE status: public title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm type: conference user_id: '24135' year: '2013' ... --- _id: '1788' author: - first_name: Petra full_name: Berenbrink, Petra last_name: Berenbrink - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Tom full_name: Friedetzky, Tom last_name: Friedetzky - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Lars full_name: Nagel, Lars last_name: Nagel citation: ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148' apa: Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L. (2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148 bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Meister, Dirk and Nagel, Lars}, year={2013} }' chicago: Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148. ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013. mla: Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013, doi:10.1109/IPDPSW.2013.148. short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.' date_created: 2018-03-26T14:52:56Z date_updated: 2022-01-06T06:53:22Z department: - _id: '27' doi: 10.1109/IPDPSW.2013.148 publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) publisher: IEEE status: public title: Distributing Storage in Cloud Environments type: conference user_id: '24135' year: '2013' ... --- _id: '1790' author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster citation: ama: 'Niehörster O. Autonomous Resource Management in Dynamic Data Centers. Aachen, Germany: Shaker; 2013.' apa: 'Niehörster, O. (2013). Autonomous Resource Management in Dynamic Data Centers. Aachen, Germany: Shaker.' bibtex: '@book{Niehörster_2013, place={Aachen, Germany}, title={Autonomous Resource Management in Dynamic Data Centers}, publisher={Shaker}, author={Niehörster, Oliver}, year={2013} }' chicago: 'Niehörster, Oliver. Autonomous Resource Management in Dynamic Data Centers. Aachen, Germany: Shaker, 2013.' ieee: 'O. Niehörster, Autonomous Resource Management in Dynamic Data Centers. Aachen, Germany: Shaker, 2013.' mla: Niehörster, Oliver. Autonomous Resource Management in Dynamic Data Centers. Shaker, 2013. short: O. Niehörster, Autonomous Resource Management in Dynamic Data Centers, Shaker, Aachen, Germany, 2013. date_created: 2018-03-26T15:12:56Z date_updated: 2022-01-06T06:53:22Z department: - _id: '27' place: Aachen, Germany publication_identifier: isbn: - 978-3-8440-1735-9 publisher: Shaker status: public title: Autonomous Resource Management in Dynamic Data Centers type: book user_id: '24135' year: '2013' ... --- _id: '1791' author: - first_name: Dirk full_name: Meister, Dirk last_name: Meister citation: ama: Meister D. Advanced Data Deduplication Techniques and Their Application. Johannes Gutenberg-Universität Mainz; 2013. apa: Meister, D. (2013). Advanced Data Deduplication Techniques and Their Application. Johannes Gutenberg-Universität Mainz. bibtex: '@book{Meister_2013, title={Advanced Data Deduplication Techniques and Their Application}, publisher={Johannes Gutenberg-Universität Mainz}, author={Meister, Dirk}, year={2013} }' chicago: Meister, Dirk. Advanced Data Deduplication Techniques and Their Application. Johannes Gutenberg-Universität Mainz, 2013. ieee: D. Meister, Advanced Data Deduplication Techniques and Their Application. Johannes Gutenberg-Universität Mainz, 2013. mla: Meister, Dirk. Advanced Data Deduplication Techniques and Their Application. Johannes Gutenberg-Universität Mainz, 2013. short: D. Meister, Advanced Data Deduplication Techniques and Their Application, Johannes Gutenberg-Universität Mainz, 2013. date_created: 2018-03-26T15:13:49Z date_updated: 2022-01-06T06:53:23Z department: - _id: '27' publisher: Johannes Gutenberg-Universität Mainz status: public title: Advanced Data Deduplication Techniques and Their Application type: dissertation user_id: '24135' year: '2013' ... --- _id: '1792' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069 apa: Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3), 522–536. https://doi.org/10.1109/TVLSI.2013.2248069 bibtex: '@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={10.1109/TVLSI.2013.2248069}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }' chicago: 'Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22, no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.' ieee: S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 522–536, 2013. mla: Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069. short: S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536. date_created: 2018-03-26T15:15:03Z date_updated: 2022-01-06T06:53:23Z department: - _id: '27' - _id: '78' doi: 10.1109/TVLSI.2013.2248069 intvolume: ' 22' issue: '3' page: 522-536 publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems publisher: IEEE status: public title: Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices type: journal_article user_id: '24135' volume: 22 year: '2013' ... --- _id: '1793' author: - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Tim full_name: Süß, Tim last_name: Süß citation: ama: 'Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.' apa: Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association. bibtex: '@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }' chicago: Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013. ieee: D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182. mla: Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82. short: 'D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.' date_created: 2018-03-26T15:16:03Z date_updated: 2022-01-06T06:53:23Z department: - _id: '27' page: 175-182 publication: Proc. USENIX Conference on File and Storage Technologies (FAST) publisher: USENIX Association status: public title: File Recipe Compression in Data Deduplication Systems type: conference user_id: '24135' year: '2013' ... --- _id: '528' abstract: - lang: eng text: Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394' apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394 bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }' chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394. ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.' mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394. short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.' date_created: 2017-10-17T12:42:35Z date_updated: 2023-09-26T13:37:35Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FPT.2013.6718394 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T10:36:08Z date_updated: 2018-03-15T10:36:08Z file_id: '1294' file_name: 528-plessl13_fpt.pdf file_size: 822680 relation: main_file success: 1 file_date_updated: 2018-03-15T10:36:08Z has_accepted_license: '1' keyword: - coldboot language: - iso: eng page: 386-389 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '13' name: SFB 901 - Subproject C1 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) publisher: IEEE quality_controlled: '1' status: public title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES type: conference user_id: '15278' year: '2013' ... --- _id: '505' abstract: - lang: eng text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Peter full_name: Kling, Peter last_name: Kling - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Friedhelm full_name: Meyer auf der Heide, Friedhelm id: '15523' last_name: Meyer auf der Heide citation: ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232' apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232' bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }' chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.' ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.' mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.' short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.' date_created: 2017-10-17T12:42:30Z date_updated: 2023-09-26T13:38:20Z ddc: - '040' department: - _id: '63' - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ISORC.2013.6913232 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T13:38:56Z date_updated: 2018-03-15T13:38:56Z file_id: '1308' file_name: 505-Plessl13_seus.pdf file_size: 1040834 relation: main_file success: 1 file_date_updated: 2018-03-15T13:38:56Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) publisher: IEEE quality_controlled: '1' status: public title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services' type: conference user_id: '15278' year: '2013' ... --- _id: '1787' author: - first_name: Tim full_name: Suess, Tim last_name: Suess - first_name: Andrew full_name: Schoenrock, Andrew last_name: Schoenrock - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136' apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136 bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }' chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.' ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.' mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136. short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.' date_created: 2018-03-26T14:51:05Z date_updated: 2023-09-26T13:38:05Z department: - _id: '27' - _id: '518' - _id: '78' - _id: '63' doi: 10.1109/IPDPSW.2013.136 language: - iso: eng page: 64-73 place: Washington, DC, USA project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) publication_identifier: isbn: - 978-0-7695-4979-8 publisher: IEEE Computer Society quality_controlled: '1' status: public title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer type: conference user_id: '15278' year: '2013' ... --- _id: '1965' abstract: - lang: eng text: Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations. author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: Jens full_name: Simon, Jens id: '15273' last_name: Simon - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Jens full_name: Krüger, Jens last_name: Krüger citation: ama: Niehörster O, Simon J, Brinkmann A, Keller A, Krüger J. Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing. 2012;10(3):553-577. doi:10.1007/s10723-012-9230-7 apa: Niehörster, O., Simon, J., Brinkmann, A., Keller, A., & Krüger, J. (2012). Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing, 10(3), 553–577. https://doi.org/10.1007/s10723-012-9230-7 bibtex: '@article{Niehörster_Simon_Brinkmann_Keller_Krüger_2012, title={Cost-aware and SLO Fulfilling Software as a Service}, volume={10}, DOI={10.1007/s10723-012-9230-7}, number={3}, journal={Journal of Grid Computing}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Keller, Axel and Krüger, Jens}, year={2012}, pages={553–577} }' chicago: 'Niehörster, Oliver, Jens Simon, André Brinkmann, Axel Keller, and Jens Krüger. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing 10, no. 3 (2012): 553–77. https://doi.org/10.1007/s10723-012-9230-7.' ieee: O. Niehörster, J. Simon, A. Brinkmann, A. Keller, and J. Krüger, “Cost-aware and SLO Fulfilling Software as a Service,” Journal of Grid Computing, vol. 10, no. 3, pp. 553–577, 2012. mla: Niehörster, Oliver, et al. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing, vol. 10, no. 3, 2012, pp. 553–77, doi:10.1007/s10723-012-9230-7. short: O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid Computing 10 (2012) 553–577. date_created: 2018-03-29T11:16:18Z date_updated: 2022-01-06T06:54:09Z department: - _id: '27' doi: 10.1007/s10723-012-9230-7 intvolume: ' 10' issue: '3' language: - iso: eng page: 553-577 publication: Journal of Grid Computing publication_status: published status: public title: Cost-aware and SLO Fulfilling Software as a Service type: journal_article user_id: '15274' volume: 10 year: '2012' ... --- _id: '2097' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125' apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125 bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }' chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125. ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140. mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125. short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.' date_created: 2018-03-29T14:34:48Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' doi: 10.1109/FPT.2012.6412125 page: 135-140 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm type: conference user_id: '24135' year: '2012' ... --- _id: '2098' author: - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Tim full_name: Hartung, Tim last_name: Hartung - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34' apa: 'Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34' bibtex: '@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }' chicago: 'Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.' ieee: 'J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.' mla: 'Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34.' short: 'J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.' date_created: 2018-03-29T14:40:04Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/ICPADS.2012.34 page: 181-188 publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) publisher: IEEE status: public title: 'ESB: Ext2 Split Block Device' type: conference user_id: '24135' year: '2012' ... --- _id: '2099' author: - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Michael full_name: Kuhn, Michael last_name: Kuhn - first_name: Julian full_name: Kunkel, Julian last_name: Kunkel - first_name: Toni full_name: Cortes, Toni last_name: Cortes citation: ama: 'Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14' apa: 'Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14' bibtex: '@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }' chicago: 'Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14.' ieee: D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on Supercomputing (SC), 2012, pp. 7:1-7:11. mla: Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14. short: 'D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11.' date_created: 2018-03-29T14:41:55Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/SC.2012.14 page: 7:1-7:11 place: Los Alamitos, CA, USA publication: Proc. Int. Conf. on Supercomputing (SC) publisher: IEEE Computer Society status: public title: A Study on Data Deduplication in HPC Storage Systems type: conference user_id: '24135' year: '2012' ... --- _id: '2100' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.' apa: Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG). bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }' chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012. ieee: S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012. mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012. short: 'S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.' date_created: 2018-03-29T14:43:18Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' publication: Int. Architecture and Engineering Symp. (ARCHENG) status: public title: FPGA implementation of a second-order convolutive blind signal separation algorithm type: conference user_id: '24135' year: '2012' ... --- _id: '2101' author: - first_name: Matthias full_name: Grawinkel, Matthias last_name: Grawinkel - first_name: Tim full_name: Süß, Tim last_name: Süß - first_name: Georg full_name: Best, Georg last_name: Best - first_name: Ivan full_name: Popov, Ivan last_name: Popov - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17. doi:10.1109/SC.Companion.2012.13' apa: Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW) (pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13 bibtex: '@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13}, booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel, Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012}, pages={13–17} }' chicago: Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann. “Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop (PDSW), 13–17. IEEE, 2012. https://doi.org/10.1109/SC.Companion.2012.13. ieee: M. Grawinkel, T. Süß, G. Best, I. Popov, and A. Brinkmann, “Towards Dynamic Scripted pNFS Layouts,” in Proc. Parallel Data Storage Workshop (PDSW), 2012, pp. 13–17. mla: Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13. short: 'M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17.' date_created: 2018-03-29T14:44:24Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/SC.Companion.2012.13 page: 13-17 publication: Proc. Parallel Data Storage Workshop (PDSW) publisher: IEEE status: public title: Towards Dynamic Scripted pNFS Layouts type: conference user_id: '24135' year: '2012' ... --- _id: '2102' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Martin full_name: Wewior, Martin last_name: Wewior - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Bernd full_name: Schuller, Bernd last_name: Schuller - first_name: Johannes full_name: Schuster, Johannes last_name: Schuster - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: Ákos full_name: Balaskó, Ákos last_name: Balaskó - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Anna full_name: Szikszay Fabri, Anna last_name: Szikszay Fabri - first_name: Lars full_name: Packschies, Lars last_name: Packschies - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Gregor full_name: Fels, Gregor last_name: Fels - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: René full_name: Jäkel, René last_name: Jäkel - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher citation: ama: Gesing S, Grunzke R, Krüger J, et al. A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics. Journal of Grid Computing. 2012;10(4):769-790. doi:10.1007/s10723-012-9247-y apa: Gesing, S., Grunzke, R., Krüger, J., Birkenheuer, G., Wewior, M., Schäfer, P., … Kohlbacher, O. (2012). A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics. Journal of Grid Computing, 10(4), 769–790. https://doi.org/10.1007/s10723-012-9247-y bibtex: '@article{Gesing_Grunzke_Krüger_Birkenheuer_Wewior_Schäfer_Schuller_Schuster_Herres-Pawlis_Breuers_et al._2012, title={A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics}, volume={10}, DOI={10.1007/s10723-012-9247-y}, number={4}, journal={Journal of Grid Computing}, publisher={Springer}, author={Gesing, Sandra and Grunzke, Richard and Krüger, Jens and Birkenheuer, Georg and Wewior, Martin and Schäfer, Patrick and Schuller, Bernd and Schuster, Johannes and Herres-Pawlis, Sonja and Breuers, Sebastian and et al.}, year={2012}, pages={769–790} }' chicago: 'Gesing, Sandra, Richard Grunzke, Jens Krüger, Georg Birkenheuer, Martin Wewior, Patrick Schäfer, Bernd Schuller, et al. “A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics.” Journal of Grid Computing 10, no. 4 (2012): 769–90. https://doi.org/10.1007/s10723-012-9247-y.' ieee: S. Gesing et al., “A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics,” Journal of Grid Computing, vol. 10, no. 4, pp. 769–790, 2012. mla: Gesing, Sandra, et al. “A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics.” Journal of Grid Computing, vol. 10, no. 4, Springer, 2012, pp. 769–90, doi:10.1007/s10723-012-9247-y. short: S. Gesing, R. Grunzke, J. Krüger, G. Birkenheuer, M. Wewior, P. Schäfer, B. Schuller, J. Schuster, S. Herres-Pawlis, S. Breuers, Á. Balaskó, M. Kozlovszky, A. Szikszay Fabri, L. Packschies, P. Kacsuk, D. Blunk, T. Steinke, A. Brinkmann, G. Fels, R. Müller-Pfefferkorn, R. Jäkel, O. Kohlbacher, Journal of Grid Computing 10 (2012) 769–790. date_created: 2018-03-29T14:53:52Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1007/s10723-012-9247-y intvolume: ' 10' issue: '4' page: 769-790 publication: Journal of Grid Computing publisher: Springer status: public title: A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics type: journal_article user_id: '24135' volume: 10 year: '2012' ... --- _id: '2103' author: - first_name: Martin full_name: Wistuba, Martin last_name: Wistuba - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143' apa: Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143 bibtex: '@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }' chicago: Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143. ieee: M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99. mla: Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143. short: 'M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.' date_created: 2018-03-29T14:59:35Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' doi: 10.1109/CIG.2012.6374143 page: 91-99 publication: Proc. IEEE Conf. on Computational Intelligence and Games (CIG) publisher: IEEE status: public title: Comparison of Bayesian Move Prediction Systems for Computer Go type: conference user_id: '24135' year: '2012' ... --- _id: '2104' author: - first_name: Tobias full_name: Schlemmer, Tobias last_name: Schlemmer - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher citation: ama: 'Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012.' apa: Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn, R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways via Virtual Organizations. In Proc. EGI Technical Forum. bibtex: '@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012, title={Generic User Management for Science Gateways via Virtual Organizations}, booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke, Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn, Ralph and Kohlbacher, Oliver}, year={2012} }' chicago: Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer, Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum, 2012. ieee: T. Schlemmer et al., “Generic User Management for Science Gateways via Virtual Organizations,” in Proc. EGI Technical Forum, 2012. mla: Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via Virtual Organizations.” Proc. EGI Technical Forum, 2012. short: 'T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.' date_created: 2018-03-29T15:00:48Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' publication: Proc. EGI Technical Forum status: public title: Generic User Management for Science Gateways via Virtual Organizations type: conference user_id: '24135' year: '2012' ... --- _id: '2105' author: - first_name: Giuseppe full_name: Congiu, Giuseppe last_name: Congiu - first_name: Matthias full_name: Grawinkel, Matthias last_name: Grawinkel - first_name: Sai full_name: Narasimhamurthy, Sai last_name: Narasimhamurthy - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS). IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16' apa: 'Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012). One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16' bibtex: '@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services}, DOI={10.1109/ClusterW.2012.16}, booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }' chicago: 'Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.' ieee: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,” in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 2012, pp. 16–24.' mla: 'Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24, doi:10.1109/ClusterW.2012.16.' short: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24.' date_created: 2018-03-29T15:02:15Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/ClusterW.2012.16 page: 16-24 publication: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) publisher: IEEE status: public title: 'One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services' type: conference user_id: '24135' year: '2012' ... --- _id: '2107' author: - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Martin full_name: Kruse, Martin last_name: Kruse - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Bernd full_name: Schuller, Bernd last_name: Schuller - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Andreas full_name: Zink, Andreas last_name: Zink citation: ama: 'Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.' apa: Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit. bibtex: '@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc. UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012} }' chicago: Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway for Computational Workflows.” In Proc. UNICORE Summit, 2012. ieee: R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012. mla: Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012. short: 'R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.' date_created: 2018-03-29T15:06:46Z date_updated: 2022-01-06T06:54:44Z department: - _id: '27' - _id: '518' publication: Proc. UNICORE Summit status: public title: A Data Driven Science Gateway for Computational Workflows type: conference user_id: '24135' year: '2012' ... --- _id: '1789' author: - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Sascha full_name: Effert, Sascha last_name: Effert citation: ama: 'Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380' apa: Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380 bibtex: '@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha}, year={2012}, pages={1–12} }' chicago: Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380. ieee: J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2012, pp. 1–12. mla: Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12, doi:10.1109/MSST.2012.6232380. short: 'J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12.' date_created: 2018-03-26T15:12:01Z date_updated: 2022-01-06T06:53:22Z department: - _id: '27' doi: 10.1109/MSST.2012.6232380 page: 1-12 publication: Proc. Symp. on Mass Storage Systems and Technologies (MSST) publisher: IEEE status: public title: Design of an exact data deduplication cluster type: conference user_id: '24135' year: '2012' ... --- _id: '2171' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke citation: ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From National to International Scale. In: Proc. EGI Community Forum. ; 2012.' apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). The MoSGrid Community From National to International Scale. In Proc. EGI Community Forum. bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={The MoSGrid Community From National to International Scale}, booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }' chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “The MoSGrid Community From National to International Scale.” In Proc. EGI Community Forum, 2012. ieee: S. Gesing et al., “The MoSGrid Community From National to International Scale,” in Proc. EGI Community Forum, 2012. mla: Gesing, Sandra, et al. “The MoSGrid Community From National to International Scale.” Proc. EGI Community Forum, 2012. short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012.' date_created: 2018-04-03T09:01:19Z date_updated: 2022-01-06T06:55:11Z department: - _id: '27' publication: Proc. EGI Community Forum status: public title: The MoSGrid Community From National to International Scale type: conference user_id: '24135' year: '2012' ... --- _id: '2172' author: - first_name: Kris full_name: Thielemans, Kris last_name: Thielemans - first_name: Charalampos full_name: Tsoumpas, Charalampos last_name: Tsoumpas - first_name: Sanida full_name: Mustafovic, Sanida last_name: Mustafovic - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Pablo full_name: Aguiar, Pablo last_name: Aguiar - first_name: Nikolaos full_name: Dikaios, Nikolaos last_name: Dikaios - first_name: Matthew full_name: W Jacobson, Matthew last_name: W Jacobson citation: ama: 'Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867' apa: 'Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios, N., & W Jacobson, M. (2012). STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology, 57(4), 867–883. https://doi.org/10.1088/0031-9155/57/4/867' bibtex: '@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012, title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57}, DOI={10.1088/0031-9155/57/4/867}, number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing}, author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}, year={2012}, pages={867–883} }' chicago: 'Thielemans, Kris, Charalampos Tsoumpas, Sanida Mustafovic, Tobias Beisel, Pablo Aguiar, Nikolaos Dikaios, and Matthew W Jacobson. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology 57, no. 4 (2012): 867–83. https://doi.org/10.1088/0031-9155/57/4/867.' ieee: 'K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883, 2012.' mla: 'Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.' short: K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883. date_created: 2018-04-03T09:02:27Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' doi: 10.1088/0031-9155/57/4/867 intvolume: ' 57' issue: '4' page: 867-883 publication: Physics in Medicine and Biology publisher: IOP Publishing status: public title: 'STIR: Software for Tomographic Image Reconstruction Release 2' type: journal_article user_id: '24135' volume: 57 year: '2012' ... --- _id: '2173' author: - first_name: Soydan full_name: Redif, Soydan last_name: Redif - first_name: Server full_name: Kasap, Server last_name: Kasap citation: ama: Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343 apa: Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. Int. Journal of Electronics, 100(12), 1646–1651. https://doi.org/10.1080/00207217.2012.751343 bibtex: '@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }' chicago: 'Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100, no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.' ieee: S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012. mla: Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no. 12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343. short: S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651. date_created: 2018-04-03T09:05:36Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' doi: 10.1080/00207217.2012.751343 intvolume: ' 100' issue: '12' page: 1646-1651 publication: Int. Journal of Electronics publisher: Taylor & Francis status: public title: Parallel algorithm for computation of second-order sequential best rotations type: journal_article user_id: '24135' volume: 100 year: '2012' ... --- _id: '2174' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Khaled full_name: Benkrid, Khaled last_name: Benkrid citation: ama: Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328. apa: Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328. bibtex: '@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }' chicago: 'Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.' ieee: S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012. mla: Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28. short: S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328. date_created: 2018-04-03T09:08:00Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' intvolume: ' 7' issue: '6' page: 1312-1328 publication: Journal of Computers publisher: Academy Publishers status: public title: Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer type: journal_article user_id: '24135' volume: 7 year: '2012' ... --- _id: '2176' author: - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: René full_name: Jäkel, René last_name: Jäkel - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ines full_name: Dos Santos Vieira, Ines last_name: Dos Santos Vieira citation: ama: Herres-Pawlis S, Birkenheuer G, Brinkmann A, et al. Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway. Studies in Health Technology and Informatics. 2012;175:142-151. doi:10.3233/978-1-61499-054-3-142 apa: Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Gesing, S., Grunzke, R., Jäkel, R., … Dos Santos Vieira, I. (2012). Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway. Studies in Health Technology and Informatics, 175, 142–151. https://doi.org/10.3233/978-1-61499-054-3-142 bibtex: '@article{Herres-Pawlis_Birkenheuer_Brinkmann_Gesing_Grunzke_Jäkel_Kohlbacher_Krüger_Dos Santos Vieira_2012, title={Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway}, volume={175}, DOI={10.3233/978-1-61499-054-3-142}, journal={Studies in Health Technology and Informatics}, publisher={IOP Publishing}, author={Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Gesing, Sandra and Grunzke, Richard and Jäkel, René and Kohlbacher, Oliver and Krüger, Jens and Dos Santos Vieira, Ines}, year={2012}, pages={142–151} }' chicago: 'Herres-Pawlis, Sonja, Georg Birkenheuer, André Brinkmann, Sandra Gesing, Richard Grunzke, René Jäkel, Oliver Kohlbacher, Jens Krüger, and Ines Dos Santos Vieira. “Workflow-Enhanced Conformational Analysis of Guanidine Zinc Complexes via a Science Gateway.” Studies in Health Technology and Informatics 175 (2012): 142–51. https://doi.org/10.3233/978-1-61499-054-3-142.' ieee: S. Herres-Pawlis et al., “Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway,” Studies in Health Technology and Informatics, vol. 175, pp. 142–151, 2012. mla: Herres-Pawlis, Sonja, et al. “Workflow-Enhanced Conformational Analysis of Guanidine Zinc Complexes via a Science Gateway.” Studies in Health Technology and Informatics, vol. 175, IOP Publishing, 2012, pp. 142–51, doi:10.3233/978-1-61499-054-3-142. short: S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, S. Gesing, R. Grunzke, R. Jäkel, O. Kohlbacher, J. Krüger, I. Dos Santos Vieira, Studies in Health Technology and Informatics 175 (2012) 142–151. date_created: 2018-04-03T09:12:01Z date_updated: 2022-01-06T06:55:13Z department: - _id: '27' doi: 10.3233/978-1-61499-054-3-142 intvolume: ' 175' page: 142-151 publication: Studies in Health Technology and Informatics publisher: IOP Publishing status: public title: Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway type: journal_article user_id: '24135' volume: 175 year: '2012' ... --- _id: '2178' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke citation: ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.' apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050). bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }' chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012. ieee: S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050. mla: Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012. short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.' date_created: 2018-04-03T09:15:35Z date_updated: 2022-01-06T06:55:13Z department: - _id: '27' publication: Proceedings of Science status: public title: A Science Gateway Getting Ready for Serving the International Molecular Simulation Community type: conference user_id: '24135' volume: PoS(EGICF12-EMITC2)050 year: '2012' ... --- _id: '2106' abstract: - lang: eng text: "Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view." author: - first_name: Björn full_name: Meyer, Björn last_name: Meyer - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: 'Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370' apa: Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370 bibtex: '@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }' chicago: Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370. ieee: 'B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.' mla: Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370. short: 'B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.' conference: name: 22nd International Conference on Field Programmable Logic and Applicaitons (FPL) date_created: 2018-03-29T15:04:25Z date_updated: 2023-09-26T13:39:13Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '15' - _id: '78' doi: 10.1109/FPL.2012.6339370 file: - access_level: closed content_type: application/pdf creator: fossie date_created: 2019-02-13T09:04:46Z date_updated: 2019-02-13T09:04:46Z file_id: '7638' file_name: 2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf file_size: 2148787 relation: main_file success: 1 file_date_updated: 2019-02-13T09:04:46Z has_accepted_license: '1' keyword: - funding-upb-forschungspreis - funding-maxup - tet_topic_hpc language: - iso: eng page: 189-196 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? type: conference user_id: '15278' year: '2012' ... --- _id: '2108' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002' bibtex: '@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.' mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.' short: T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126. date_created: 2018-03-29T15:12:38Z date_updated: 2023-09-26T13:39:30Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2011.04.002 intvolume: ' 36' issue: '2' keyword: - funding-altera language: - iso: eng page: 110-126 publication: Microprocessors and Microsystems publication_identifier: issn: - 0141-9331 quality_controlled: '1' status: public title: 'IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators' type: journal_article user_id: '15278' volume: 36 year: '2012' ... --- _id: '615' abstract: - lang: eng text: Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745' apa: Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745 bibtex: '@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }' chicago: Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745. ieee: 'M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.' mla: Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745. short: 'M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.' date_created: 2017-10-17T12:42:51Z date_updated: 2023-09-26T13:42:26Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2012.6416745 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T06:48:32Z date_updated: 2018-03-15T06:48:32Z file_id: '1246' file_name: 615-ReConFig12_01.pdf file_size: 730144 relation: main_file success: 1 file_date_updated: 2018-03-15T06:48:32Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators type: conference user_id: '15278' year: '2012' ... --- _id: '591' abstract: - lang: eng text: One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz citation: ama: 'Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773' apa: Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773 bibtex: '@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }' chicago: Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773. ieee: 'T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.' mla: Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773. short: 'T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.' date_created: 2017-10-17T12:42:47Z date_updated: 2023-09-26T13:41:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2012.6416773 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:33:18Z date_updated: 2018-03-15T08:33:18Z file_id: '1257' file_name: 591-ReConFig2012Kenter_Schmitz_Plessl.pdf file_size: 371235 relation: main_file success: 1 file_date_updated: 2018-03-15T08:33:18Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Pragma based parallelization - Trading hardware efficiency for ease of use? type: conference user_id: '15278' year: '2012' ... --- _id: '609' abstract: - lang: eng text: Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.' apa: Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9. bibtex: '@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }' chicago: Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012. ieee: M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9. mla: Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9. short: 'M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.' date_created: 2017-10-17T12:42:50Z date_updated: 2023-09-26T13:41:36Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:14:17Z date_updated: 2018-03-15T08:14:17Z file_id: '1249' file_name: 609-happe12_fpl_awareness.pdf file_size: 146789 relation: main_file success: 1 file_date_updated: 2018-03-15T08:14:17Z has_accepted_license: '1' language: - iso: eng page: 8-9 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) quality_controlled: '1' status: public title: Hardware/Software Platform for Self-aware Compute Nodes type: conference user_id: '15278' year: '2012' ... --- _id: '567' abstract: - lang: eng text: Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. author: - first_name: Pablo full_name: Barrio, Pablo last_name: Barrio - first_name: Carlos full_name: Carreras, Carlos last_name: Carreras - first_name: Roberto full_name: Sierra, Roberto last_name: Sierra - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973' apa: 'Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973' bibtex: '@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }' chicago: 'Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.' ieee: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.' mla: 'Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.' short: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.' date_created: 2017-10-17T12:42:42Z date_updated: 2023-09-26T13:42:54Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/HPCSim.2012.6266973 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T10:20:24Z date_updated: 2018-03-15T10:20:24Z file_id: '1275' file_name: 567-ba-ca-12a.pdf file_size: 288508 relation: main_file success: 1 file_date_updated: 2018-03-15T10:20:24Z has_accepted_license: '1' language: - iso: eng page: 559-565 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) publisher: IEEE quality_controlled: '1' status: public title: 'Turning control flow graphs into function calls: Code generation for heterogeneous architectures' type: conference user_id: '15278' year: '2012' ...