---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1780'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Copolla, Marcello
last_name: Copolla
- first_name: Karim
full_name: Djafarian, Karim
last_name: Djafarian
- first_name: George
full_name: Koranaros, George
last_name: Koranaros
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Michele
full_name: Paolino, Michele
last_name: Paolino
- first_name: Oliver
full_name: Pell, Oliver
last_name: Pell
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource
management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38'
apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino,
M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE:
Towards efficient resource management in heterogeneous system architectures. Proc.
Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications
(ARC). https://doi.org/10.1007/978-3-319-05960-0_38'
bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D.
Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management
in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38},
booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools
and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and
Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio
and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio,
Marco and Bolchini, Cristiana}, year={2014} }'
chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros,
Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio,
and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous
System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures,
Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.'
ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management
in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.'
mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management
in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.'
short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino,
O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014.'
date_created: 2018-03-26T13:45:35Z
date_updated: 2023-09-26T13:36:20Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_38
language:
- iso: eng
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and
Applications (ARC)'
publisher: Springer
quality_controlled: '1'
status: public
title: 'SAVE: Towards efficient resource management in heterogeneous system architectures'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1779'
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain
Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture
News. 2014;41(5):65-70. doi:10.1145/2641361.2641372
apa: Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH
Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372
bibtex: '@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference
Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41},
DOI={10.1145/2641361.2641372},
number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM},
author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014},
pages={65–70} }'
chicago: 'Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite
Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM
SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.'
ieee: 'H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time
Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer
Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.'
mla: Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations
with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture
News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.
short: H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News
41 (2014) 65–70.
date_created: 2018-03-26T13:42:34Z
date_updated: 2023-09-26T13:35:58Z
department:
- _id: '27'
- _id: '518'
- _id: '61'
- _id: '78'
doi: 10.1145/2641361.2641372
intvolume: ' 41'
issue: '5'
keyword:
- funding-maxup
- tet_topic_hpc
language:
- iso: eng
page: 65-70
publication: ACM SIGARCH Computer Architecture News
publication_identifier:
issn:
- 0163-5964
publisher: ACM
quality_controlled: '1'
status: public
title: Accelerating Finite Difference Time Domain Simulations with Reconfigurable
Dataflow Computers
type: journal_article
user_id: '15278'
volume: 41
year: '2014'
...
---
_id: '1784'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Viktor
full_name: Gottfried, Viktor
last_name: Gottfried
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download
Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture
and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97.
doi:10.1109/NAS.2013.18'
apa: 'Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming
the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking,
Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer
Society. https://doi.org/10.1109/NAS.2013.18'
bibtex: '@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington
DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers},
DOI={10.1109/NAS.2013.18}, booktitle={Proc.
IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE
Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor
and Brinkmann, André}, year={2013}, pages={88–97} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD:
Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int.
Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC,
USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.'
ieee: 'J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the
Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking,
Architecture and Storage (NAS), 2013, pp. 88–97.'
mla: 'Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data
Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS),
IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.'
short: 'J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington
DC, USA, 2013, pp. 88–97.'
date_created: 2018-03-26T14:43:38Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
doi: 10.1109/NAS.2013.18
page: 88-97
place: Washington DC, USA
publication: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)
publisher: IEEE Computer Society
status: public
title: 'MCD: Overcoming the Data Download Bottleneck in Data Centers'
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1786'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind
Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530'
apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530},
booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE},
author={Kasap, Server and Redif, Soydan}, year={2013} }'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing
and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.
ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications
Conf. (SUI), 2013.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013.'
date_created: 2018-03-26T14:48:53Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/SIU.2013.6531530
publication: Proc. IEEE Signal Processing and Communications Conf. (SUI)
publisher: IEEE
status: public
title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1788'
author:
- first_name: Petra
full_name: Berenbrink, Petra
last_name: Berenbrink
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Tom
full_name: Friedetzky, Tom
last_name: Friedetzky
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Lars
full_name: Nagel, Lars
last_name: Nagel
citation:
ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing
Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148'
apa: Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L.
(2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148
bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing
Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky,
Tom and Meister, Dirk and Nagel, Lars}, year={2013} }'
chicago: Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars
Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148.
ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing
Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013.
mla: Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc.
Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE,
2013, doi:10.1109/IPDPSW.2013.148.
short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc.
Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.'
date_created: 2018-03-26T14:52:56Z
date_updated: 2022-01-06T06:53:22Z
department:
- _id: '27'
doi: 10.1109/IPDPSW.2013.148
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publisher: IEEE
status: public
title: Distributing Storage in Cloud Environments
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1790'
author:
- first_name: Oliver
full_name: Niehörster, Oliver
last_name: Niehörster
citation:
ama: 'Niehörster O. Autonomous Resource Management in Dynamic Data Centers.
Aachen, Germany: Shaker; 2013.'
apa: 'Niehörster, O. (2013). Autonomous Resource Management in Dynamic Data Centers.
Aachen, Germany: Shaker.'
bibtex: '@book{Niehörster_2013, place={Aachen, Germany}, title={Autonomous Resource
Management in Dynamic Data Centers}, publisher={Shaker}, author={Niehörster, Oliver},
year={2013} }'
chicago: 'Niehörster, Oliver. Autonomous Resource Management in Dynamic Data
Centers. Aachen, Germany: Shaker, 2013.'
ieee: 'O. Niehörster, Autonomous Resource Management in Dynamic Data Centers.
Aachen, Germany: Shaker, 2013.'
mla: Niehörster, Oliver. Autonomous Resource Management in Dynamic Data Centers.
Shaker, 2013.
short: O. Niehörster, Autonomous Resource Management in Dynamic Data Centers, Shaker,
Aachen, Germany, 2013.
date_created: 2018-03-26T15:12:56Z
date_updated: 2022-01-06T06:53:22Z
department:
- _id: '27'
place: Aachen, Germany
publication_identifier:
isbn:
- 978-3-8440-1735-9
publisher: Shaker
status: public
title: Autonomous Resource Management in Dynamic Data Centers
type: book
user_id: '24135'
year: '2013'
...
---
_id: '1791'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
citation:
ama: Meister D. Advanced Data Deduplication Techniques and Their Application.
Johannes Gutenberg-Universität Mainz; 2013.
apa: Meister, D. (2013). Advanced Data Deduplication Techniques and Their Application.
Johannes Gutenberg-Universität Mainz.
bibtex: '@book{Meister_2013, title={Advanced Data Deduplication Techniques and Their
Application}, publisher={Johannes Gutenberg-Universität Mainz}, author={Meister,
Dirk}, year={2013} }'
chicago: Meister, Dirk. Advanced Data Deduplication Techniques and Their Application.
Johannes Gutenberg-Universität Mainz, 2013.
ieee: D. Meister, Advanced Data Deduplication Techniques and Their Application.
Johannes Gutenberg-Universität Mainz, 2013.
mla: Meister, Dirk. Advanced Data Deduplication Techniques and Their Application.
Johannes Gutenberg-Universität Mainz, 2013.
short: D. Meister, Advanced Data Deduplication Techniques and Their Application,
Johannes Gutenberg-Universität Mainz, 2013.
date_created: 2018-03-26T15:13:49Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
publisher: Johannes Gutenberg-Universität Mainz
status: public
title: Advanced Data Deduplication Techniques and Their Application
type: dissertation
user_id: '24135'
year: '2013'
...
---
_id: '1792'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing
the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans
on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069
apa: Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3),
522–536. https://doi.org/10.1109/TVLSI.2013.2248069
bibtex: '@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices},
volume={22}, DOI={10.1109/TVLSI.2013.2248069},
number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems},
publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536}
}'
chicago: 'Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array
Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial
Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22,
no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.'
ieee: S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for
Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, pp. 522–536, 2013.
mla: Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture
for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.”
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no.
3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069.
short: S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems
22 (2013) 522–536.
date_created: 2018-03-26T15:15:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/TVLSI.2013.2248069
intvolume: ' 22'
issue: '3'
page: 522-536
publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems
publisher: IEEE
status: public
title: Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue
Decomposition of Para-Hermitian Polynomial Matrices
type: journal_article
user_id: '24135'
volume: 22
year: '2013'
...
---
_id: '1793'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
citation:
ama: 'Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication
Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST).
USENIX Association; 2013:175-182.'
apa: Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in
Data Deduplication Systems. In Proc. USENIX Conference on File and Storage
Technologies (FAST) (pp. 175–182). USENIX Association.
bibtex: '@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression
in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and
Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister,
Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }'
chicago: Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in
Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage
Technologies (FAST), 175–82. USENIX Association, 2013.
ieee: D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication
Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST),
2013, pp. 175–182.
mla: Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.”
Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX
Association, 2013, pp. 175–82.
short: 'D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and
Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.'
date_created: 2018-03-26T15:16:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
page: 175-182
publication: Proc. USENIX Conference on File and Storage Technologies (FAST)
publisher: USENIX Association
status: public
title: File Recipe Compression in Data Deduplication Systems
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '528'
abstract:
- lang: eng
text: Cold-boot attacks exploit the fact that DRAM contents are not immediately
lost when a PC is powered off. Instead the contents decay rather slowly, in particular
if the DRAM chips are cooled to low temperatures. This effect opens an attack
vector on cryptographic applications that keep decrypted keys in DRAM. An attacker
with access to the target computer can reboot it or remove the RAM modules and
quickly copy the RAM contents to non-volatile memory. By exploiting the known
cryptographic structure of the cipher and layout of the key data in memory, in
our application an AES key schedule with redundancy, the resulting memory image
can be searched for sections that could correspond to decayed cryptographic keys;
then, the attacker can attempt to reconstruct the original key. However, the runtime
of these algorithms grows rapidly with increasing memory image size, error rate
and complexity of the bit error model, which limits the practicability of the
approach.In this work, we study how the algorithm for key search can be accelerated
with custom computing machines. We present an FPGA-based architecture on a Maxeler
dataflow computing system that outperforms a software implementation up to 205x,
which significantly improves the practicability of cold-attacks against AES.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot
Attacks against AES. In: Proceedings of the International Conference on Field-Programmable
Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394'
apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated
Key Search for Cold-Boot Attacks against AES. Proceedings of the International
Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394
bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated
Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge,
Christoph and Plessl, Christian}, year={2013}, pages={386–389} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl.
“FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT), 386–89.
IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.
ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search
for Cold-Boot Attacks against AES,” in Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.'
mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks
against AES.” Proceedings of the International Conference on Field-Programmable
Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.'
date_created: 2017-10-17T12:42:35Z
date_updated: 2023-09-26T13:37:35Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2013.6718394
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:36:08Z
date_updated: 2018-03-15T10:36:08Z
file_id: '1294'
file_name: 528-plessl13_fpt.pdf
file_size: 822680
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:36:08Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 386-389
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '13'
name: SFB 901 - Subproject C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '505'
abstract:
- lang: eng
text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT
services that will be provided by assembling modular software components available
on world-wide markets. After suitable components have been found, they are automatically
integrated, configured and brought to execution in an On-The-Fly Compute Center.
We envision that these future compute centers will continue to leverage three
current trends in large scale computing which are an increasing amount of parallel
processing, a trend to use heterogeneous computing resources, and—in the light
of rising energy cost—energy-efficiency as a primary goal in the design and operation
of computing systems. In this paper, we point out three research challenges and
our current work in these areas.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
citation:
ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings
of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous
Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232'
apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide,
F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232'
bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232},
booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus
and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide,
Friedhelm}, year={2013} }'
chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm
Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology
for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.'
ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.'
mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for
Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.'
short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in:
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS), IEEE, 2013.'
date_created: 2017-10-17T12:42:30Z
date_updated: 2023-09-26T13:38:20Z
ddc:
- '040'
department:
- _id: '63'
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISORC.2013.6913232
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T13:38:56Z
date_updated: 2018-03-15T13:38:56Z
file_id: '1308'
file_name: 505-Plessl13_seus.pdf
file_size: 1040834
relation: main_file
success: 1
file_date_updated: 2018-03-15T13:38:56Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services'
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '1787'
author:
- first_name: Tim
full_name: Suess, Tim
last_name: Suess
- first_name: Andrew
full_name: Schoenrock, Andrew
last_name: Schoenrock
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the
Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136'
apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro
Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel
and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136
bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington,
DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer},
DOI={10.1109/IPDPSW.2013.136},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and
Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }'
chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl.
“Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int.
Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington,
DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.'
ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining
on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.'
mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.”
Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW),
IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.
short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society,
Washington, DC, USA, 2013, pp. 64–73.'
date_created: 2018-03-26T14:51:05Z
date_updated: 2023-09-26T13:38:05Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
- _id: '63'
doi: 10.1109/IPDPSW.2013.136
language:
- iso: eng
page: 64-73
place: Washington, DC, USA
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publication_identifier:
isbn:
- 978-0-7695-4979-8
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '1965'
abstract:
- lang: eng
text: Virtualization technology makes data centers more dynamic and easier to administrate.
Today, cloud providers offer customers access to complex applications running
on virtualized hardware. Nevertheless, big virtualized data centers become stochastic
environments and the simplification on the user side leads to many challenges
for the provider. He has to find cost-efficient configurations and has to deal
with dynamic environments to ensure service level objectives (SLOs). We introduce
a software solution that reduces the degree of human intervention to manage clouds.
It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure
as a Service (IaaS) layer. Worker agents allocate resources, configure applications,
check the feasibility of requests, and generate cost estimates. They are equipped
with application specific knowledge allowing it to estimate the type and number
of necessary resources. During runtime, a worker agent monitors the job and adapts
its resources to ensure the specified quality of service—even in noisy clouds
where the job instances are influenced by other jobs. They interact with a scheduler
agent, which takes care of limited resources and does a cost-aware scheduling
by assigning jobs to times with low costs. The whole architecture is self-optimizing
and able to use public or private clouds. Building a private cloud needs to face
the challenge to find a mapping of virtual machines (VMs) to hosts. We present
a rule-based mapping algorithm for VMs. It offers an interface where policies
can be defined and combined in a generic way. The algorithm performs the initial
mapping at request time as well as a remapping during runtime. It deals with policy
and infrastructure changes. An energy-aware scheduler and the availability of
cheap resources provided by a spot market are analyzed. We evaluated our approach
by building up an SaaS stack, which assigns resources in consideration of an energy
function and that ensures SLOs of two different applications, a brokerage system
and a high-performance computing software. Experiments were done on a real cloud
system and by simulations.
author:
- first_name: Oliver
full_name: Niehörster, Oliver
last_name: Niehörster
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Axel
full_name: Keller, Axel
id: '15274'
last_name: Keller
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
citation:
ama: Niehörster O, Simon J, Brinkmann A, Keller A, Krüger J. Cost-aware and SLO
Fulfilling Software as a Service. Journal of Grid Computing. 2012;10(3):553-577.
doi:10.1007/s10723-012-9230-7
apa: Niehörster, O., Simon, J., Brinkmann, A., Keller, A., & Krüger, J. (2012).
Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing,
10(3), 553–577. https://doi.org/10.1007/s10723-012-9230-7
bibtex: '@article{Niehörster_Simon_Brinkmann_Keller_Krüger_2012, title={Cost-aware
and SLO Fulfilling Software as a Service}, volume={10}, DOI={10.1007/s10723-012-9230-7},
number={3}, journal={Journal of Grid Computing}, author={Niehörster, Oliver and
Simon, Jens and Brinkmann, André and Keller, Axel and Krüger, Jens}, year={2012},
pages={553–577} }'
chicago: 'Niehörster, Oliver, Jens Simon, André Brinkmann, Axel Keller, and Jens
Krüger. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid
Computing 10, no. 3 (2012): 553–77. https://doi.org/10.1007/s10723-012-9230-7.'
ieee: O. Niehörster, J. Simon, A. Brinkmann, A. Keller, and J. Krüger, “Cost-aware
and SLO Fulfilling Software as a Service,” Journal of Grid Computing, vol.
10, no. 3, pp. 553–577, 2012.
mla: Niehörster, Oliver, et al. “Cost-Aware and SLO Fulfilling Software as a Service.”
Journal of Grid Computing, vol. 10, no. 3, 2012, pp. 553–77, doi:10.1007/s10723-012-9230-7.
short: O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid
Computing 10 (2012) 553–577.
date_created: 2018-03-29T11:16:18Z
date_updated: 2022-01-06T06:54:09Z
department:
- _id: '27'
doi: 10.1007/s10723-012-9230-7
intvolume: ' 10'
issue: '3'
language:
- iso: eng
page: 553-577
publication: Journal of Grid Computing
publication_status: published
status: public
title: Cost-aware and SLO Fulfilling Software as a Service
type: journal_article
user_id: '15274'
volume: 10
year: '2012'
...
---
_id: '2097'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial
matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology
(ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125'
apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of
an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field
Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation
of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation
of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on
Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012.
https://doi.org/10.1109/FPT.2012.6412125.
ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate
polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable
Technology (ICFPT), 2012, pp. 135–140.
mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an
Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.
short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2012, pp. 135–140.'
date_created: 2018-03-29T14:34:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/FPT.2012.6412125
page: 135-140
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: FPGA-based design and implementation of an approximate polynomial matrix EVD
algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2098'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Tim
full_name: Hartung, Tim
last_name: Hartung
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device.
In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS).
IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34'
apa: 'Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2
Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems
(ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34'
bibtex: '@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2
Split Block Device}, DOI={10.1109/ICPADS.2012.34},
booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)},
publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and
Brinkmann, André}, year={2012}, pages={181–188} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB:
Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed
Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.'
ieee: 'J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block
Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS),
2012, pp. 181–188.'
mla: 'Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int.
Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88,
doi:10.1109/ICPADS.2012.34.'
short: 'J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.'
date_created: 2018-03-29T14:40:04Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/ICPADS.2012.34
page: 181-188
publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)
publisher: IEEE
status: public
title: 'ESB: Ext2 Split Block Device'
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2099'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Michael
full_name: Kuhn, Michael
last_name: Kuhn
- first_name: Julian
full_name: Kunkel, Julian
last_name: Kunkel
- first_name: Toni
full_name: Cortes, Toni
last_name: Cortes
citation:
ama: 'Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data
Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing
(SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14'
apa: 'Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes,
T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int.
Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer
Society. https://doi.org/10.1109/SC.2012.14'
bibtex: '@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los
Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems},
DOI={10.1109/SC.2012.14}, booktitle={Proc.
Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister,
Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian
and Cortes, Toni}, year={2012}, pages={7:1-7:11} }'
chicago: 'Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel,
and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc.
Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer
Society, 2012. https://doi.org/10.1109/SC.2012.14.'
ieee: D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A
Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on
Supercomputing (SC), 2012, pp. 7:1-7:11.
mla: Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.”
Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp.
7:1-7:11, doi:10.1109/SC.2012.14.
short: 'D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in:
Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos,
CA, USA, 2012, pp. 7:1-7:11.'
date_created: 2018-03-29T14:41:55Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/SC.2012.14
page: 7:1-7:11
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on Supercomputing (SC)
publisher: IEEE Computer Society
status: public
title: A Study on Data Deduplication in HPC Storage Systems
type: conference
user_id: '24135'
year: '2012'
...