@inproceedings{2236, author = {{Birkenheuer, Georg and Breuers, Sebastian and Brinkmann, André and Blunk, Dirk and Fels, Gregor and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Packschies, Lars}}, booktitle = {{Proc. of Grid Workflow Workshop (GWW)}}, pages = {{177--184}}, publisher = {{Gesellschaft für Informatik (GI)}}, title = {{{Grid-Workflows in Molecular Science}}}, year = {{2010}}, } @inproceedings{2231, author = {{Lensing, Paul Hermann and Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI)}}, pages = {{33--42}}, publisher = {{IEEE}}, title = {{{hashFS: Applying Hashing to Optimized File Systems for Small File Reads}}}, doi = {{10.1109/SNAPI.2010.12}}, year = {{2010}}, } @inproceedings{2234, author = {{Bolte, Matthias and Sievers, Michael and Birkenheuer, Georg and Niehörster, Oliver and Brinkmann, André}}, booktitle = {{Proc. Design, Automation and Test in Europe Conf. (DATE)}}, publisher = {{EDA Consortium}}, title = {{{Non-intrusive Virtualization Management Using libvirt}}}, year = {{2010}}, } @inproceedings{2228, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}}, editor = {{Hammami, Omar and Larrabee, Sandra}}, title = {{{Performance Estimation for the Exploration of CPU-Accelerator Architectures}}}, year = {{2010}}, } @inproceedings{2216, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{67--72}}, publisher = {{IEEE Computer Society}}, title = {{{Pruning the Design Space for Just-In-Time Processor Customization}}}, doi = {{10.1109/ReConFig.2010.19}}, year = {{2010}}, } @inproceedings{2206, author = {{Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}}, booktitle = {{Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}}, isbn = {{978-1-4244-8864-3}}, pages = {{372--376}}, publisher = {{IEEE}}, title = {{{Reconfigurable Nodes for Future Networks}}}, doi = {{10.1109/GLOCOMW.2010.5700341}}, year = {{2010}}, } @inproceedings{2225, author = {{Gao, Yan and Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}}, pages = {{126--134}}, publisher = {{IEEE}}, title = {{{Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors}}}, doi = {{10.1109/NAS.2010.11}}, year = {{2010}}, } @inproceedings{809, author = {{Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}}, booktitle = {{Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers}}, pages = {{51--76}}, title = {{{Risk Aware Overbooking for Commercial Grids}}}, doi = {{10.1007/978-3-642-16505-4_4}}, year = {{2010}}, } @inproceedings{2227, author = {{Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}}, booktitle = {{Proc. Int. Conf. Networked Sensing Systems (INSS)}}, isbn = {{978-1-4244-7911-5}}, pages = {{245--248}}, publisher = {{IEEE}}, title = {{{Rupeas: Ruby Powered Event Analysis DSL}}}, doi = {{10.1109/INSS.2010.5572211}}, year = {{2010}}, } @inproceedings{2217, author = {{Bienkowski, Marcin and Brinkmann, André and Klonowski, Marek and Korzeniowski, Miroslaw}}, booktitle = {{Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis)}}, publisher = {{Springer}}, title = {{{SkewCCC+: A Heterogeneous Distributed Hash Table}}}, doi = {{10.1007/978-3-642-17653-1_18}}, volume = {{6490}}, year = {{2010}}, } @inproceedings{2218, author = {{Wewior, Martin and Packschies, Lars and Blunk, Dirk and Wickeroth, Daniel and Warzecha, Klaus-Dieter and Herres-Pawlis, Sonja and Gesing, Sandra and Breuers, Sebastian and Krüger, Jens and Birkenheuer, Georg and Lang, Ulrich}}, booktitle = {{Proc. Int. Workshop on Scientific Gateways (IWSG)}}, pages = {{39--43}}, publisher = {{Consorzio COMETA}}, title = {{{The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations}}}, year = {{2010}}, } @inproceedings{2223, author = {{Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{225--231}}, publisher = {{CSREA Press}}, title = {{{Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}}}, year = {{2010}}, } @inproceedings{2226, author = {{Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, isbn = {{978-1-4244-6965-9}}, pages = {{65--72}}, publisher = {{IEEE Computer Society}}, title = {{{Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}}}, doi = {{10.1109/ASAP.2010.5540798}}, year = {{2010}}, } @inproceedings{2219, author = {{Gesing, Sandra and Marton, Istvan and Birkenheuer, Georg and Schuller, Bernd and Grunzke, Richard and Krüger, Jens and Breuers, Sebastian and Blunk, Dirk and Fels, Gregor and Packschies, Lars and Brinkmann, André and Kohlbacher, Oliver and Kozlovszky, Miklos}}, booktitle = {{Proc. Int. Workshop on Scientific Gateways (IWSG)}}, pages = {{44--48}}, publisher = {{Consorzio COMETA}}, title = {{{Workflow Interoperability in a Grid Portal for Molecular Simulations}}}, year = {{2010}}, } @inproceedings{2261, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, isbn = {{978-1-4244-3892-1}}, issn = {{1946-1488}}, keywords = {{IMORC, NOC, KNN, accelerator}}, pages = {{338--344}}, publisher = {{IEEE}}, title = {{{An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}}}, year = {{2009}}, } @inproceedings{2239, author = {{Höing, Andre and Scherp, Guido and Gudenkauf, Stefan and Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Service Oriented Computing (ICSOC)}}, pages = {{301--315}}, publisher = {{Springer}}, title = {{{An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL}}}, doi = {{0.1007/978-3-642-10383-4_20}}, volume = {{5900}}, year = {{2009}}, } @inproceedings{2238, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{978-0-7695-3917-1}}, keywords = {{IMORC, graphics}}, pages = {{119--124}}, publisher = {{IEEE Computer Society}}, title = {{{Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}}}, doi = {{10.1109/ReConFig.2009.32}}, year = {{2009}}, } @inproceedings{2260, author = {{Birkenheuer, Georg and Carlson, Arthur and Fölling, Alexander and Högqvist, Mikael and Hoheisel, Andreas and Papaspyrou, Alexander and Rieger, Klaus and Schott, Bernhard and Ziegler, Wolfgang}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, isbn = {{978-83-61433-01-9}}, pages = {{96--103}}, title = {{{Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!}}}, year = {{2009}}, } @inproceedings{2262, abstract = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }}, author = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}}, keywords = {{EvoCache, evolvable hardware, computer architecture}}, pages = {{11--18}}, publisher = {{IEEE Computer Society}}, title = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}}, year = {{2009}}, } @inproceedings{2350, abstract = {{Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. }}, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, isbn = {{978-1-4244-4450-2}}, keywords = {{IMORC, interconnect, performance}}, pages = {{275--278}}, publisher = {{IEEE Computer Society}}, title = {{{IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}}}, doi = {{10.1109/FCCM.2009.25}}, year = {{2009}}, }